luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Sta::portExtCaps

This commit is contained in:
James Cherry 2021-04-02 16:05:57 -07:00
parent e10258d9e5
commit edeba84c36
3 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
search/Sta.cc
View File

@ -1293,8 +1293,7 @@ Sta::removeClockUncertainty(Clock *from_clk,
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold)
{
sdc_->removeClockUncertainty(from_clk, from_rf, to_clk, to_rf,
setup_hold);
sdc_->removeClockUncertainty(from_clk, from_rf, to_clk, to_rf, setup_hold);
search_->arrivalsInvalid();
}
@ -1972,8 +1971,7 @@ Sta::makeGroupPath(const char *name,
ExceptionTo *to,
const char *comment)
{
sdc_->makeGroupPath(name, is_default, from, thrus, to,
comment);
sdc_->makeGroupPath(name, is_default, from, thrus, to, comment);
search_->arrivalsInvalid();
}
@ -3427,6 +3425,9 @@ Sta::portExtCaps(Port *port,
bool pin_exists = false;
bool wire_exists = false;
bool fanout_exists = false;
pin_cap = min_max->initValue();
wire_cap = min_max->initValue();
fanout = min_max->initValue();
for (RiseFall *rf : RiseFall::range()) {
float pin_cap1, wire_cap1;
int fanout1;

5
tcl/Network.tcl
View File

@ -396,9 +396,8 @@ proc report_net_pin { pin verbose corner digits } {
set wire_cap " wire [capacitance_range_str $cap_min $cap_max $digits]"
}
set port [$pin port]
set cap_r_min [port_ext_pin_cap $port "min"]
set cap_r_max [port_ext_pin_cap $port "max"]
set cap_min [port_ext_pin_cap $port "min"]
set cap_max [port_ext_pin_cap $port "max"]
if { $cap_min > 0 || $cap_max > 0} {
set pin_cap " pin [capacitance_range_str $cap_min $cap_max $digits]"
}

18
test/example4.ok
View File

@ -9,21 +9,21 @@ Path Type: max
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ r2/CK (DFF_X1)
2.58 2.58 ^ r2/Q (DFF_X1)
2.59 5.17 ^ u1/Z (BUF_X1)
2.77 7.95 ^ u2/ZN (AND2_X1)
0.00 7.95 ^ r3/D (DFF_X1)
7.95 data arrival time
2.58 5.16 ^ u1/Z (BUF_X1)
2.75 7.91 ^ u2/ZN (AND2_X1)
0.00 7.92 ^ r3/D (DFF_X1)
7.92 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ r3/CK (DFF_X1)
-0.61 9.39 library setup time
9.39 data required time
-0.57 9.43 library setup time
9.43 data required time
---------------------------------------------------------
9.39 data required time
-7.95 data arrival time
9.43 data required time
-7.92 data arrival time
---------------------------------------------------------
1.45 slack (MET)
1.52 slack (MET)