luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sic 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-01-08 18:02:01 -07:00
parent e0024709f4
commit ebb0a5d060
7 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
dcalc/ArnoldiDelayCalc.cc
View File

@ -257,7 +257,7 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
{ {
Parasitic *parasitic = nullptr; Parasitic *parasitic = nullptr;
const Corner *corner = dcalc_ap->corner(); const Corner *corner = dcalc_ap->corner();
// set_load net has precidence over parasitics. // set_load net has precedence over parasitics.
if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) { if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
Parasitic *parasitic_network = Parasitic *parasitic_network =

2
dcalc/DmpDelayCalc.cc
View File

@ -208,7 +208,7 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
{ {
Parasitic *parasitic = nullptr; Parasitic *parasitic = nullptr;
const Corner *corner = dcalc_ap->corner(); const Corner *corner = dcalc_ap->corner();
// set_load net has precidence over parasitics. // set_load net has precedence over parasitics.
if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) { if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
if (parasitics_->haveParasitics()) { if (parasitics_->haveParasitics()) {

2
dcalc/GraphDelayCalc.cc
View File

@ -1205,7 +1205,7 @@ GraphDelayCalc::loadCap(const Parasitic *parasitic,
float &pin_cap, float &pin_cap,
float &wire_cap) const float &wire_cap) const
{ {
// set_load net has precidence over parasitics. // set_load net has precedence over parasitics.
if (!has_net_load && parasitic) { if (!has_net_load && parasitic) {
if (parasitics_->isParasiticNetwork(parasitic)) if (parasitics_->isParasiticNetwork(parasitic))
wire_cap += parasitics_->capacitance(parasitic); wire_cap += parasitics_->capacitance(parasitic);

2
dcalc/LumpedCapDelayCalc.cc
View File

@ -57,7 +57,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
{ {
Parasitic *parasitic = nullptr; Parasitic *parasitic = nullptr;
const Corner *corner = dcalc_ap->corner(); const Corner *corner = dcalc_ap->corner();
// set_load net has precidence over parasitics. // set_load net has precedence over parasitics.
if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) { if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt(); const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
if (parasitics_->haveParasitics()) { if (parasitics_->haveParasitics()) {

4
include/sta/Sdc.hh
View File

@ -267,7 +267,7 @@ public:
float limit); float limit);
void setLatchBorrowLimit(const Clock *clk, void setLatchBorrowLimit(const Clock *clk,
float limit); float limit);
// Return the latch borrow limit respecting precidence if multiple // Return the latch borrow limit respecting precedence if multiple
// limits apply. // limits apply.
void latchBorrowLimit(const Pin *data_pin, void latchBorrowLimit(const Pin *data_pin,
const Pin *enable_pin, const Pin *enable_pin,
@ -286,7 +286,7 @@ public:
void setMinPulseWidth(const Clock *clk, void setMinPulseWidth(const Clock *clk,
const RiseFallBoth *rf, const RiseFallBoth *rf,
float min_width); float min_width);
// Return min pulse with respecting precidence. // Return min pulse with respecting precedence.
void minPulseWidth(const Pin *pin, void minPulseWidth(const Pin *pin,
const Clock *clk, const Clock *clk,
const RiseFall *hi_low, const RiseFall *hi_low,

2
search/Search.cc
View File

@ -2468,7 +2468,7 @@ Search::thruClkInfo(PathVertex *from_path,
sdc_->clockLatency(from_clk, to_pin, clk_rf, min_max, sdc_->clockLatency(from_clk, to_pin, clk_rf, min_max,
latency, exists); latency, exists);
if (exists) { if (exists) {
// Latency on pin has precidence over fanin or hierarchical // Latency on pin has precedence over fanin or hierarchical
// pin latency. // pin latency.
to_latency = latency; to_latency = latency;
to_clk_prop = false; to_clk_prop = false;

2
search/VisitPathEnds.cc
View File

@ -97,7 +97,7 @@ VisitPathEnds::visitClkedPathEnds(const Pin *pin,
// Ignore segment startpoint paths. // Ignore segment startpoint paths.
&& (!is_segment_start && (!is_segment_start
|| !tag->isSegmentStart())) { || !tag->isSegmentStart())) {
// set_output_delay to timing check has precidence. // set_output_delay to timing check has precedence.
if (sdc_->hasOutputDelay(pin)) if (sdc_->hasOutputDelay(pin))
visitOutputDelayEnd(pin, path, end_rf, path_ap, filtered, visitor, visitOutputDelayEnd(pin, path, end_rf, path_ap, filtered, visitor,
is_constrained); is_constrained);