parent
e0024709f4
commit
ebb0a5d060
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@ -257,7 +257,7 @@ ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
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{
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Parasitic *parasitic = nullptr;
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const Corner *corner = dcalc_ap->corner();
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// set_load net has precidence over parasitics.
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// set_load net has precedence over parasitics.
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if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
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const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
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Parasitic *parasitic_network =
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@ -208,7 +208,7 @@ DmpCeffTwoPoleDelayCalc::findParasitic(const Pin *drvr_pin,
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{
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Parasitic *parasitic = nullptr;
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const Corner *corner = dcalc_ap->corner();
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// set_load net has precidence over parasitics.
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// set_load net has precedence over parasitics.
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if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
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const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
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if (parasitics_->haveParasitics()) {
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@ -1205,7 +1205,7 @@ GraphDelayCalc::loadCap(const Parasitic *parasitic,
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float &pin_cap,
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float &wire_cap) const
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{
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// set_load net has precidence over parasitics.
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// set_load net has precedence over parasitics.
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if (!has_net_load && parasitic) {
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if (parasitics_->isParasiticNetwork(parasitic))
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wire_cap += parasitics_->capacitance(parasitic);
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@ -57,7 +57,7 @@ LumpedCapDelayCalc::findParasitic(const Pin *drvr_pin,
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{
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Parasitic *parasitic = nullptr;
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const Corner *corner = dcalc_ap->corner();
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// set_load net has precidence over parasitics.
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// set_load net has precedence over parasitics.
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if (!sdc_->drvrPinHasWireCap(drvr_pin, corner)) {
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const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
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if (parasitics_->haveParasitics()) {
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@ -267,7 +267,7 @@ public:
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float limit);
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void setLatchBorrowLimit(const Clock *clk,
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float limit);
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// Return the latch borrow limit respecting precidence if multiple
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// Return the latch borrow limit respecting precedence if multiple
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// limits apply.
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void latchBorrowLimit(const Pin *data_pin,
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const Pin *enable_pin,
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@ -286,7 +286,7 @@ public:
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void setMinPulseWidth(const Clock *clk,
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const RiseFallBoth *rf,
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float min_width);
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// Return min pulse with respecting precidence.
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// Return min pulse with respecting precedence.
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void minPulseWidth(const Pin *pin,
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const Clock *clk,
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const RiseFall *hi_low,
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@ -2468,7 +2468,7 @@ Search::thruClkInfo(PathVertex *from_path,
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sdc_->clockLatency(from_clk, to_pin, clk_rf, min_max,
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latency, exists);
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if (exists) {
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// Latency on pin has precidence over fanin or hierarchical
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// Latency on pin has precedence over fanin or hierarchical
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// pin latency.
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to_latency = latency;
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to_clk_prop = false;
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@ -97,7 +97,7 @@ VisitPathEnds::visitClkedPathEnds(const Pin *pin,
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// Ignore segment startpoint paths.
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&& (!is_segment_start
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|| !tag->isSegmentStart())) {
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// set_output_delay to timing check has precidence.
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// set_output_delay to timing check has precedence.
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if (sdc_->hasOutputDelay(pin))
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visitOutputDelayEnd(pin, path, end_rf, path_ap, filtered, visitor,
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is_constrained);
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