Merge remote-tracking branch 'parallax/master'
This commit is contained in:
commit
eb8ab089df
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@ -12,18 +12,20 @@ AllowShortLoopsOnASingleLine: false
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AlwaysBreakAfterReturnType: TopLevel
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AlwaysBreakAfterReturnType: TopLevel
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BinPackArguments: false
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BinPackArguments: false
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# fails
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# fails
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BinPackParameters: false
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BinPackParameters: AlwaysOnePerLine
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BraceWrapping:
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BraceWrapping:
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AfterClass: true
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AfterClass: true
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AfterStruct: true
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AfterStruct: true
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AfterFunction: true
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AfterFunction: true
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BeforeElse: true
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BeforeElse: true
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BreakBeforeBinaryOperators: NonAssignment
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BreakBeforeBraces: Custom
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BreakBeforeBraces: Custom
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# fails if all initializers fit on one line
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# fails if all initializers fit on one line
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BreakConstructorInitializers: AfterColon
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BreakConstructorInitializers: AfterColon
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ColumnLimit: 0
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ColumnLimit: 90
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# fails
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# fails
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ConstructorInitializerAllOnOneLineOrOnePerLine: false
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ConstructorInitializerIndentWidth: 2
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ConstructorInitializerIndentWidth: 2
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IncludeBlocks: Preserve
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IncludeBlocks: Preserve
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PackConstructorInitializers: Never
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PointerAlignment: Right
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PointerAlignment: Right
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SortIncludes: Never
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@ -5706,7 +5706,7 @@ LibertyReader::visitPgType(LibertyAttr *attr)
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PwrGndType type = findPwrGndType(type_name);
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PwrGndType type = findPwrGndType(type_name);
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PortDirection *dir = PortDirection::unknown();
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PortDirection *dir = PortDirection::unknown();
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switch (type) {
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switch (type) {
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case PwrGndType::primary_ground:;
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case PwrGndType::primary_ground:
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case PwrGndType::backup_ground:
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case PwrGndType::backup_ground:
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case PwrGndType::internal_ground:
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case PwrGndType::internal_ground:
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dir = PortDirection::ground();
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dir = PortDirection::ground();
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@ -489,13 +489,16 @@ PropActivityVisitor::visit(Vertex *vertex)
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}
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}
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if (network_->isDriver(pin)) {
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if (network_->isDriver(pin)) {
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LibertyPort *port = network_->libertyPort(pin);
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LibertyPort *port = network_->libertyPort(pin);
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if (port) {
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LibertyCell *test_cell = port->libertyCell()->testCell();
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if (test_cell)
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port = test_cell->findLibertyPort(port->name());
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}
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if (port) {
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if (port) {
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FuncExpr *func = port->function();
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FuncExpr *func = port->function();
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if (func == nullptr) {
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LibertyCell *test_cell = port->libertyCell()->testCell();
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if (test_cell) {
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port = test_cell->findLibertyPort(port->name());
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if (port)
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func = port->function();
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}
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}
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if (func) {
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if (func) {
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PwrActivity activity = power_->evalActivity(func, inst);
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PwrActivity activity = power_->evalActivity(func, inst);
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changed = setActivityCheck(pin, activity);
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changed = setActivityCheck(pin, activity);
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@ -777,10 +780,24 @@ Power::seedRegOutputActivities(const Instance *inst,
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BfsFwdIterator &bfs)
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BfsFwdIterator &bfs)
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{
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{
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LibertyCell *cell = network_->libertyCell(inst);
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LibertyCell *cell = network_->libertyCell(inst);
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LibertyCell *test_cell = cell->testCell();
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const SequentialSeq &seqs = cell->sequentials();
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const SequentialSeq &seqs = test_cell
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if (!seqs.empty())
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? test_cell->sequentials()
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seedRegOutputActivities(inst, nullptr, seqs, bfs);
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: cell->sequentials();
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else {
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LibertyCell *test_cell = cell->testCell();
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if (test_cell) {
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const SequentialSeq &seqs = test_cell->sequentials();
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seedRegOutputActivities(inst, test_cell, seqs, bfs);
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}
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}
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}
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void
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Power::seedRegOutputActivities(const Instance *inst,
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const LibertyCell *test_cell,
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const SequentialSeq &seqs,
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BfsFwdIterator &bfs)
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{
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for (Sequential *seq : seqs) {
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for (Sequential *seq : seqs) {
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seedRegOutputActivities(inst, seq, seq->output(), false);
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seedRegOutputActivities(inst, seq, seq->output(), false);
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seedRegOutputActivities(inst, seq, seq->outputInv(), true);
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seedRegOutputActivities(inst, seq, seq->outputInv(), true);
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@ -791,7 +808,7 @@ Power::seedRegOutputActivities(const Instance *inst,
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Pin *pin = pin_iter->next();
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Pin *pin = pin_iter->next();
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LibertyPort *port = network_->libertyPort(pin);
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LibertyPort *port = network_->libertyPort(pin);
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if (test_cell)
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if (test_cell)
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port = test_cell->findLibertyPort(port->name());
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port = test_cell->findLibertyPort(port->name());
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if (port) {
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if (port) {
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FuncExpr *func = port->function();
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FuncExpr *func = port->function();
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Vertex *vertex = graph_->pinDrvrVertex(pin);
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Vertex *vertex = graph_->pinDrvrVertex(pin);
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@ -191,6 +191,10 @@ protected:
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bool invert);
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bool invert);
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void seedRegOutputActivities(const Instance *inst,
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void seedRegOutputActivities(const Instance *inst,
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BfsFwdIterator &bfs);
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BfsFwdIterator &bfs);
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void seedRegOutputActivities(const Instance *inst,
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const LibertyCell *test_cell,
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const SequentialSeq &seqs,
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BfsFwdIterator &bfs);
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PwrActivity evalActivity(FuncExpr *expr,
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PwrActivity evalActivity(FuncExpr *expr,
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const Instance *inst);
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const Instance *inst);
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PwrActivity evalActivity(FuncExpr *expr,
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PwrActivity evalActivity(FuncExpr *expr,
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@ -636,7 +636,8 @@ PathEnum::makeDivertedPath(Path *path,
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after_div_copy = copy;
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after_div_copy = copy;
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if (first)
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if (first)
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div_path = copy;
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div_path = copy;
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else if (network_->isLatchData(p->pin(this)))
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else if (found_div
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&& network_->isLatchData(p->pin(this)))
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break;
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break;
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if (p == before_div) {
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if (p == before_div) {
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// Replaced on next pass.
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// Replaced on next pass.
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@ -101,7 +101,7 @@ tclArgError(Tcl_Interp *interp,
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try {
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try {
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Sta::sta()->report()->error(id, msg, arg);
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Sta::sta()->report()->error(id, msg, arg);
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} catch (const std::exception &e) {
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} catch (const std::exception &e) {
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Tcl_SetResult(interp, const_cast<char*>(e.what()), TCL_STATIC);
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Tcl_SetResult(interp, const_cast<char*>(e.what()), TCL_VOLATILE);
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}
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}
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}
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}
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