Merge remote-tracking branch 'parallax/master'

This commit is contained in:
Matt Liberty 2025-11-25 16:53:40 +00:00
commit eb8ab089df
6 changed files with 40 additions and 16 deletions

View File

@ -12,18 +12,20 @@ AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterReturnType: TopLevel AlwaysBreakAfterReturnType: TopLevel
BinPackArguments: false BinPackArguments: false
# fails # fails
BinPackParameters: false BinPackParameters: AlwaysOnePerLine
BraceWrapping: BraceWrapping:
AfterClass: true AfterClass: true
AfterStruct: true AfterStruct: true
AfterFunction: true AfterFunction: true
BeforeElse: true BeforeElse: true
BreakBeforeBinaryOperators: NonAssignment
BreakBeforeBraces: Custom BreakBeforeBraces: Custom
# fails if all initializers fit on one line # fails if all initializers fit on one line
BreakConstructorInitializers: AfterColon BreakConstructorInitializers: AfterColon
ColumnLimit: 0 ColumnLimit: 90
# fails # fails
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 2 ConstructorInitializerIndentWidth: 2
IncludeBlocks: Preserve IncludeBlocks: Preserve
PackConstructorInitializers: Never
PointerAlignment: Right PointerAlignment: Right
SortIncludes: Never

View File

@ -5706,7 +5706,7 @@ LibertyReader::visitPgType(LibertyAttr *attr)
PwrGndType type = findPwrGndType(type_name); PwrGndType type = findPwrGndType(type_name);
PortDirection *dir = PortDirection::unknown(); PortDirection *dir = PortDirection::unknown();
switch (type) { switch (type) {
case PwrGndType::primary_ground:; case PwrGndType::primary_ground:
case PwrGndType::backup_ground: case PwrGndType::backup_ground:
case PwrGndType::internal_ground: case PwrGndType::internal_ground:
dir = PortDirection::ground(); dir = PortDirection::ground();

View File

@ -489,13 +489,16 @@ PropActivityVisitor::visit(Vertex *vertex)
} }
if (network_->isDriver(pin)) { if (network_->isDriver(pin)) {
LibertyPort *port = network_->libertyPort(pin); LibertyPort *port = network_->libertyPort(pin);
if (port) {
LibertyCell *test_cell = port->libertyCell()->testCell();
if (test_cell)
port = test_cell->findLibertyPort(port->name());
}
if (port) { if (port) {
FuncExpr *func = port->function(); FuncExpr *func = port->function();
if (func == nullptr) {
LibertyCell *test_cell = port->libertyCell()->testCell();
if (test_cell) {
port = test_cell->findLibertyPort(port->name());
if (port)
func = port->function();
}
}
if (func) { if (func) {
PwrActivity activity = power_->evalActivity(func, inst); PwrActivity activity = power_->evalActivity(func, inst);
changed = setActivityCheck(pin, activity); changed = setActivityCheck(pin, activity);
@ -777,10 +780,24 @@ Power::seedRegOutputActivities(const Instance *inst,
BfsFwdIterator &bfs) BfsFwdIterator &bfs)
{ {
LibertyCell *cell = network_->libertyCell(inst); LibertyCell *cell = network_->libertyCell(inst);
LibertyCell *test_cell = cell->testCell(); const SequentialSeq &seqs = cell->sequentials();
const SequentialSeq &seqs = test_cell if (!seqs.empty())
? test_cell->sequentials() seedRegOutputActivities(inst, nullptr, seqs, bfs);
: cell->sequentials(); else {
LibertyCell *test_cell = cell->testCell();
if (test_cell) {
const SequentialSeq &seqs = test_cell->sequentials();
seedRegOutputActivities(inst, test_cell, seqs, bfs);
}
}
}
void
Power::seedRegOutputActivities(const Instance *inst,
const LibertyCell *test_cell,
const SequentialSeq &seqs,
BfsFwdIterator &bfs)
{
for (Sequential *seq : seqs) { for (Sequential *seq : seqs) {
seedRegOutputActivities(inst, seq, seq->output(), false); seedRegOutputActivities(inst, seq, seq->output(), false);
seedRegOutputActivities(inst, seq, seq->outputInv(), true); seedRegOutputActivities(inst, seq, seq->outputInv(), true);
@ -791,7 +808,7 @@ Power::seedRegOutputActivities(const Instance *inst,
Pin *pin = pin_iter->next(); Pin *pin = pin_iter->next();
LibertyPort *port = network_->libertyPort(pin); LibertyPort *port = network_->libertyPort(pin);
if (test_cell) if (test_cell)
port = test_cell->findLibertyPort(port->name()); port = test_cell->findLibertyPort(port->name());
if (port) { if (port) {
FuncExpr *func = port->function(); FuncExpr *func = port->function();
Vertex *vertex = graph_->pinDrvrVertex(pin); Vertex *vertex = graph_->pinDrvrVertex(pin);

View File

@ -191,6 +191,10 @@ protected:
bool invert); bool invert);
void seedRegOutputActivities(const Instance *inst, void seedRegOutputActivities(const Instance *inst,
BfsFwdIterator &bfs); BfsFwdIterator &bfs);
void seedRegOutputActivities(const Instance *inst,
const LibertyCell *test_cell,
const SequentialSeq &seqs,
BfsFwdIterator &bfs);
PwrActivity evalActivity(FuncExpr *expr, PwrActivity evalActivity(FuncExpr *expr,
const Instance *inst); const Instance *inst);
PwrActivity evalActivity(FuncExpr *expr, PwrActivity evalActivity(FuncExpr *expr,

View File

@ -636,7 +636,8 @@ PathEnum::makeDivertedPath(Path *path,
after_div_copy = copy; after_div_copy = copy;
if (first) if (first)
div_path = copy; div_path = copy;
else if (network_->isLatchData(p->pin(this))) else if (found_div
&& network_->isLatchData(p->pin(this)))
break; break;
if (p == before_div) { if (p == before_div) {
// Replaced on next pass. // Replaced on next pass.

View File

@ -101,7 +101,7 @@ tclArgError(Tcl_Interp *interp,
try { try {
Sta::sta()->report()->error(id, msg, arg); Sta::sta()->report()->error(id, msg, arg);
} catch (const std::exception &e) { } catch (const std::exception &e) {
Tcl_SetResult(interp, const_cast<char*>(e.what()), TCL_STATIC); Tcl_SetResult(interp, const_cast<char*>(e.what()), TCL_VOLATILE);
} }
} }