issue38 ccs_sim1
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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@ -226,6 +226,8 @@ CcsSimDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
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else {
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simulate(dcalc_args);
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ArcDcalcArg &drvr_arg = dcalc_args[0];
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const LibertyLibrary *drvr_library = drvr_arg.drvrLibrary();
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for (size_t drvr_idx = 0; drvr_idx < dcalc_args.size(); drvr_idx++) {
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ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx];
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ArcDcalcResult &dcalc_result = dcalc_results[drvr_idx];
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@ -258,8 +260,6 @@ CcsSimDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
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delayAsString(wire_delay, this),
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delayAsString(load_slew, this));
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LibertyLibrary *drvr_library =
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network_->libertyPort(load_pin)->libertyCell()->libertyLibrary();
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thresholdAdjust(load_pin, drvr_library, drvr_rf_, wire_delay, load_slew);
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dcalc_result.setWireDelay(load_idx, wire_delay);
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dcalc_result.setLoadSlew(load_idx, load_slew);
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@ -187,7 +187,7 @@ proc run_test { test } {
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puts " pass$error_msg"
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}
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} else {
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puts " *NO OK FILE*$error_msg"
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puts " *NO OK FILE*"
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append_failure $test
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incr errors(no_ok)
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}
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