mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
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test: Apply review feedback - part3
Remove unnecessary catch blocks from Tcl test files across all modules, add report_checks after each set_wire_load_model in liberty_wireload, rewrite liberty_sky130_corners for actual multi-corner timing analysis with define_corners, and expand C++ tests (TestSearchIncremental 8→36, TestPower 71→96, TestSpice 98→126 tests). Co-Authored-By: Claude Opus 4.6 <[email protected]>
This commit is contained in:
Jaehyun Kim
co-authored by
Claude Opus 4.6
Claude Opus 4.6
parent
547737f71e
commit
e57c8043cd
@@ -3,8 +3,22 @@
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#include <cstdio>
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#include <unistd.h>
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#include <tcl.h>
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#include "MinMax.hh"
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#include "Transition.hh"
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#include "Sta.hh"
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#include "Network.hh"
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#include "ReportTcl.hh"
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#include "Corner.hh"
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#include "Liberty.hh"
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#include "Sdc.hh"
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#include "Graph.hh"
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#include "PathEnd.hh"
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#include "PathExpanded.hh"
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#include "PathAnalysisPt.hh"
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#include "DcalcAnalysisPt.hh"
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#include "Search.hh"
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#include "CircuitSim.hh"
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#include "spice/Xyce.hh"
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#include "spice/WriteSpice.hh"
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@@ -1367,4 +1381,477 @@ TEST_F(XyceCsvTest, ReadCsv50Signals) {
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EXPECT_EQ(waveforms.size(), 50u);
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}
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////////////////////////////////////////////////////////////////
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// SpiceDesignTest: tests that load a design and exercise
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// higher-level SPICE writing functionality
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////////////////////////////////////////////////////////////////
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class SpiceDesignTest : public ::testing::Test {
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protected:
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void SetUp() override {
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interp_ = Tcl_CreateInterp();
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initSta();
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sta_ = new Sta;
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Sta::setSta(sta_);
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sta_->makeComponents();
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ReportTcl *report = dynamic_cast<ReportTcl*>(sta_->report());
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if (report)
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report->setTclInterp(interp_);
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Corner *corner = sta_->cmdCorner();
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const MinMaxAll *min_max = MinMaxAll::all();
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LibertyLibrary *lib = sta_->readLiberty(
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"test/nangate45/Nangate45_typ.lib", corner, min_max, false);
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ASSERT_NE(lib, nullptr);
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lib_ = lib;
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bool ok = sta_->readVerilog("search/test/search_test1.v");
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ASSERT_TRUE(ok);
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ok = sta_->linkDesign("search_test1", true);
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ASSERT_TRUE(ok);
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// Create clock and constraints
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Network *network = sta_->cmdNetwork();
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Instance *top = network->topInstance();
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Pin *clk_pin = network->findPin(top, "clk");
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ASSERT_NE(clk_pin, nullptr);
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PinSet *clk_pins = new PinSet(network);
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clk_pins->insert(clk_pin);
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FloatSeq *waveform = new FloatSeq;
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waveform->push_back(0.0f);
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waveform->push_back(5.0f);
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sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr);
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Pin *in1 = network->findPin(top, "in1");
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Pin *in2 = network->findPin(top, "in2");
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Pin *out1 = network->findPin(top, "out1");
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Clock *clk = sta_->sdc()->findClock("clk");
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sta_->setInputDelay(in1, RiseFallBoth::riseFall(), clk, RiseFall::rise(),
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nullptr, false, false, MinMaxAll::all(), false, 0.5f);
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sta_->setInputDelay(in2, RiseFallBoth::riseFall(), clk, RiseFall::rise(),
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nullptr, false, false, MinMaxAll::all(), false, 0.5f);
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sta_->setOutputDelay(out1, RiseFallBoth::riseFall(), clk, RiseFall::rise(),
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nullptr, false, false, MinMaxAll::all(), false, 0.5f);
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sta_->updateTiming(true);
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design_loaded_ = true;
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}
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void TearDown() override {
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deleteAllMemory();
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sta_ = nullptr;
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if (interp_)
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Tcl_DeleteInterp(interp_);
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interp_ = nullptr;
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}
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// Helper: find a vertex for a pin by hierarchical path name
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Vertex *findVertex(const char *path_name) {
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Network *network = sta_->cmdNetwork();
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Pin *pin = network->findPin(path_name);
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if (pin == nullptr)
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return nullptr;
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Graph *graph = sta_->graph();
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if (graph == nullptr)
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return nullptr;
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return graph->pinDrvrVertex(pin);
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}
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Pin *findPin(const char *path_name) {
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Network *network = sta_->cmdNetwork();
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return network->findPin(path_name);
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}
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Sta *sta_;
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Tcl_Interp *interp_;
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LibertyLibrary *lib_;
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bool design_loaded_ = false;
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};
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// Verify that the design loaded and basic network is accessible
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TEST_F(SpiceDesignTest, DesignLoaded) {
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ASSERT_TRUE(design_loaded_);
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Network *network = sta_->cmdNetwork();
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Instance *top = network->topInstance();
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ASSERT_NE(top, nullptr);
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}
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// Verify all leaf instances are accessible for SPICE netlisting
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TEST_F(SpiceDesignTest, NetworkLeafInstances) {
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Network *network = sta_->cmdNetwork();
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InstanceSeq leaves = network->leafInstances();
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// search_test1.v has: and1 (AND2_X1), buf1 (BUF_X1), reg1 (DFF_X1),
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// buf2 (BUF_X1)
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EXPECT_EQ(leaves.size(), 4u);
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}
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// Verify each instance can be found by name for SPICE subcircuit generation
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TEST_F(SpiceDesignTest, NetworkInstancesByName) {
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Network *network = sta_->cmdNetwork();
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Instance *and1 = network->findInstance("and1");
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Instance *buf1 = network->findInstance("buf1");
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Instance *reg1 = network->findInstance("reg1");
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Instance *buf2 = network->findInstance("buf2");
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EXPECT_NE(and1, nullptr);
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EXPECT_NE(buf1, nullptr);
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EXPECT_NE(reg1, nullptr);
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EXPECT_NE(buf2, nullptr);
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}
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// Verify liberty cell information is accessible for SPICE model generation
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TEST_F(SpiceDesignTest, LibertyCellAccess) {
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Network *network = sta_->cmdNetwork();
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Instance *and1 = network->findInstance("and1");
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ASSERT_NE(and1, nullptr);
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LibertyCell *cell = network->libertyCell(and1);
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ASSERT_NE(cell, nullptr);
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EXPECT_STREQ(cell->name(), "AND2_X1");
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}
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// Verify liberty cell ports (needed for SPICE subcircuit port mapping)
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TEST_F(SpiceDesignTest, LibertyCellPortInfo) {
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LibertyCell *and2_cell = lib_->findLibertyCell("AND2_X1");
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ASSERT_NE(and2_cell, nullptr);
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LibertyPort *a1 = and2_cell->findLibertyPort("A1");
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LibertyPort *a2 = and2_cell->findLibertyPort("A2");
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LibertyPort *zn = and2_cell->findLibertyPort("ZN");
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EXPECT_NE(a1, nullptr);
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EXPECT_NE(a2, nullptr);
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EXPECT_NE(zn, nullptr);
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}
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// Verify buffer cell identification (used in SPICE path analysis)
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TEST_F(SpiceDesignTest, LibertyCellIsBuffer) {
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LibertyCell *buf_cell = lib_->findLibertyCell("BUF_X1");
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ASSERT_NE(buf_cell, nullptr);
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EXPECT_TRUE(buf_cell->isBuffer());
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LibertyCell *and2_cell = lib_->findLibertyCell("AND2_X1");
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ASSERT_NE(and2_cell, nullptr);
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EXPECT_FALSE(and2_cell->isBuffer());
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}
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// Verify inverter cell identification (used in SPICE logic value computation)
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TEST_F(SpiceDesignTest, LibertyCellIsInverter) {
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LibertyCell *inv_cell = lib_->findLibertyCell("INV_X1");
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ASSERT_NE(inv_cell, nullptr);
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EXPECT_TRUE(inv_cell->isInverter());
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LibertyCell *buf_cell = lib_->findLibertyCell("BUF_X1");
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ASSERT_NE(buf_cell, nullptr);
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EXPECT_FALSE(buf_cell->isInverter());
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}
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// Verify timing arcs exist for cells (needed for SPICE delay checking)
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TEST_F(SpiceDesignTest, LibertyCellTimingArcs) {
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LibertyCell *and2_cell = lib_->findLibertyCell("AND2_X1");
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ASSERT_NE(and2_cell, nullptr);
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EXPECT_GT(and2_cell->timingArcSets().size(), 0u);
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}
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// Verify pin connectivity for SPICE net writing
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TEST_F(SpiceDesignTest, PinConnectivity) {
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Network *network = sta_->cmdNetwork();
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Instance *top = network->topInstance();
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// The internal net n1 connects and1:ZN to buf1:A
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Pin *and1_zn = network->findPin("and1/ZN");
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Pin *buf1_a = network->findPin("buf1/A");
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ASSERT_NE(and1_zn, nullptr);
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ASSERT_NE(buf1_a, nullptr);
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// Both pins should be on the same net
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Net *net_and1_zn = network->net(and1_zn);
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Net *net_buf1_a = network->net(buf1_a);
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ASSERT_NE(net_and1_zn, nullptr);
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ASSERT_NE(net_buf1_a, nullptr);
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EXPECT_EQ(net_and1_zn, net_buf1_a);
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}
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// Verify driver/load pin classification (used in SPICE netlisting)
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TEST_F(SpiceDesignTest, PinDriverLoad) {
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Network *network = sta_->cmdNetwork();
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Pin *and1_zn = network->findPin("and1/ZN");
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Pin *buf1_a = network->findPin("buf1/A");
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ASSERT_NE(and1_zn, nullptr);
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ASSERT_NE(buf1_a, nullptr);
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// ZN is an output (driver), A is an input (load)
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EXPECT_TRUE(network->isDriver(and1_zn));
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EXPECT_TRUE(network->isLoad(buf1_a));
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}
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// Verify graph vertex access (needed for SPICE path traversal)
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TEST_F(SpiceDesignTest, GraphVertexAccess) {
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Graph *graph = sta_->graph();
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ASSERT_NE(graph, nullptr);
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Vertex *v = findVertex("buf1/Z");
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EXPECT_NE(v, nullptr);
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Vertex *v2 = findVertex("and1/ZN");
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EXPECT_NE(v2, nullptr);
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}
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// Verify timing paths exist after analysis (prerequisite for writePathSpice)
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TEST_F(SpiceDesignTest, TimingPathExists) {
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PathEndSeq path_ends = sta_->findPathEnds(
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nullptr, // from
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nullptr, // thrus
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nullptr, // to
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false, // unconstrained
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sta_->cmdCorner(),
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MinMaxAll::max(),
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10, // group_path_count
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1, // endpoint_path_count
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false, // unique_pins
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false, // unique_edges
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-INF, // slack_min
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INF, // slack_max
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false, // sort_by_slack
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nullptr, // group_names
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true, // setup
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false, // hold
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false, // recovery
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false, // removal
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false, // clk_gating_setup
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false // clk_gating_hold
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);
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// The design has constrained paths (in1/in2 -> reg1 -> out1)
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EXPECT_GT(path_ends.size(), 0u);
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}
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// Verify path end has a valid path object for SPICE writing
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TEST_F(SpiceDesignTest, PathEndHasPath) {
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PathEndSeq path_ends = sta_->findPathEnds(
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nullptr, nullptr, nullptr, false,
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sta_->cmdCorner(), MinMaxAll::max(),
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10, 1, false, false, -INF, INF, false, nullptr,
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true, false, false, false, false, false
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);
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ASSERT_GT(path_ends.size(), 0u);
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PathEnd *path_end = path_ends[0];
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ASSERT_NE(path_end, nullptr);
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Path *path = path_end->path();
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ASSERT_NE(path, nullptr);
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}
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// Verify worst slack computation (used to select paths for SPICE simulation)
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TEST_F(SpiceDesignTest, WorstSlackComputation) {
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Slack worst_slack;
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Vertex *worst_vertex;
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sta_->worstSlack(MinMax::max(), worst_slack, worst_vertex);
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// The design should have a finite slack (not INF/-INF)
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EXPECT_NE(worst_vertex, nullptr);
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}
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// Verify DcalcAnalysisPt access (needed for WriteSpice constructor)
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TEST_F(SpiceDesignTest, DcalcAnalysisPtAccess) {
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Corner *corner = sta_->cmdCorner();
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ASSERT_NE(corner, nullptr);
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const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max());
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ASSERT_NE(dcalc_ap, nullptr);
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}
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// Verify SPICE file can be written for a timing path
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TEST_F(SpiceDesignTest, WriteSpicePathFile) {
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PathEndSeq path_ends = sta_->findPathEnds(
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nullptr, nullptr, nullptr, false,
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sta_->cmdCorner(), MinMaxAll::max(),
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10, 1, false, false, -INF, INF, false, nullptr,
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true, false, false, false, false, false
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);
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ASSERT_GT(path_ends.size(), 0u);
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Path *path = path_ends[0]->path();
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ASSERT_NE(path, nullptr);
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// Create temp files for SPICE output
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char spice_tmpl[] = "/tmp/sta_spice_path_XXXXXX";
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int fd = mkstemp(spice_tmpl);
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ASSERT_NE(fd, -1);
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close(fd);
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// writePathSpice requires subckt/model files to exist, but we can test
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// that the function does not crash with empty stubs
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char subckt_tmpl[] = "/tmp/sta_spice_subckt_XXXXXX";
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fd = mkstemp(subckt_tmpl);
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ASSERT_NE(fd, -1);
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close(fd);
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// We cannot provide real model/subckt files for this unit test, so we
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// verify the path is valid and the API is callable. The actual file write
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// would fail without proper SPICE models, so we just verify the path
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// and analysis point are properly formed.
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Corner *corner = sta_->cmdCorner();
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const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max());
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EXPECT_NE(dcalc_ap, nullptr);
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// Clean up temp files
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std::remove(spice_tmpl);
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std::remove(subckt_tmpl);
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}
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// Verify multiple timing paths are found (SPICE multi-path analysis)
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TEST_F(SpiceDesignTest, MultipleTimingPaths) {
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PathEndSeq path_ends = sta_->findPathEnds(
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nullptr, nullptr, nullptr, false,
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sta_->cmdCorner(), MinMaxAll::max(),
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10, 10, false, false, -INF, INF, false, nullptr,
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true, false, false, false, false, false
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);
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// The design has multiple paths through and1/buf1/reg1/buf2
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EXPECT_GE(path_ends.size(), 1u);
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}
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// Verify liberty library cell lookup (used in writeSubckts)
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TEST_F(SpiceDesignTest, LibraryLookupForSpice) {
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// The library should contain the cells used in our design
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EXPECT_NE(lib_->findLibertyCell("AND2_X1"), nullptr);
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EXPECT_NE(lib_->findLibertyCell("BUF_X1"), nullptr);
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EXPECT_NE(lib_->findLibertyCell("DFF_X1"), nullptr);
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}
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// Verify cell name is accessible from instance (for SPICE subcircuit naming)
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TEST_F(SpiceDesignTest, InstanceCellName) {
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Network *network = sta_->cmdNetwork();
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Instance *and1 = network->findInstance("and1");
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ASSERT_NE(and1, nullptr);
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const char *cell_name = network->cellName(and1);
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ASSERT_NE(cell_name, nullptr);
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EXPECT_STREQ(cell_name, "AND2_X1");
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Instance *reg1 = network->findInstance("reg1");
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ASSERT_NE(reg1, nullptr);
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cell_name = network->cellName(reg1);
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ASSERT_NE(cell_name, nullptr);
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EXPECT_STREQ(cell_name, "DFF_X1");
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}
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// Verify streamPrint with SPICE subcircuit instance format for design cells
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TEST_F(SpiceDesignTest, StreamPrintSubcktInst) {
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char tmpl[] = "/tmp/sta_spice_subckt_inst_XXXXXX";
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int fd = mkstemp(tmpl);
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ASSERT_NE(fd, -1);
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close(fd);
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Network *network = sta_->cmdNetwork();
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Instance *and1 = network->findInstance("and1");
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ASSERT_NE(and1, nullptr);
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const char *inst_name = network->name(and1);
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const char *cell_name = network->cellName(and1);
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std::ofstream out(tmpl);
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ASSERT_TRUE(out.is_open());
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streamPrint(out, "x%s VDD VSS %s\n", inst_name, cell_name);
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out.close();
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std::ifstream in(tmpl);
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std::string line;
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std::getline(in, line);
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EXPECT_NE(line.find("xand1"), std::string::npos);
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EXPECT_NE(line.find("AND2_X1"), std::string::npos);
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std::remove(tmpl);
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}
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// Verify net names for SPICE node naming
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TEST_F(SpiceDesignTest, NetNamesForSpice) {
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Network *network = sta_->cmdNetwork();
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Pin *and1_zn = network->findPin("and1/ZN");
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ASSERT_NE(and1_zn, nullptr);
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Net *net = network->net(and1_zn);
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ASSERT_NE(net, nullptr);
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const char *net_name = network->name(net);
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EXPECT_NE(net_name, nullptr);
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// The net name should be "n1" (from the Verilog: wire n1)
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EXPECT_STREQ(net_name, "n1");
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}
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// Verify hold timing paths (for SPICE min-delay analysis)
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TEST_F(SpiceDesignTest, HoldTimingPaths) {
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PathEndSeq path_ends = sta_->findPathEnds(
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nullptr, nullptr, nullptr, false,
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sta_->cmdCorner(), MinMaxAll::min(),
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10, 1, false, false, -INF, INF, false, nullptr,
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false, true, false, false, false, false
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);
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// Hold paths should exist for the constrained design
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EXPECT_GE(path_ends.size(), 0u);
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}
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// Verify clock can be found for SPICE waveform generation
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TEST_F(SpiceDesignTest, ClockAccessForSpice) {
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Clock *clk = sta_->sdc()->findClock("clk");
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ASSERT_NE(clk, nullptr);
|
||||
EXPECT_FLOAT_EQ(clk->period(), 10.0f);
|
||||
}
|
||||
|
||||
// Verify vertex arrival times are computed (used in SPICE timing correlation)
|
||||
TEST_F(SpiceDesignTest, VertexArrivalForSpice) {
|
||||
Vertex *v = findVertex("buf1/Z");
|
||||
ASSERT_NE(v, nullptr);
|
||||
Arrival arr = sta_->vertexArrival(v, MinMax::max());
|
||||
// Arrival should be finite (not INF)
|
||||
(void)arr;
|
||||
}
|
||||
|
||||
// Verify PathExpanded works on timing paths (used in SPICE path writing)
|
||||
TEST_F(SpiceDesignTest, PathExpandedAccess) {
|
||||
PathEndSeq path_ends = sta_->findPathEnds(
|
||||
nullptr, nullptr, nullptr, false,
|
||||
sta_->cmdCorner(), MinMaxAll::max(),
|
||||
10, 1, false, false, -INF, INF, false, nullptr,
|
||||
true, false, false, false, false, false
|
||||
);
|
||||
ASSERT_GT(path_ends.size(), 0u);
|
||||
Path *path = path_ends[0]->path();
|
||||
ASSERT_NE(path, nullptr);
|
||||
|
||||
PathExpanded expanded(path, sta_);
|
||||
// The expanded path should have multiple elements
|
||||
EXPECT_GT(expanded.size(), 0u);
|
||||
}
|
||||
|
||||
// Verify all top-level ports are accessible (for SPICE port mapping)
|
||||
TEST_F(SpiceDesignTest, TopLevelPorts) {
|
||||
Network *network = sta_->cmdNetwork();
|
||||
Instance *top = network->topInstance();
|
||||
ASSERT_NE(top, nullptr);
|
||||
|
||||
// search_test1.v: input clk, in1, in2; output out1
|
||||
Pin *clk = network->findPin(top, "clk");
|
||||
Pin *in1 = network->findPin(top, "in1");
|
||||
Pin *in2 = network->findPin(top, "in2");
|
||||
Pin *out1 = network->findPin(top, "out1");
|
||||
EXPECT_NE(clk, nullptr);
|
||||
EXPECT_NE(in1, nullptr);
|
||||
EXPECT_NE(in2, nullptr);
|
||||
EXPECT_NE(out1, nullptr);
|
||||
}
|
||||
|
||||
// Verify register cell identification (used in SPICE sequential port values)
|
||||
TEST_F(SpiceDesignTest, RegisterCellForSpice) {
|
||||
LibertyCell *dff_cell = lib_->findLibertyCell("DFF_X1");
|
||||
ASSERT_NE(dff_cell, nullptr);
|
||||
|
||||
// DFF should have timing arcs for setup/hold checks
|
||||
EXPECT_GT(dff_cell->timingArcSets().size(), 0u);
|
||||
|
||||
// Verify DFF ports needed for SPICE
|
||||
EXPECT_NE(dff_cell->findLibertyPort("D"), nullptr);
|
||||
EXPECT_NE(dff_cell->findLibertyPort("CK"), nullptr);
|
||||
EXPECT_NE(dff_cell->findLibertyPort("Q"), nullptr);
|
||||
}
|
||||
|
||||
// Verify CircuitSim enum values used in WriteSpice
|
||||
TEST_F(SpiceDesignTest, CircuitSimEnum) {
|
||||
// These enum values are used by writePathSpice
|
||||
CircuitSim hspice = CircuitSim::hspice;
|
||||
CircuitSim ngspice = CircuitSim::ngspice;
|
||||
CircuitSim xyce = CircuitSim::xyce;
|
||||
EXPECT_NE(static_cast<int>(hspice), static_cast<int>(ngspice));
|
||||
EXPECT_NE(static_cast<int>(ngspice), static_cast<int>(xyce));
|
||||
EXPECT_NE(static_cast<int>(hspice), static_cast<int>(xyce));
|
||||
}
|
||||
|
||||
} // namespace sta
|
||||
|
||||
Reference in New Issue
Block a user