require CUDD
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry
parent
2da2064852
commit
e3a1fd792c
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@ -28,7 +28,6 @@ project(STA VERSION 2.6.0
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LANGUAGES CXX
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)
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option(USE_CUDD "Use CUDD BDD package" ON)
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option(CUDD_DIR "CUDD BDD package directory")
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option(USE_TCL_READLINE "Use TCL readliine package" ON)
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option(USE_SANITIZE "Compile with santize address enabled")
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@ -371,14 +370,12 @@ find_package(Eigen3 REQUIRED)
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#
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# Locate CUDD bdd package.
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#
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set(CUDD 0)
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if (USE_CUDD)
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find_library(CUDD_LIB
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find_library(CUDD_LIB
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NAME cudd
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PATHS ${CUDD_DIR}
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PATH_SUFFIXES lib lib/cudd cudd/.libs
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)
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if (CUDD_LIB)
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if (CUDD_LIB)
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message(STATUS "CUDD library: ${CUDD_LIB}")
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get_filename_component(CUDD_LIB_DIR "${CUDD_LIB}" PATH)
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get_filename_component(CUDD_LIB_PARENT1 "${CUDD_LIB_DIR}" PATH)
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@ -387,14 +384,11 @@ if (USE_CUDD)
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if (CUDD_HEADER)
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get_filename_component(CUDD_INCLUDE "${CUDD_HEADER}" PATH)
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message(STATUS "CUDD header: ${CUDD_HEADER}")
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# Referenced by StaConfig.hh.cmake
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set(CUDD 1)
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else()
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message(STATUS "CUDD header: not found")
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endif()
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else()
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else()
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message(STATUS "CUDD library: not found")
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endif()
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endif()
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if("${SSTA}" STREQUAL "")
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@ -517,6 +511,7 @@ target_link_libraries(OpenSTA
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Eigen3::Eigen
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${TCL_LIBRARY}
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${CMAKE_THREAD_LIBS_INIT}
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${CUDD_LIB}
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)
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if (TCL_READLINE_LIBRARY)
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@ -527,9 +522,7 @@ if (ZLIB_LIBRARIES)
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target_link_libraries(OpenSTA ${ZLIB_LIBRARIES})
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endif()
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if (CUDD_LIB)
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target_link_libraries(OpenSTA ${CUDD_LIB})
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endif()
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target_link_libraries(OpenSTA )
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target_include_directories(OpenSTA
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PUBLIC
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@ -103,9 +103,9 @@ External library dependencies:
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```
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Ubuntu Macos license
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eigen 3.4.0 3.4.0 MPL2 required
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cudd 3.0.0 3.0.0 BSD required
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tclreadline 2.3.8 2.3.8 BSD optional
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zLib 1.2.5 1.2.8 zlib optional
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cudd 3.0.0 3.0.0 BSD optional
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```
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The [TCL readline library](https://tclreadline.sourceforge.net/tclreadline.html)
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@ -7,8 +7,9 @@ Release 2.6.0 2024/07/??
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-------------------------
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The version of c++ used by OpenSTA is now 17.
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The Cudd BBD packager is now required.
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The USE_CUDD and USE_TCL_READLINE options default to ON.
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The USE_TCL_READLINE option defaults to ON.
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Release 2.5.0 2024/01/17
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-------------------------
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@ -18,16 +18,10 @@
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#include <map>
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#include "cudd.h"
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#include "StaState.hh"
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#include "LibertyClass.hh"
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#if CUDD
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#include "cudd.h"
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#else
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struct DdNode;
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struct DdManager;
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#endif
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namespace sta {
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typedef std::map<const LibertyPort*, DdNode*> BddPortVarMap;
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108
power/Power.cc
108
power/Power.cc
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@ -502,8 +502,6 @@ Power::clockGatePins(const Instance *inst,
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////////////////////////////////////////////////////////////////
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#if CUDD
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PwrActivity
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Power::evalActivity(FuncExpr *expr,
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const Instance *inst)
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@ -609,112 +607,6 @@ Power::evalBddActivity(DdNode *bdd,
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return activity;
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}
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#else
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PwrActivity
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Power::evalActivity(FuncExpr *expr,
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const Instance *inst)
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{
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return evalActivity(expr, inst, nullptr, true);
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}
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// Eval activity thru expr.
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// With cofactor_port eval the positive/negative cofactor of expr wrt cofactor_port.
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PwrActivity
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Power::evalActivity(FuncExpr *expr,
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const Instance *inst,
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const LibertyPort *cofactor_port,
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bool cofactor_positive)
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{
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switch (expr->op()) {
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case FuncExpr::op_port: {
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LibertyPort *port = expr->port();
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if (port == cofactor_port) {
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if (cofactor_positive)
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return PwrActivity(0.0, 1.0, PwrActivityOrigin::constant);
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else
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return PwrActivity(0.0, 0.0, PwrActivityOrigin::constant);
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}
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if (port->direction()->isInternal())
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return findSeqActivity(inst, port);
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else {
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Pin *pin = findLinkPin(inst, port);
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if (pin) {
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PwrActivity activity = findActivity(pin);
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activity.setOrigin(PwrActivityOrigin::propagated);
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return activity;
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}
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}
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return PwrActivity(0.0, 0.0, PwrActivityOrigin::constant);
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}
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case FuncExpr::op_not: {
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PwrActivity activity1 = evalActivity(expr->left(), inst,
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cofactor_port, cofactor_positive);
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return PwrActivity(activity1.activity(),
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1.0 - activity1.duty(),
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PwrActivityOrigin::propagated);
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}
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case FuncExpr::op_or: {
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PwrActivity activity1 = evalActivity(expr->left(), inst,
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cofactor_port, cofactor_positive);
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PwrActivity activity2 = evalActivity(expr->right(), inst,
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cofactor_port, cofactor_positive);
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float p1 = 1.0 - activity1.duty();
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float p2 = 1.0 - activity2.duty();
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return PwrActivity(activity1.activity() * p2 + activity2.activity() * p1,
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// d1 + d2 - d1 * d2
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1.0 - p1 * p2,
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PwrActivityOrigin::propagated);
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}
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case FuncExpr::op_and: {
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PwrActivity activity1 = evalActivity(expr->left(), inst,
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cofactor_port, cofactor_positive);
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PwrActivity activity2 = evalActivity(expr->right(), inst,
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cofactor_port, cofactor_positive);
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float p1 = activity1.duty();
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float p2 = activity2.duty();
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return PwrActivity(activity1.activity() * p2 + activity2.activity() * p1,
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p1 * p2,
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PwrActivityOrigin::propagated);
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}
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case FuncExpr::op_xor: {
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PwrActivity activity1 = evalActivity(expr->left(), inst,
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cofactor_port, cofactor_positive);
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PwrActivity activity2 = evalActivity(expr->right(), inst,
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cofactor_port, cofactor_positive);
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float d1 = activity1.duty();
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float d2 = activity2.duty();
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float p1 = d1 * (1.0 - d2);
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float p2 = (1.0 - d1) * d2;
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return PwrActivity(activity1.activity() + activity2.activity(),
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p1 + p2,
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PwrActivityOrigin::propagated);
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}
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case FuncExpr::op_one:
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return PwrActivity(0.0, 1.0, PwrActivityOrigin::constant);
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case FuncExpr::op_zero:
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return PwrActivity(0.0, 0.0, PwrActivityOrigin::constant);
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}
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return PwrActivity();
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}
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// Eval activity of difference(expr) wrt cofactor port.
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float
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Power::evalDiffDuty(FuncExpr *expr,
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LibertyPort *cofactor_port,
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const Instance *inst)
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{
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// Activity of positive/negative cofactors.
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PwrActivity pos = evalActivity(expr, inst, cofactor_port, true);
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PwrActivity neg = evalActivity(expr, inst, cofactor_port, false);
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// difference = xor(pos, neg).
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float p1 = pos.duty() * (1.0 - neg.duty());
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float p2 = neg.duty() * (1.0 - pos.duty());
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return p1 + p2;
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}
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#endif // CUDD
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////////////////////////////////////////////////////////////////
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void
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@ -16,30 +16,11 @@
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#include "Bdd.hh"
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#include "cudd.h"
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#include "StaConfig.hh"
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#include "Report.hh"
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#include "FuncExpr.hh"
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#if CUDD
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#include "cudd.h"
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#else
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#include <cstdint>
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#define CUDD_UNIQUE_SLOTS 0
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#define CUDD_CACHE_SLOTS 0
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DdManager *Cudd_Init(int, int, int, int, int) { return nullptr; }
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void Cudd_Quit(void *) {}
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DdNode *Cudd_Not(void *) { return nullptr; }
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DdNode *Cudd_bddOr(void *, void *, void *) { return nullptr; }
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DdNode *Cudd_bddAnd(void *, void *, void *) { return nullptr; }
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DdNode *Cudd_bddXor(void *, void *, void *) { return nullptr; }
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DdNode *Cudd_ReadOne(void *) { return nullptr; }
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DdNode *Cudd_ReadLogicZero(void *) { return nullptr; }
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DdNode *Cudd_bddNewVar(void *) { return nullptr; }
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int Cudd_NodeReadIndex(void *) { return 0;}
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void Cudd_Ref(void *) {}
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void Cudd_RecursiveDeref(void *, void *) {}
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#endif
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namespace sta {
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Bdd::Bdd(const StaState *sta) :
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287
search/Sim.cc
287
search/Sim.cc
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@ -16,7 +16,9 @@
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#include "Sim.hh"
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#include "StaConfig.hh" // CUDD
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// https://davidkebo.com/cudd
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#include "cudd.h"
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#include "Error.hh"
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#include "Mutex.hh"
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#include "Debug.hh"
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@ -32,14 +34,6 @@
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#include "Sdc.hh"
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#include "Graph.hh"
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#if CUDD
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// https://davidkebo.com/cudd
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#include "cudd.h"
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#else
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#define Cudd_Init(ignore1, ignore2, ignore3, ignore4, ignore5) nullptr
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#define Cudd_Quit(ignore1)
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#endif
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namespace sta {
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static LogicValue
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@ -69,8 +63,6 @@ Sim::~Sim()
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delete observer_;
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}
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#if CUDD
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TimingSense
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Sim::functionSense(const FuncExpr *expr,
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const Pin *input_pin,
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@ -159,279 +151,6 @@ Sim::funcBddSim(const FuncExpr *expr,
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return bdd;
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}
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#else
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// No CUDD.
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static LogicValue
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logicOr(LogicValue value1,
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LogicValue value2)
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{
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static LogicValue logic_or[5][5] =
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{{LogicValue::zero, LogicValue::one, LogicValue::unknown, LogicValue::unknown, LogicValue::unknown},
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{LogicValue::one, LogicValue::one, LogicValue::one, LogicValue::one, LogicValue::one},
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{LogicValue::unknown,LogicValue::one, LogicValue::unknown, LogicValue::unknown, LogicValue::unknown},
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{LogicValue::unknown,LogicValue::one, LogicValue::unknown, LogicValue::unknown, LogicValue::unknown},
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{LogicValue::unknown,LogicValue::one, LogicValue::unknown, LogicValue::unknown, LogicValue::unknown}};
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return logic_or[int(value1)][int(value2)];
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}
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static LogicValue
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logicAnd(LogicValue value1,
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LogicValue value2)
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{
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static LogicValue logic_and[5][5] =
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{{LogicValue::zero,LogicValue::zero, LogicValue::zero, LogicValue::zero, LogicValue::zero},
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{LogicValue::zero,LogicValue::one, LogicValue::unknown,LogicValue::unknown, LogicValue::unknown},
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{LogicValue::zero,LogicValue::unknown,LogicValue::unknown,LogicValue::unknown, LogicValue::unknown},
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{LogicValue::zero,LogicValue::unknown,LogicValue::unknown,LogicValue::unknown, LogicValue::unknown},
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{LogicValue::zero,LogicValue::unknown,LogicValue::unknown,LogicValue::unknown, LogicValue::unknown}};
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return logic_and[int(value1)][int(value2)];
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}
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static LogicValue
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logicXor(LogicValue value1,
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LogicValue value2)
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{
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static LogicValue logic_xor[5][5]=
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{{LogicValue::zero, LogicValue::one, LogicValue::unknown,LogicValue::unknown, LogicValue::unknown},
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{LogicValue::one, LogicValue::zero, LogicValue::unknown,LogicValue::unknown, LogicValue::unknown},
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{LogicValue::unknown,LogicValue::unknown,LogicValue::unknown,LogicValue::unknown, LogicValue::unknown},
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{LogicValue::unknown,LogicValue::unknown,LogicValue::unknown,LogicValue::unknown, LogicValue::unknown},
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{LogicValue::unknown,LogicValue::unknown,LogicValue::unknown,LogicValue::unknown, LogicValue::unknown}};
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return logic_xor[int(value1)][int(value2)];
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}
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static TimingSense
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senseNot(TimingSense sense)
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{
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static TimingSense sense_not[5] = {TimingSense::negative_unate,
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TimingSense::positive_unate,
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TimingSense::non_unate,
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TimingSense::none,
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TimingSense::unknown};
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return sense_not[int(sense)];
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}
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static TimingSense
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senseAndOr(TimingSense sense1,
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TimingSense sense2)
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{
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static TimingSense sense_and_or[5][5] =
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{{TimingSense::positive_unate, TimingSense::non_unate,
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TimingSense::non_unate, TimingSense::positive_unate, TimingSense::unknown},
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{TimingSense::non_unate, TimingSense::negative_unate,
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TimingSense::non_unate, TimingSense::negative_unate, TimingSense::unknown},
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{TimingSense::non_unate, TimingSense::non_unate, TimingSense::non_unate,
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TimingSense::non_unate, TimingSense::unknown},
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{TimingSense::positive_unate, TimingSense::negative_unate,
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TimingSense::non_unate, TimingSense::none, TimingSense::unknown},
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{TimingSense::unknown, TimingSense::unknown,
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TimingSense::unknown, TimingSense::non_unate, TimingSense::unknown}};
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return sense_and_or[int(sense1)][int(sense2)];
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}
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static TimingSense
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senseXor(TimingSense sense1,
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TimingSense sense2)
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{
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static TimingSense xor_sense[5][5] =
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{{TimingSense::non_unate, TimingSense::non_unate,
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TimingSense::non_unate, TimingSense::non_unate, TimingSense::unknown},
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{TimingSense::non_unate, TimingSense::non_unate,
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TimingSense::non_unate, TimingSense::non_unate, TimingSense::unknown},
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{TimingSense::non_unate, TimingSense::non_unate,
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TimingSense::non_unate, TimingSense::non_unate, TimingSense::unknown},
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{TimingSense::non_unate, TimingSense::non_unate,
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TimingSense::non_unate, TimingSense::none, TimingSense::unknown},
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{TimingSense::unknown, TimingSense::unknown,
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TimingSense::unknown, TimingSense::unknown, TimingSense::unknown}};
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return xor_sense[int(sense1)][int(sense2)];
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}
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TimingSense
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Sim::functionSense(const FuncExpr *expr,
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const Pin *input_pin,
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const Instance *inst)
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{
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TimingSense sense = TimingSense::none;
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LogicValue value = LogicValue::unknown;
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functionSense(expr, input_pin, inst, sense, value);
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return sense;
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}
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void
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Sim::functionSense(const FuncExpr *expr,
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const Pin *input_pin,
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const Instance *inst,
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// return values
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TimingSense &sense,
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LogicValue &value) const
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{
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switch (expr->op()) {
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case FuncExpr::op_port: {
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Pin *pin = network_->findPin(inst, expr->port());
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if (pin) {
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if (pin == input_pin)
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sense = TimingSense::positive_unate;
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else
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sense = TimingSense::none;
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value = logicValue(pin);
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}
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else {
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sense = TimingSense::none;
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value = LogicValue::unknown;
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}
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break;
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}
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case FuncExpr::op_not: {
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TimingSense sense1;
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LogicValue value1;
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functionSense(expr->left(), input_pin, inst, sense1, value1);
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if (value1 == LogicValue::zero) {
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sense = TimingSense::none;
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value = LogicValue::one;
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}
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else if (value1 == LogicValue::one) {
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sense = TimingSense::none;
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value = LogicValue::zero;
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}
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else {
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sense = senseNot(sense1);
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value = LogicValue::unknown;
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}
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break;
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}
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case FuncExpr::op_or: {
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TimingSense sense1, sense2;
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LogicValue value1, value2;
|
||||
functionSense(expr->left(), input_pin, inst, sense1, value1);
|
||||
functionSense(expr->right(), input_pin, inst, sense2, value2);
|
||||
if (value1 == LogicValue::one || value2 == LogicValue::one) {
|
||||
sense = TimingSense::none;
|
||||
value = LogicValue::one;
|
||||
}
|
||||
else if (value1 == LogicValue::zero) {
|
||||
sense = sense2;
|
||||
value = value2;
|
||||
}
|
||||
else if (value2 == LogicValue::zero) {
|
||||
sense = sense1;
|
||||
value = value1;
|
||||
}
|
||||
else {
|
||||
sense = senseAndOr(sense1, sense2);
|
||||
value = LogicValue::unknown;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case FuncExpr::op_and: {
|
||||
TimingSense sense1, sense2;
|
||||
LogicValue value1, value2;
|
||||
functionSense(expr->left(), input_pin, inst, sense1, value1);
|
||||
functionSense(expr->right(), input_pin, inst, sense2, value2);
|
||||
if (value1 == LogicValue::zero || value2 == LogicValue::zero) {
|
||||
sense = TimingSense::none;
|
||||
value = LogicValue::zero;
|
||||
}
|
||||
else if (value1 == LogicValue::one) {
|
||||
sense = sense2;
|
||||
value = value2;
|
||||
}
|
||||
else if (value2 == LogicValue::one) {
|
||||
sense = sense1;
|
||||
value = value1;
|
||||
}
|
||||
else {
|
||||
sense = senseAndOr(sense1, sense2);
|
||||
value = LogicValue::unknown;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case FuncExpr::op_xor: {
|
||||
TimingSense sense1, sense2;
|
||||
LogicValue value1, value2;
|
||||
functionSense(expr->left(), input_pin, inst, sense1, value1);
|
||||
functionSense(expr->right(), input_pin, inst, sense2, value2);
|
||||
if ((value1 == LogicValue::zero && value2 == LogicValue::zero)
|
||||
|| (value1 == LogicValue::one && value2 == LogicValue::one)) {
|
||||
sense = TimingSense::none;
|
||||
value = LogicValue::zero;
|
||||
}
|
||||
else if ((value1 == LogicValue::zero && value2 == LogicValue::one)
|
||||
|| (value1 == LogicValue::one && value2 == LogicValue::zero)) {
|
||||
sense = TimingSense::none;
|
||||
value = LogicValue::one;
|
||||
}
|
||||
else if (value1 == LogicValue::zero) {
|
||||
sense = sense2;
|
||||
value = value2;
|
||||
}
|
||||
else if (value1 == LogicValue::one) {
|
||||
sense = senseNot(sense2);
|
||||
value = logicNot(value2);
|
||||
}
|
||||
else if (value2 == LogicValue::zero) {
|
||||
sense = sense1;
|
||||
value = value1;
|
||||
}
|
||||
else if (value2 == LogicValue::one) {
|
||||
sense = senseNot(sense1);
|
||||
value = logicNot(value1);
|
||||
}
|
||||
else {
|
||||
sense = senseXor(sense1, sense2);
|
||||
value = logicXor(value1, value2);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case FuncExpr::op_one:
|
||||
sense = TimingSense::none;
|
||||
value = LogicValue::one;
|
||||
break;
|
||||
case FuncExpr::op_zero:
|
||||
sense = TimingSense::none;
|
||||
value = LogicValue::zero;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
LogicValue
|
||||
Sim::evalExpr(const FuncExpr *expr,
|
||||
const Instance *inst)
|
||||
{
|
||||
switch (expr->op()) {
|
||||
case FuncExpr::op_port: {
|
||||
LibertyPort *port = expr->port();
|
||||
if (port) {
|
||||
Pin *pin = network_->findPin(inst, port->name());
|
||||
if (pin)
|
||||
return logicValue(pin);
|
||||
}
|
||||
// Internal ports don't have instance pins.
|
||||
return LogicValue::unknown;
|
||||
}
|
||||
case FuncExpr::op_not:
|
||||
return logicNot(evalExpr(expr->left(), inst));
|
||||
case FuncExpr::op_or:
|
||||
return logicOr(evalExpr(expr->left(),inst),
|
||||
evalExpr(expr->right(),inst));
|
||||
case FuncExpr::op_and:
|
||||
return logicAnd(evalExpr(expr->left(),inst),
|
||||
evalExpr(expr->right(),inst));
|
||||
case FuncExpr::op_xor:
|
||||
return logicXor(evalExpr(expr->left(),inst),
|
||||
evalExpr(expr->right(),inst));
|
||||
case FuncExpr::op_one:
|
||||
return LogicValue::one;
|
||||
case FuncExpr::op_zero:
|
||||
return LogicValue::zero;
|
||||
}
|
||||
// Prevent warnings from lame compilers.
|
||||
return LogicValue::zero;
|
||||
}
|
||||
|
||||
#endif // CUDD
|
||||
|
||||
static LogicValue
|
||||
logicNot(LogicValue value)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -4,8 +4,6 @@
|
|||
|
||||
#cmakedefine ZLIB_FOUND
|
||||
|
||||
#define CUDD ${CUDD}
|
||||
|
||||
#define SSTA ${SSTA}
|
||||
|
||||
#define TCL_READLINE ${TCL_READLINE}
|
||||
|
|
|
|||
Loading…
Reference in New Issue