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network top instance name use cell name 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2025-01-15 17:22:22 -07:00
parent e7eebc98a3
commit e1b0aa8c9f
1 changed files with 1 additions and 1 deletions
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2
verilog/VerilogReader.cc
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@ -1822,7 +1822,7 @@ VerilogReader::linkNetwork(const char *top_cell_name,
VerilogModule *module = this->module(top_cell); VerilogModule *module = this->module(top_cell);
if (module) { if (module) {
// Seed the recursion for expansion with the top level instance. // Seed the recursion for expansion with the top level instance.
Instance *top_instance = network_->makeInstance(top_cell, "", nullptr); Instance *top_instance = network_->makeInstance(top_cell, top_cell_name, nullptr);
VerilogBindingTbl bindings(zero_net_name_, one_net_name_); VerilogBindingTbl bindings(zero_net_name_, one_net_name_);
VerilogNetSeq::Iterator port_iter(module->ports()); VerilogNetSeq::Iterator port_iter(module->ports());
while (port_iter.hasNext()) { while (port_iter.hasNext()) {