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made module deletion optional in linkNetwork (#200) 

* made module deletion optional in linkNetwork

Signed-off-by: Cho Moon <cmoon@precisioninno.com>

* merged with master

Signed-off-by: Cho Moon <cmoon@precisioninno.com>

---------

Signed-off-by: Cho Moon <cmoon@precisioninno.com>
This commit is contained in:
Cho Moon 2025-02-05 13:32:08 -08:00 committed by GitHub
parent b39ad56bc1
commit e04e9d1145
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GPG Key ID: B5690EEEBB952194
2 changed files with 7 additions and 4 deletions
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3
include/sta/VerilogReader.hh
View File

@ -147,7 +147,8 @@ public:
int to_index); int to_index);
VerilogModule *module(Cell *cell); VerilogModule *module(Cell *cell);
Instance *linkNetwork(const char *top_cell_name, Instance *linkNetwork(const char *top_cell_name,
bool make_black_boxes); bool make_black_boxes,
bool delete_modules);
const char *filename() const { return filename_.c_str(); } const char *filename() const { return filename_.c_str(); }
void incrLine(); void incrLine();
Report *report() const { return report_; } Report *report() const { return report_; }

8
verilog/VerilogReader.cc
View File

@ -146,7 +146,7 @@ VerilogReader::VerilogReader(NetworkReader *network) :
{ {
network->setLinkFunc([=] (const char *top_cell_name, network->setLinkFunc([=] (const char *top_cell_name,
bool make_black_boxes) -> Instance* { bool make_black_boxes) -> Instance* {
return linkNetwork(top_cell_name, make_black_boxes); return linkNetwork(top_cell_name, make_black_boxes, true);
}); });
constant10_max_ = stdstrPrint("%llu", std::numeric_limits<VerilogConstant10>::max()); constant10_max_ = stdstrPrint("%llu", std::numeric_limits<VerilogConstant10>::max());
} }
@ -1701,7 +1701,8 @@ private:
Instance * Instance *
VerilogReader::linkNetwork(const char *top_cell_name, VerilogReader::linkNetwork(const char *top_cell_name,
bool make_black_boxes) bool make_black_boxes,
bool delete_modules)
{ {
if (library_) { if (library_) {
Cell *top_cell = network_->findCell(library_, top_cell_name); Cell *top_cell = network_->findCell(library_, top_cell_name);
@ -1729,7 +1730,8 @@ VerilogReader::linkNetwork(const char *top_cell_name,
} }
makeModuleInstBody(module, top_instance, &bindings, make_black_boxes); makeModuleInstBody(module, top_instance, &bindings, make_black_boxes);
bool errors = reportLinkErrors(); bool errors = reportLinkErrors();
deleteModules(); if (delete_modules)
deleteModules();
if (errors) { if (errors) {
network_->deleteInstance(top_instance); network_->deleteInstance(top_instance);
return nullptr; return nullptr;