rename examples
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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doc/OpenSTA.odt
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doc/OpenSTA.pdf
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# delay calc example
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read_liberty example1_slow.lib
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read_liberty nangate45_slow.lib
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read_verilog example1.v
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link_design top
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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# 3 corners with +/- 10% derating example
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define_corners ss tt ff
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read_liberty -corner ss example1_slow.lib
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read_liberty -corner tt example1_typ.lib
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read_liberty -corner ff example1_fast.lib
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read_liberty -corner ss nangate45_slow.lib
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read_liberty -corner tt nangate45_typ.lib
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read_liberty -corner ff nangate45_fast.lib
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read_verilog example1.v
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link_design top
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set_timing_derate -early 0.9
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# min/max delay calc example
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read_liberty -max example1_slow.lib
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read_liberty -min example1_fast.lib
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read_liberty -max nangate45_slow.lib
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read_liberty -min nangate45_fast.lib
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read_verilog example1.v
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link_design top
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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# 3 corners with +/- 10% derating example
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define_corners ss tt ff
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read_liberty -corner ss nangate45_slow.lib
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read_liberty -corner tt nangate45_typ.lib
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read_liberty -corner ff nangate45_fast.lib
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read_verilog example1.v
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link_design top
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set_timing_derate -early 0.9
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set_timing_derate -late 1.1
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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# report all corners
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report_checks -path_delay min_max
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# report typical corner
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report_checks -corner tt
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# sdf example
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read_liberty example1_slow.lib
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read_liberty nangate45_slow.lib
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read_verilog example1.v
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link_design top
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read_sdf example1.sdf
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# delay calc example with parasitics
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read_liberty example1_slow.lib
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# delay calc with spef parasitics
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read_liberty nangate45_slow.lib
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read_verilog example1.v
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link_design top
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read_spef example1.dspef
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