Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenSTA into secure-test-suite-cleanup
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
This commit is contained in:
commit
d6a80441e4
|
|
@ -0,0 +1,20 @@
|
||||||
|
name: Check that OK files are up to date
|
||||||
|
|
||||||
|
on:
|
||||||
|
pull_request:
|
||||||
|
|
||||||
|
jobs:
|
||||||
|
No-Diffs-In-Ok-Files:
|
||||||
|
runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
|
||||||
|
steps:
|
||||||
|
- name: Check out repository code
|
||||||
|
uses: actions/checkout@v6
|
||||||
|
with:
|
||||||
|
fetch-depth: 0
|
||||||
|
- name: Check ok files
|
||||||
|
run: |
|
||||||
|
set +e
|
||||||
|
grep --include="*.ok" -Rn "Differences found "
|
||||||
|
if [[ "$?" == "0" ]]; then
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
|
@ -647,6 +647,4 @@ Timing arcs
|
||||||
combinational
|
combinational
|
||||||
^ -> v
|
^ -> v
|
||||||
v -> ^
|
v -> ^
|
||||||
Differences found at line 107.
|
No differences found.
|
||||||
cell_rise(Timing_7_7) {
|
|
||||||
cell_rise(Timing_7_7) {
|
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,12 +1,6 @@
|
||||||
Differences found at line 107.
|
No differences found.
|
||||||
cell_rise(Timing_7_7) {
|
No differences found.
|
||||||
cell_rise(Timing_7_7) {
|
No differences found.
|
||||||
Differences found at line 118.
|
|
||||||
cell_rise(del_1_7_7) {
|
|
||||||
cell_rise(del_1_7_7) {
|
|
||||||
Differences found at line 70.
|
|
||||||
cell_rise(TIMING_DELAY_7x7ds1) {
|
|
||||||
cell_rise(TIMING_DELAY_7x7ds1) {
|
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||||
|
|
@ -17,18 +11,10 @@ Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||||
Differences found at line 83.
|
No differences found.
|
||||||
cell_rise(delay_template_7x7_x1) {
|
No differences found.
|
||||||
cell_rise(delay_template_7x7_x1) {
|
No differences found.
|
||||||
Differences found at line 81.
|
No differences found.
|
||||||
cell_rise(delay_template_7x7) {
|
|
||||||
cell_rise(delay_template_7x7) {
|
|
||||||
Differences found at line 83.
|
|
||||||
cell_rise(delay_template_7x7_x1) {
|
|
||||||
cell_rise(delay_template_7x7_x1) {
|
|
||||||
Differences found at line 90.
|
|
||||||
cell_rise(fakeram7_256x32_mem_out_delay_template) {
|
|
||||||
cell_rise(fakeram7_256x32_mem_out_delay_template) {
|
|
||||||
Warning 1171: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
|
Warning 1171: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13156, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13156, timing group from output port.
|
||||||
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13189, timing group from output port.
|
Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13189, timing group from output port.
|
||||||
|
|
|
||||||
|
|
@ -1,9 +1,5 @@
|
||||||
Differences found at line 107.
|
No differences found.
|
||||||
cell_rise(Timing_7_7) {
|
No differences found.
|
||||||
cell_rise(Timing_7_7) {
|
|
||||||
Differences found at line 118.
|
|
||||||
cell_rise(del_1_7_7) {
|
|
||||||
cell_rise(del_1_7_7) {
|
|
||||||
INV_X1: 1 arc sets
|
INV_X1: 1 arc sets
|
||||||
rise->fall
|
rise->fall
|
||||||
fall->rise
|
fall->rise
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -30,6 +30,4 @@ filter_pins direction == input: 1
|
||||||
filter_nets full_name =~ n*: 7
|
filter_nets full_name =~ n*: 7
|
||||||
No differences found.
|
No differences found.
|
||||||
remove_constraints: skipped (API removed)
|
remove_constraints: skipped (API removed)
|
||||||
Differences found at line 10.
|
No differences found.
|
||||||
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
|
|
||||||
create_clock -name vclk -period 5.0000
|
|
||||||
|
|
|
||||||
|
|
@ -7,11 +7,23 @@ current_design sdc_test2
|
||||||
###############################################################################
|
###############################################################################
|
||||||
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
|
create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
|
||||||
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
|
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
|
||||||
|
create_clock -name vclk -period 5.0000
|
||||||
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
|
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
|
||||||
|
set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
|
||||||
|
set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
|
||||||
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
|
set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
|
||||||
|
set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
|
||||||
|
group_path -name grp_reg2reg\
|
||||||
|
-from [get_clocks {clk1}]\
|
||||||
|
-to [get_clocks {clk1}]
|
||||||
|
group_path -name grp_io\
|
||||||
|
-from [list [get_ports {in1}]\
|
||||||
|
[get_ports {in2}]]\
|
||||||
|
-to [get_ports {out1}]
|
||||||
###############################################################################
|
###############################################################################
|
||||||
# Environment
|
# Environment
|
||||||
###############################################################################
|
###############################################################################
|
||||||
|
set_logic_zero [get_ports {in3}]
|
||||||
###############################################################################
|
###############################################################################
|
||||||
# Design Rules
|
# Design Rules
|
||||||
###############################################################################
|
###############################################################################
|
||||||
|
|
|
||||||
|
|
@ -54,7 +54,6 @@ Path Type: min
|
||||||
-0.05 slack (VIOLATED)
|
-0.05 slack (VIOLATED)
|
||||||
|
|
||||||
|
|
||||||
Warning: util_report_string_log.tcl line 1, unknown field nets.
|
|
||||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||||
Path Group: clk
|
Path Group: clk
|
||||||
|
|
|
||||||
|
|
@ -64,7 +64,6 @@ Path Type: min
|
||||||
|
|
||||||
|
|
||||||
No paths found.
|
No paths found.
|
||||||
Warning 168: util_log_redirect.tcl line 1, unknown field nets.
|
|
||||||
Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||||
Endpoint: out (output port clocked by clk)
|
Endpoint: out (output port clocked by clk)
|
||||||
Path Group: clk
|
Path Group: clk
|
||||||
|
|
@ -76,6 +75,7 @@ Fanout Cap Slew Delay Time Description
|
||||||
0.00 0.00 clock network delay (ideal)
|
0.00 0.00 clock network delay (ideal)
|
||||||
0.00 0.00 0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
0.00 0.00 0.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||||
1 0.00 0.01 0.04 0.04 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
|
1 0.00 0.01 0.04 0.04 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
|
||||||
|
out (net)
|
||||||
0.00 0.00 0.04 ^ out (out)
|
0.00 0.00 0.04 ^ out (out)
|
||||||
0.04 data arrival time
|
0.04 data arrival time
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -30,7 +30,7 @@ log_begin $log_file1
|
||||||
report_checks
|
report_checks
|
||||||
report_checks -path_delay min
|
report_checks -path_delay min
|
||||||
report_checks -from [get_ports in1] -to [get_ports out]
|
report_checks -from [get_ports in1] -to [get_ports out]
|
||||||
report_checks -fields {slew cap input_pins nets fanout}
|
report_checks -fields {slew cap input_pins net fanout}
|
||||||
report_units
|
report_units
|
||||||
|
|
||||||
log_end
|
log_end
|
||||||
|
|
|
||||||
|
|
@ -310,9 +310,7 @@ Path Type: max
|
||||||
current 1mA
|
current 1mA
|
||||||
power 1nW
|
power 1nW
|
||||||
distance 1um
|
distance 1um
|
||||||
Differences found at line 57.
|
No differences found.
|
||||||
Warning: util_report_string_log.tcl line 1, unknown field nets.
|
|
||||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
|
||||||
--- Test 2: log + redirect simultaneous ---
|
--- Test 2: log + redirect simultaneous ---
|
||||||
No differences found.
|
No differences found.
|
||||||
No differences found.
|
No differences found.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue