luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #393 from The-OpenROAD-Project-staging/sta_update_0725 

Sta update 0725
This commit is contained in:
Matt Liberty 2026-07-27 14:17:44 +00:00 committed by GitHub
parent 3ce15f0f72 de61cd0845
commit d468d14fdc
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
27 changed files with 452 additions and 544 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
.github/workflows/ci.yml vendored
View File

@ -5,7 +5,8 @@ on:
pull_request:
jobs:
build:
# Primary native Linux build used for install artifacts.
linux-ubuntu:
if: github.repository_owner != 'The-OpenROAD-Project-private'
runs-on: ubuntu-latest
steps:
@ -51,7 +52,7 @@ jobs:
uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1
if: ${{ !cancelled() }}
with:
name: artifact
name: artifact-ubuntu
path: |
build/install/*
retention-days: 1
@ -60,6 +61,78 @@ jobs:
uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1
if: ${{ !cancelled() }}
with:
name: result
name: result-ubuntu
path: |
test/results/*
# CentOS 7 Docker: old platform still common in EDA environments.
linux-centos:
if: github.repository_owner != 'The-OpenROAD-Project-private'
runs-on: ubuntu-latest
timeout-minutes: 30
steps:
- name: Checkout
uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0 # v7.0.0
with:
submodules: true
- name: Build image
run: docker build -f Dockerfile.centos7 --tag sta-centos7 .
- name: Test in container
run: |
mkdir -p test/results
docker run --rm \
-v "$PWD/test/results:/OpenSTA/test/results" \
--entrypoint /bin/bash sta-centos7 \
-c "cd /OpenSTA/test && ./regression || (cat results/diffs && exit 1)"
- name: Upload Test Result
uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1
if: ${{ !cancelled() }}
with:
name: result-centos7
path: |
test/results/*
# Native macOS coverage via Brewfile.
macos:
if: github.repository_owner != 'The-OpenROAD-Project-private'
runs-on: macos-latest
timeout-minutes: 30
steps:
- name: Checkout
uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0 # v7.0.0
with:
submodules: true
- name: Install dependencies
run: brew bundle
- name: Build
run: |
eval "$(/opt/homebrew/bin/brew shellenv)"
export PATH="$(brew --prefix flex)/bin:$PATH"
export PATH="$(brew --prefix bison)/bin:$PATH"
export TCL_LIBRARY="$(brew --prefix tcl-tk@8)/lib/libtcl8.6.dylib"
export TCL_INCLUDE_PATH="$(brew --prefix tcl-tk@8)/include/tcl-tk"
export FLEX_INCLUDE_DIR="$(brew --prefix flex)/include"
cmake -S . -B build \
-D TCL_LIBRARY=$TCL_LIBRARY \
-D TCL_INCLUDE_PATH=$TCL_INCLUDE_PATH \
-D FLEX_INCLUDE_DIR=$FLEX_INCLUDE_DIR \
-DCMAKE_BUILD_TYPE=Release
cmake --build build -j "$(sysctl -n hw.ncpu)"
- name: Test
run: |
cd test
./regression || (cat results/diffs && exit 1)
- name: Upload Test Result
uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1
if: ${{ !cancelled() }}
with:
name: result-macos
path: |
test/results/*

0
BUILD → BUILD.bazel
View File

3
Brewfile
View File

@ -2,8 +2,9 @@ brew "bison"
brew "cmake"
brew "eigen"
brew "flex"
brew "googletest"
brew "swig"
brew "tcl-tk@8"
tap "mht208/formal"
brew "mht208/formal/cudd"
brew "mht208/formal/cudd", trusted: true

10
Dockerfile.centos7
View File

@ -14,10 +14,11 @@ RUN sed -i s/mirror.centos.org/vault.centos.org/g /etc/yum.repos.d/*.repo \
&& yum install -y devtoolset-11 git wget cmake3 make eigen3-devel tcl swig3 flex zlib-devel valgrind \
&& yum clean -y all
RUN ln -sf /usr/bin/cmake3 /usr/bin/cmake
RUN ln -sf /usr/bin/cmake3 /usr/bin/cmake && \
ln -sf /usr/bin/ctest3 /usr/bin/ctest
# Download Bison
RUN wget https://ftp.gnu.org/gnu/bison/bison-3.8.2.tar.gz && \
RUN wget https://mirrors.kernel.org/gnu/bison/bison-3.8.2.tar.gz && \
tar -xvf bison-3.8.2.tar.gz && \
rm bison-3.8.2.tar.gz
@ -42,8 +43,9 @@ RUN source /opt/rh/devtoolset-11/enable && \
make install
# Download TCL
RUN wget http://prdownloads.sourceforge.net/tcl/tcl8.6.16-src.tar.gz && \
tar -xvf tcl8.6.16-src.tar.gz && \
RUN wget https://github.com/tcltk/tcl/archive/refs/tags/core-8-6-16.tar.gz -O tcl8.6.16-src.tar.gz && \
mkdir -p tcl8.6.16 && \
tar -xvf tcl8.6.16-src.tar.gz -C tcl8.6.16 --strip-components=1 && \
rm tcl8.6.16-src.tar.gz
# Build TCL

122
dcalc/GraphDelayCalc.cc
View File

@ -213,7 +213,6 @@ GraphDelayCalc::delaysInvalid()
debugPrint(debug_, "delay_calc", 1, "delays invalid");
delays_exist_ = false;
delays_seeded_ = false;
incremental_ = false;
iter_->clear();
// No need to keep track of incremental updates any more.
invalid_delays_.clear();
@ -224,7 +223,7 @@ GraphDelayCalc::delaysInvalid()
void
GraphDelayCalc::delayInvalid(const Pin *pin)
{
if (graph_ && incremental_) {
if (graph_ && delays_exist_) {
if (network_->isHierarchical(pin)) {
EdgesThruHierPinIterator edge_iter(pin, network_, graph_);
while (edge_iter.hasNext()) {
@ -248,7 +247,7 @@ GraphDelayCalc::delayInvalid(Vertex *vertex)
{
debugPrint(debug_, "delay_calc", 2, "delay invalid {}",
vertex->to_string(this));
if (incremental_) {
if (delays_exist_) {
invalid_delays_.insert(vertex);
// Invalidate driver that triggers dcalc for multi-driver nets.
MultiDrvrNet *multi_drvr = multiDrvrNet(vertex);
@ -274,7 +273,7 @@ void
GraphDelayCalc::deleteVertexBefore(Vertex *vertex)
{
iter_->deleteVertexBefore(vertex);
if (incremental_)
if (delays_exist_)
invalid_delays_.erase(vertex);
MultiDrvrNet *multi_drvr = multiDrvrNet(vertex);
if (multi_drvr) {
@ -329,7 +328,7 @@ FindVertexDelays::copy() const
void
FindVertexDelays::visit(Vertex *vertex)
{
graph_delay_calc_->findVertexDelay(vertex, arc_delay_calc_, true);
graph_delay_calc_->findVertexDelay(vertex, arc_delay_calc_);
}
// The logical structure of incremental delay calculation closely
@ -348,7 +347,7 @@ GraphDelayCalc::findDelays(Level level)
}
else
iter_->ensureSize();
if (incremental_)
if (delays_exist_)
seedInvalidDelays();
if (!iter_->empty()) {
@ -367,7 +366,6 @@ GraphDelayCalc::findDelays(Level level)
invalid_latch_edges_.clear();
delays_exist_ = true;
incremental_ = true;
debugPrint(debug_, "delay_calc", 1, "found {} delays", dcalc_count);
stats.report("Delay calc");
}
@ -674,13 +672,12 @@ GraphDelayCalc::findInputArcDelay(const Pin *drvr_pin,
void
GraphDelayCalc::findDelays(Vertex *drvr_vertex)
{
findVertexDelay(drvr_vertex, arc_delay_calc_, true);
findVertexDelay(drvr_vertex, arc_delay_calc_);
}
void
GraphDelayCalc::findVertexDelay(Vertex *vertex,
ArcDelayCalc *arc_delay_calc,
bool propagate)
ArcDelayCalc *arc_delay_calc)
{
const Pin *pin = vertex->pin();
debugPrint(debug_, "delay_calc", 2, "find delays {} ({})",
@ -692,32 +689,38 @@ GraphDelayCalc::findVertexDelay(Vertex *vertex,
|| (vertex->isBidirectDriver()
&& network_->isTopLevelPort(pin)))
seedRootSlew(vertex, arc_delay_calc);
else {
if (network_->isLeaf(pin)) {
if (vertex->isDriver(network_)) {
LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(vertex);
DrvrLoadSlews load_slews_prev;
if (incremental_)
load_slews_prev = loadSlews(load_pin_index_map);
findDriverDelays(vertex, arc_delay_calc, load_pin_index_map);
if (propagate) {
if (network_->direction(pin)->isInternal())
enqueueTimingChecksEdges(vertex);
// Enqueue adjacent vertices even if the load slews did not
// change when non-incremental to stride past annotations.
if (!incremental_
|| loadSlewsChanged(load_slews_prev, load_pin_index_map))
iter_->enqueueFanout(vertex);
}
}
else {
// Load vertex.
enqueueTimingChecksEdges(vertex);
// Enqueue driver vertices from this input load.
if (propagate)
iter_->enqueueFanout(vertex);
}
}
else if (network_->isLeaf(pin)
&& vertex->isDriver(network_)) {
LoadPinIndexMap load_pin_index_map = makeLoadPinIndexMap(vertex);
DrvrLoadSlews load_slews_prev;
if (delays_exist_)
load_slews_prev = loadSlews(load_pin_index_map);
findDriverDelays(vertex, arc_delay_calc, load_pin_index_map);
if (network_->direction(pin)->isInternal())
enqueueCheckEdges(vertex);
graph_->visitFanouts(vertex, search_non_latch_pred_,
[this, &load_slews_prev, &load_pin_index_map]
(Vertex *fanout) {
// Enqueue adjacent vertices even if the load slew
// did not change when non-incremental to stride
// past annotations.
if (!delays_exist_
|| loadSlewChanged(fanout, load_slews_prev,
load_pin_index_map)) {
iter_->enqueue(fanout);
fanout->setBfsPredecessorChanged(true);
}
});
}
else if (vertex->isLoad(network_)) {
// Load vertex.
// Includes top level bidirect load vertex with wire edge to bidirect driver.
enqueueCheckEdges(vertex);
graph_->visitFanouts(vertex, search_non_latch_pred_,
[this] (Vertex *fanout) {
iter_->enqueue(fanout);
fanout->setBfsPredecessorChanged(true);
});
}
}
@ -737,24 +740,25 @@ GraphDelayCalc::loadSlews(LoadPinIndexMap &load_pin_index_map)
}
bool
GraphDelayCalc::loadSlewsChanged(DrvrLoadSlews &load_slews_prev,
LoadPinIndexMap &load_pin_index_map)
GraphDelayCalc::loadSlewChanged(Vertex *load_vertex,
DrvrLoadSlews &load_slews_prev,
LoadPinIndexMap &load_pin_index_map)
{
if (load_slews_prev.empty())
return true;
size_t index = load_pin_index_map[load_vertex->pin()];
SlewSeq &slews_prev = load_slews_prev[index];;
size_t slew_count = graph_->slewCount();
for (auto const [pin, index] : load_pin_index_map) {
Vertex *load_vertex = graph_->pinLoadVertex(pin);
SlewSeq &slews_prev = load_slews_prev[index];;
for (size_t i = 0; i < slew_count; i++) {
const Slew slew = graph_->slew(load_vertex, i);
if (!delayEqual(slew, slews_prev[i], this))
return true;
}
for (size_t i = 0; i < slew_count; i++) {
const Slew slew = graph_->slew(load_vertex, i);
if (!delayEqual(slew, slews_prev[i], this))
return true;
}
return false;
}
void
GraphDelayCalc::enqueueTimingChecksEdges(Vertex *vertex)
GraphDelayCalc::enqueueCheckEdges(Vertex *vertex)
{
if (vertex->hasChecks()) {
VertexInEdgeIterator edge_iter(vertex, graph_);
@ -1180,10 +1184,10 @@ GraphDelayCalc::annotateDelaysSlews(Edge *edge,
dcalc_result.drvrSlew(), scene, min_max);
if (!edge->role()->isLatchDtoQ()) {
Vertex *drvr_vertex = edge->to(graph_);
delay_changed |= annotateLoadDelays(drvr_vertex, arc->toEdge()->asRiseFall(),
dcalc_result,
load_pin_index_map, delay_zero, true,
scene, min_max);
annotateLoadDelays(drvr_vertex, arc->toEdge()->asRiseFall(),
dcalc_result,
load_pin_index_map, delay_zero, true,
scene, min_max);
}
return delay_changed;
}
@ -1238,7 +1242,7 @@ GraphDelayCalc::annotateDelaySlew(Edge *edge,
// Annotate wire arc delays and load pin slews.
// extra_delay is additional wire delay to add to delay returned
// by the delay calculator.
bool
void
GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex,
const RiseFall *drvr_rf,
ArcDcalcResult &dcalc_result,
@ -1249,7 +1253,6 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex,
const MinMax *min_max)
{
DcalcAPIndex ap_index = scene->dcalcAnalysisPtIndex(min_max);
bool changed = false;
VertexOutEdgeIterator edge_iter(drvr_vertex, graph_);
while (edge_iter.hasNext()) {
Edge *wire_edge = edge_iter.next();
@ -1264,20 +1267,17 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex,
load_vertex->to_string(this),
delayAsString(wire_delay, this),
delayAsString(load_slew, this));
bool load_changed = false;
if (!load_vertex->slewAnnotated(drvr_rf, min_max)) {
if (drvr_vertex->slewAnnotated(drvr_rf, min_max)) {
// Copy the driver slew to the load if it is annotated.
const Slew drvr_slew = graph_->slew(drvr_vertex, drvr_rf, ap_index);
graph_->setSlew(load_vertex, drvr_rf, ap_index, drvr_slew);
load_changed = true;
}
else {
const Slew slew = graph_->slew(load_vertex, drvr_rf, ap_index);
if (!merge
|| delayGreater(load_slew, slew, min_max, this)) {
graph_->setSlew(load_vertex, drvr_rf, ap_index, load_slew);
load_changed = true;
}
}
}
@ -1290,18 +1290,12 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex,
if (!merge
|| delayGreater(wire_delay_extra, delay, min_max, this)) {
graph_->setWireArcDelay(wire_edge, drvr_rf, ap_index, wire_delay_extra);
load_changed = true;
if (observer_)
observer_->delayChangedTo(load_vertex);
}
}
if (load_changed && observer_)
observer_->delayChangedTo(load_vertex);
// Enqueue bidirect driver from load vertex.
if (bidirectDrvrSlewFromLoad(load_pin))
iter_->enqueue(graph_->pinDrvrVertex(load_pin));
changed |= load_changed;
}
}
return changed;
}
LoadPinIndexMap

1
dcalc/PrimaDelayCalc.cc
View File

@ -65,7 +65,6 @@ PrimaDelayCalc::PrimaDelayCalc(StaState *sta) :
PrimaDelayCalc::PrimaDelayCalc(const PrimaDelayCalc &dcalc) :
DelayCalcBase(dcalc),
pin_node_map_(network_),
node_index_map_(dcalc.node_index_map_),
prima_order_(dcalc.prima_order_),
watch_pin_values_(network_),
table_dcalc_(makeDmpCeffElmoreDelayCalc(this))

370
doc/OpenSTA.fodt
View File

File diff suppressed because it is too large Load Diff

BIN
doc/OpenSTA.pdf
View File

Binary file not shown.

26
graph/Graph.cc
View File

@ -1045,7 +1045,6 @@ Vertex::init(Pin *pin,
slews_ = nullptr;
paths_ = nullptr;
tag_group_index_ = tag_group_index_max;
bfs_in_queue_ = 0;
is_bidirect_drvr_ = is_bidirect_drvr;
is_reg_clk_ = is_reg_clk;
has_checks_ = false;
@ -1056,6 +1055,8 @@ Vertex::init(Pin *pin,
has_sim_value_ = false;
level_ = 0;
slew_annotated_ = false;
bfs_in_queue_ = 0;
bfs_predecessor_changed_ = false;
}
Vertex::~Vertex()
@ -1115,6 +1116,23 @@ Vertex::isDriver(const Network *network) const
|| dir->isInternal())));
}
bool
Vertex::isLoad(const Network *network) const
{
PortDirection *dir = network->direction(pin_);
bool top_level_port = network->isTopLevelPort(pin_);
return ((top_level_port
&& (dir->isOutput()
|| (dir->isBidirect()
&& !is_bidirect_drvr_)))
|| (!top_level_port
&& (dir->isInput()
|| dir->isTristate()
|| (dir->isBidirect()
&& !is_bidirect_drvr_)
|| dir->isInternal())));
}
void
Vertex::setLevel(Level level)
{
@ -1264,6 +1282,12 @@ Vertex::setBfsInQueue(BfsIndex index,
bfs_in_queue_ &= ~(1 << static_cast<unsigned>(index));
}
void
Vertex::setBfsPredecessorChanged(bool changed)
{
bfs_predecessor_changed_ = changed;
}
////////////////////////////////////////////////////////////////
//
// Edge

9
include/sta/Graph.hh
View File

@ -255,6 +255,7 @@ public:
std::string name(const Network *network) const;
[[nodiscard]] bool isBidirectDriver() const { return is_bidirect_drvr_; }
[[nodiscard]] bool isDriver(const Network *network) const;
[[nodiscard]] bool isLoad(const Network *network) const;
Level level() const { return level_; }
void setLevel(Level level);
[[nodiscard]] bool visited() const { return visited1_; }
@ -286,13 +287,16 @@ public:
void setIsCheckClk(bool is_check_clk);
[[nodiscard]] bool hasDownstreamClkPin() const { return has_downstream_clk_pin_; }
void setHasDownstreamClkPin(bool has_clk_pin);
[[nodiscard]] bool bfsInQueue(BfsIndex index) const;
void setBfsInQueue(BfsIndex index, bool value);
[[nodiscard]] bool isRegClk() const { return is_reg_clk_; }
// Has sim value in some mode.
[[nodiscard]] bool hasSimValue() const { return has_sim_value_; }
void setHasSimValue(bool has_sim);
[[nodiscard]] bool bfsInQueue(BfsIndex index) const;
void setBfsInQueue(BfsIndex index, bool value);
[[nodiscard]] bool bfsPredecessorChanged() const { return bfs_predecessor_changed_; }
void setBfsPredecessorChanged(bool changed);
// ObjectTable interface.
[[nodiscard]] ObjectIdx objectIdx() const { return object_idx_; }
void setObjectIdx(ObjectIdx idx);
@ -335,6 +339,7 @@ protected:
unsigned int has_downstream_clk_pin_:1;
unsigned int visited1_:1;
unsigned int visited2_:1;
unsigned int bfs_predecessor_changed_:1;
unsigned int has_sim_value_:1;
int level_:Graph::vertex_level_bits; // 24
unsigned int slew_annotated_:slew_annotated_bits; // 4

13
include/sta/GraphDelayCalc.hh
View File

@ -232,12 +232,12 @@ protected:
void zeroSlewAndWireDelays(Vertex *drvr_vertex,
const RiseFall *rf);
void findVertexDelay(Vertex *vertex,
ArcDelayCalc *arc_delay_calc,
bool propagate);
ArcDelayCalc *arc_delay_calc);
DrvrLoadSlews loadSlews(LoadPinIndexMap &load_pin_index_map);
bool loadSlewsChanged(DrvrLoadSlews &load_slews_prev,
LoadPinIndexMap &load_pin_index_map);
void enqueueTimingChecksEdges(Vertex *vertex);
void enqueueCheckEdges(Vertex *vertex);
bool loadSlewChanged(Vertex *load_vertex,
DrvrLoadSlews &load_slews_prev,
LoadPinIndexMap &load_pin_index_map);
bool annotateDelaysSlews(Edge *edge,
const TimingArc *arc,
ArcDcalcResult &dcalc_result,
@ -251,7 +251,7 @@ protected:
const Slew &gate_slew,
const Scene *scene,
const MinMax *min_max);
bool annotateLoadDelays(Vertex *drvr_vertex,
void annotateLoadDelays(Vertex *drvr_vertex,
const RiseFall *drvr_rf,
ArcDcalcResult &dcalc_result,
LoadPinIndexMap &load_pin_index_map,
@ -296,7 +296,6 @@ protected:
// Observer for edge delay changes.
DelayCalcObserver *observer_{nullptr};
bool delays_seeded_{false};
bool incremental_{false};
bool delays_exist_{false};
// Vertices with invalid -to delays.
VertexSet invalid_delays_;

2
include/sta/Sta.hh
View File

@ -1008,6 +1008,8 @@ public:
void reportPathEnds(PathEndSeq *ends);
ReportPath *reportPath() { return report_path_; }
void reportPath(const Path *path);
// For debugging.
void reportPathVerbose(const Path *path);
// Report clk skews for clks.
void reportClkSkew(ConstClockSeq &clks,

4
include/sta/StaState.hh
View File

@ -100,7 +100,7 @@ public:
const DelayOps *delayOps() const { return delay_ops_; }
Latches *latches() { return latches_; }
Latches *latches() const { return latches_; }
unsigned threadCount() const { return thread_count_; }
size_t threadCount() const { return thread_count_; }
bool crprActive(const Mode *mode) const;
Variables *variables() { return variables_; }
const Variables *variables() const { return variables_; }
@ -139,7 +139,7 @@ protected:
DelayOps *delay_ops_;
Latches *latches_;
Variables *variables_;
int thread_count_;
size_t thread_count_;
DispatchQueue *dispatch_queue_;
};

240
power/test/power_vcd_detailed.ok
View File

@ -3245,246 +3245,6 @@ cells for instance power: 237
"total": 1.73e-08
}
]
Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------
1.174424e-05 5.011340e-06 8.463559e-12 1.675559e-05 _430_
9.018919e-06 6.474686e-06 8.933984e-12 1.549361e-05 _411_
9.015575e-06 2.486240e-06 8.626695e-12 1.150182e-05 _413_
1.016871e-05 1.049689e-06 8.326687e-12 1.121841e-05 _434_
9.828410e-06 1.173087e-06 8.449574e-12 1.100151e-05 _431_
9.828410e-06 1.173087e-06 8.448368e-12 1.100151e-05 _432_
9.650914e-06 1.049604e-06 8.436112e-12 1.070053e-05 _433_
9.121684e-06 1.024864e-06 8.416603e-12 1.014656e-05 _416_
9.240510e-06 4.218350e-07 8.620698e-12 9.662353e-06 _414_
8.899602e-06 6.959584e-07 8.501274e-12 9.595568e-06 _417_
8.766455e-06 7.974288e-07 8.446091e-12 9.563892e-06 _415_
8.941510e-06 5.457585e-07 8.253521e-12 9.487277e-06 _435_
8.918108e-06 2.286144e-07 8.184993e-12 9.146730e-06 _412_
8.760266e-06 3.348475e-07 8.203663e-12 9.095122e-06 _437_
8.586874e-06 3.928176e-07 8.253521e-12 8.979699e-06 _436_
8.246014e-06 1.901621e-07 8.568300e-12 8.436184e-06 _426_
8.245739e-06 1.708322e-07 8.568300e-12 8.416579e-06 _422_
8.245535e-06 1.474978e-07 8.568300e-12 8.393042e-06 _442_
8.245527e-06 1.463962e-07 8.568300e-12 8.391931e-06 _438_
8.245307e-06 1.015675e-07 8.568300e-12 8.346883e-06 _425_
8.245303e-06 1.009260e-07 8.568300e-12 8.346236e-06 _420_
8.245141e-06 9.556703e-08 8.568300e-12 8.340716e-06 _419_
8.232150e-06 1.003104e-07 8.049150e-12 8.332468e-06 _421_
8.232020e-06 1.000188e-07 8.049150e-12 8.332047e-06 _439_
8.232133e-06 9.909215e-08 8.049150e-12 8.331233e-06 _418_
8.245089e-06 8.449920e-08 8.568300e-12 8.329596e-06 _424_
8.232102e-06 8.743463e-08 8.049150e-12 8.319545e-06 _428_
8.231896e-06 8.752535e-08 8.049150e-12 8.319429e-06 _440_
8.231914e-06 7.848575e-08 8.049150e-12 8.310408e-06 _444_
8.231912e-06 7.724159e-08 8.049150e-12 8.309162e-06 _445_
8.232061e-06 7.656120e-08 8.049150e-12 8.308631e-06 _429_
8.231914e-06 7.280280e-08 8.049150e-12 8.304725e-06 _427_
8.231913e-06 7.256303e-08 8.049150e-12 8.304484e-06 _423_
8.231883e-06 7.041167e-08 8.049150e-12 8.302302e-06 _443_
8.231804e-06 5.765256e-08 8.049150e-12 8.289465e-06 _441_
1.677677e-06 3.896359e-06 4.529929e-12 5.574040e-06 _298_
1.331134e-06 4.080767e-06 4.711869e-12 5.411905e-06 _351_
2.213535e-06 3.066634e-06 5.153234e-12 5.280174e-06 _295_
3.202590e-06 1.266451e-06 8.810279e-12 4.469050e-06 _214_
1.404524e-06 2.215648e-06 4.360423e-12 3.620177e-06 _219_
6.102509e-07 2.941835e-06 4.944441e-12 3.552091e-06 _286_
1.132002e-06 2.244095e-06 6.352079e-12 3.376103e-06 _297_
2.811060e-06 2.415420e-07 1.081388e-11 3.052613e-06 _252_
2.452283e-06 3.962520e-07 8.217274e-12 2.848543e-06 _246_
1.000493e-06 1.833814e-06 3.203378e-12 2.834310e-06 _293_
1.244743e-06 1.531891e-06 9.375899e-12 2.776644e-06 _284_
1.818833e-06 9.046079e-07 4.020658e-12 2.723445e-06 _218_
1.738780e-06 8.322393e-07 3.476249e-12 2.571023e-06 _215_
1.702997e-06 8.322393e-07 3.269918e-12 2.535240e-06 _216_
1.178691e-06 1.347321e-06 9.205544e-13 2.526013e-06 _245_
1.577430e-06 8.908963e-07 5.698647e-12 2.468332e-06 _225_
1.192753e-06 1.196046e-06 3.404380e-12 2.388802e-06 _217_
1.070890e-06 1.148787e-06 2.001060e-12 2.219680e-06 _239_
1.860680e-06 3.059532e-07 7.452133e-12 2.166641e-06 _240_
6.877265e-07 1.471420e-06 2.450668e-12 2.159149e-06 _250_
7.249339e-07 1.384284e-06 4.276940e-12 2.109222e-06 _292_
1.559624e-06 4.347756e-07 5.416957e-12 1.994405e-06 _271_
1.566068e-06 4.235781e-07 5.698647e-12 1.989652e-06 _231_
9.360663e-07 1.018675e-06 5.078299e-12 1.954747e-06 _261_
1.177223e-06 7.695323e-07 4.411803e-12 1.946760e-06 _228_
1.667257e-06 2.616300e-07 9.035351e-12 1.928897e-06 _248_
1.104274e-06 8.153719e-07 2.966153e-12 1.919649e-06 _222_
8.685189e-07 9.958463e-07 2.270400e-12 1.864368e-06 _241_
1.697337e-06 1.449252e-07 1.018131e-11 1.842273e-06 _263_
1.647210e-06 1.449252e-07 1.076519e-11 1.792146e-06 _254_
1.646812e-06 1.449252e-07 1.076519e-11 1.791748e-06 _265_
7.173275e-07 1.056175e-06 2.596694e-12 1.773505e-06 _255_
1.480049e-06 2.415420e-07 6.525446e-12 1.721598e-06 _242_
1.132414e-06 5.183481e-07 3.131889e-12 1.650765e-06 _353_
1.135302e-06 4.347756e-07 1.441647e-12 1.570079e-06 _367_
1.274763e-06 2.093364e-07 7.986655e-12 1.484107e-06 _244_
1.270435e-06 2.093364e-07 8.361258e-12 1.479780e-06 _249_
2.623943e-07 1.206926e-06 2.371280e-12 1.469322e-06 _210_
9.351695e-07 3.594650e-07 1.655038e-12 1.294636e-06 _355_
1.060558e-06 1.449252e-07 5.892946e-12 1.205489e-06 _257_
6.533979e-07 5.272128e-07 2.684960e-12 1.180613e-06 _266_
5.630015e-07 6.017457e-07 2.101489e-12 1.164749e-06 _243_
5.122903e-07 6.219827e-07 4.557094e-12 1.134278e-06 _234_
1.572182e-07 9.485165e-07 6.353528e-12 1.105741e-06 _253_
1.537095e-07 9.485165e-07 6.353528e-12 1.102232e-06 _264_
7.397982e-07 3.381588e-07 2.812458e-12 1.077960e-06 _361_
8.241297e-07 2.505362e-07 4.996429e-12 1.074671e-06 _368_
8.816385e-07 1.449252e-07 1.016040e-11 1.026574e-06 _270_
8.721318e-07 1.449252e-07 1.073051e-11 1.017068e-06 _268_
2.745498e-07 7.377351e-07 1.839050e-12 1.012287e-06 _251_
2.267884e-07 7.849288e-07 1.706868e-12 1.011719e-06 _232_
4.586502e-07 4.923374e-07 8.125919e-13 9.509884e-07 _247_
2.055700e-07 6.884870e-07 5.655024e-12 8.940626e-07 _212_
2.055700e-07 6.884870e-07 5.244557e-12 8.940622e-07 _213_
5.364109e-07 3.508401e-07 1.818403e-12 8.872528e-07 _277_
6.134395e-07 2.737476e-07 1.955411e-12 8.871890e-07 _358_
6.722454e-07 2.069647e-07 3.824422e-12 8.792139e-07 _362_
6.649948e-07 2.069647e-07 3.931458e-12 8.719634e-07 _359_
8.633024e-07 0.000000e+00 1.073051e-11 8.633132e-07 _238_
4.757352e-07 3.327351e-07 2.908365e-12 8.084732e-07 _276_
1.839310e-07 6.160146e-07 5.942352e-12 7.999516e-07 _211_
6.000330e-07 1.851789e-07 3.656396e-12 7.852157e-07 _365_
5.728432e-07 1.755626e-07 2.035057e-12 7.484078e-07 _274_
4.833313e-07 2.078201e-07 1.684531e-12 6.911530e-07 _363_
1.589625e-07 4.951044e-07 1.150177e-12 6.540680e-07 _220_
5.897523e-07 5.446440e-08 5.400226e-12 6.442221e-07 _374_
3.063470e-07 3.305966e-07 1.043144e-12 6.369446e-07 _275_
2.530373e-07 3.703320e-07 8.125919e-13 6.233701e-07 _207_
5.306096e-07 8.714304e-08 2.127508e-12 6.177547e-07 _290_
5.000113e-07 1.055009e-07 3.034489e-12 6.055152e-07 _317_
4.115600e-07 1.730678e-07 1.588284e-12 5.846294e-07 _308_
3.931079e-07 1.416009e-07 2.223049e-12 5.347111e-07 _301_
3.790264e-07 1.426507e-07 4.249674e-12 5.216814e-07 _260_
2.336348e-07 2.730672e-07 4.990044e-13 5.067025e-07 _288_
3.556187e-07 1.413677e-07 2.883360e-12 4.969892e-07 _285_
3.413644e-07 1.413677e-07 8.677521e-13 4.827330e-07 _387_
3.356861e-07 1.449252e-07 2.400389e-12 4.806137e-07 _364_
1.179662e-07 3.613896e-07 1.534656e-12 4.793573e-07 _221_
3.195766e-07 1.449252e-07 6.616856e-13 4.645025e-07 _370_
1.820004e-07 2.646562e-07 1.166732e-12 4.466578e-07 _258_
5.411039e-08 3.885408e-07 8.117832e-12 4.426593e-07 _208_
9.749566e-08 3.261254e-07 1.837672e-12 4.236229e-07 _209_
3.361738e-07 8.278847e-08 1.603470e-12 4.189639e-07 _283_
3.174691e-07 9.803591e-08 5.610673e-12 4.155106e-07 _371_
7.886361e-08 3.200601e-07 1.139876e-12 3.989249e-07 _205_
2.228132e-07 1.758477e-07 7.974258e-13 3.986617e-07 _375_
1.907858e-07 1.987805e-07 3.037800e-12 3.895693e-07 _199_
2.708281e-07 1.124928e-07 1.533157e-12 3.833225e-07 _273_
1.910814e-07 1.851465e-07 3.037800e-12 3.762310e-07 _204_
2.203665e-07 1.539000e-07 2.316877e-12 3.742688e-07 _291_
3.336356e-07 1.089288e-08 6.665864e-12 3.445352e-07 _333_
1.623180e-07 1.758477e-07 8.421723e-13 3.381666e-07 _360_
1.958190e-07 1.414843e-07 8.900415e-13 3.373042e-07 _382_
1.589318e-07 1.758477e-07 8.484010e-13 3.347804e-07 _357_
1.853423e-07 1.411927e-07 2.148732e-12 3.265372e-07 _315_
2.468645e-07 7.625015e-08 5.811750e-12 3.231205e-07 _377_
2.880149e-07 1.172232e-08 2.743326e-12 2.997399e-07 _340_
2.879265e-07 1.172232e-08 2.743326e-12 2.996516e-07 _326_
2.208990e-07 7.866720e-08 1.740508e-12 2.995679e-07 _304_
2.878035e-07 1.172232e-08 2.743326e-12 2.995286e-07 _329_
2.199579e-07 7.866720e-08 1.771855e-12 2.986269e-07 _311_
1.559443e-07 1.414843e-07 8.539973e-13 2.974295e-07 _350_
1.533617e-07 1.385100e-07 3.431816e-12 2.918752e-07 _307_
1.764331e-07 1.138342e-07 3.246024e-12 2.902705e-07 _302_
1.444046e-07 1.438754e-07 1.219716e-12 2.882812e-07 _369_
1.422189e-07 1.432922e-07 8.049465e-13 2.855119e-07 _372_
1.234460e-07 1.616047e-07 4.104700e-12 2.850548e-07 _203_
1.421931e-07 1.423591e-07 8.049465e-13 2.845530e-07 _407_
1.647064e-07 1.198217e-07 3.154478e-12 2.845312e-07 _309_
1.421689e-07 1.414843e-07 8.049465e-13 2.836540e-07 _378_
1.421689e-07 1.414843e-07 8.049465e-13 2.836540e-07 _390_
1.421689e-07 1.414843e-07 8.049465e-13 2.836540e-07 _394_
1.421689e-07 1.414843e-07 8.049465e-13 2.836540e-07 _398_
1.421689e-07 1.414843e-07 8.049465e-13 2.836540e-07 _402_
1.943990e-07 8.051400e-08 7.653893e-13 2.749138e-07 _376_
1.407337e-07 1.298592e-07 2.485149e-13 2.705932e-07 _282_
1.882026e-07 8.083799e-08 1.241435e-12 2.690418e-07 _373_
1.176577e-07 1.444586e-07 3.853187e-12 2.621202e-07 _392_
1.176404e-07 1.444586e-07 3.853187e-12 2.621030e-07 _400_
1.176321e-07 1.444586e-07 3.853187e-12 2.620946e-07 _404_
1.176319e-07 1.444586e-07 3.853187e-12 2.620944e-07 _396_
1.176319e-07 1.444586e-07 3.853187e-12 2.620944e-07 _380_
1.176305e-07 1.444586e-07 3.853187e-12 2.620930e-07 _388_
1.176293e-07 1.444586e-07 3.853187e-12 2.620918e-07 _384_
1.550422e-07 8.278847e-08 1.839291e-12 2.378326e-07 _289_
1.057800e-07 1.291334e-07 4.982441e-12 2.349184e-07 _279_
6.351908e-08 1.635487e-07 3.907500e-12 2.270717e-07 _235_
7.479790e-08 1.306433e-07 8.422000e-13 2.054420e-07 _200_
1.931591e-07 1.043928e-08 6.566885e-12 2.036049e-07 _332_
7.401371e-08 1.136268e-07 8.422000e-13 1.876413e-07 _226_
1.103174e-07 7.625015e-08 4.279968e-12 1.865718e-07 _305_
1.103174e-07 7.625015e-08 4.279968e-12 1.865718e-07 _312_
3.060729e-08 1.452103e-07 1.911265e-13 1.758178e-07 _202_
8.208271e-08 9.234000e-08 1.357520e-12 1.744241e-07 _303_
8.208271e-08 9.234000e-08 1.357520e-12 1.744241e-07 _310_
3.232512e-08 1.053907e-07 6.526570e-12 1.377224e-07 _262_
3.979160e-08 8.818632e-08 3.987000e-12 1.279819e-07 _229_
4.133439e-08 8.581463e-08 6.300000e-13 1.271496e-07 _227_
6.059145e-08 6.238944e-08 3.907500e-12 1.229848e-07 _198_
2.408767e-08 9.778320e-08 8.101200e-13 1.218717e-07 _206_
1.877041e-08 1.020924e-07 5.535000e-13 1.208633e-07 _256_
3.967894e-08 7.571879e-08 3.987000e-12 1.154017e-07 _230_
3.940256e-08 7.571879e-08 3.987000e-12 1.151253e-07 _224_
3.955968e-08 7.390440e-08 3.987000e-12 1.134681e-07 _223_
5.130727e-08 6.089903e-08 4.804000e-13 1.122068e-07 _201_
5.104085e-08 4.532760e-08 4.804000e-13 9.636894e-08 _197_
4.071503e-08 5.470416e-08 1.705091e-12 9.542089e-08 _237_
1.097978e-08 7.463663e-08 9.759703e-12 8.562617e-08 _269_
2.105405e-08 6.311519e-08 6.062680e-13 8.416985e-08 _278_
7.229788e-08 1.089288e-08 2.357368e-12 8.319311e-08 _316_
6.431625e-08 1.573344e-08 1.278221e-13 8.004982e-08 _338_
6.420361e-08 1.570752e-08 5.361819e-13 7.991166e-08 _403_
6.411896e-08 1.570752e-08 5.361819e-13 7.982701e-08 _399_
6.407829e-08 1.570752e-08 5.361819e-13 7.978635e-08 _379_
6.406297e-08 1.570752e-08 5.361819e-13 7.977103e-08 _391_
6.406246e-08 1.570752e-08 5.361819e-13 7.977052e-08 _395_
6.404663e-08 1.570752e-08 5.361819e-13 7.975468e-08 _383_
6.476678e-08 1.089288e-08 2.084584e-12 7.566174e-08 _410_
1.844561e-08 5.470416e-08 5.535000e-13 7.315032e-08 _267_
5.590383e-08 1.573344e-08 2.342279e-13 7.163751e-08 _335_
5.560702e-08 1.573344e-08 2.342279e-13 7.134069e-08 _347_
5.553510e-08 1.573344e-08 2.342279e-13 7.126878e-08 _344_
4.059262e-08 2.600424e-08 6.300000e-13 6.659749e-08 _233_
4.056650e-08 2.590056e-08 6.300000e-13 6.646770e-08 _236_
4.976696e-08 1.573344e-08 3.104538e-13 6.550071e-08 _324_
4.815918e-08 1.573344e-08 3.667948e-13 6.389298e-08 _321_
4.723286e-08 1.568808e-08 7.593133e-13 6.292169e-08 _409_
3.920275e-08 1.605096e-08 2.277111e-12 5.525598e-08 _354_
4.222064e-08 1.089288e-08 2.294177e-12 5.311582e-08 _385_
4.206052e-08 1.089288e-08 2.294177e-12 5.295569e-08 _393_
4.204125e-08 1.089288e-08 2.294177e-12 5.293642e-08 _401_
4.203052e-08 1.089288e-08 2.294177e-12 5.292570e-08 _381_
4.202984e-08 1.089288e-08 2.294177e-12 5.292501e-08 _397_
4.202954e-08 1.089288e-08 2.294177e-12 5.292471e-08 _405_
5.075752e-08 0.000000e+00 9.535920e-13 5.075848e-08 _334_
5.075752e-08 0.000000e+00 9.535920e-13 5.075848e-08 _343_
3.194727e-08 1.089288e-08 2.282673e-12 4.284244e-08 _389_
1.051638e-08 2.781216e-08 1.958000e-13 3.832873e-08 _408_
1.762977e-08 1.522800e-08 5.535000e-13 3.285832e-08 _272_
2.045907e-08 1.089288e-08 1.845012e-12 3.135379e-08 _319_
1.829713e-08 1.089288e-08 1.850255e-12 2.919186e-08 _331_
1.829660e-08 1.089288e-08 1.850255e-12 2.919133e-08 _342_
1.801879e-08 1.089288e-08 1.850255e-12 2.891352e-08 _328_
1.245894e-08 1.572048e-08 5.002208e-14 2.817946e-08 _386_
1.195368e-08 1.598616e-08 5.002208e-14 2.793989e-08 _366_
1.702990e-08 1.089288e-08 7.726073e-12 2.793051e-08 _325_
1.702989e-08 1.089288e-08 7.726073e-12 2.793050e-08 _336_
1.702988e-08 1.089288e-08 7.726073e-12 2.793049e-08 _322_
1.702988e-08 1.089288e-08 7.726073e-12 2.793049e-08 _345_
1.702988e-08 1.089288e-08 7.726073e-12 2.793049e-08 _348_
1.195568e-08 1.535760e-08 5.002208e-14 2.731333e-08 _406_
1.190535e-08 1.539000e-08 1.897652e-13 2.729553e-08 _337_
1.569015e-08 1.089288e-08 7.517376e-12 2.659054e-08 _339_
1.031630e-08 1.549368e-08 1.958000e-13 2.581017e-08 _313_
1.435570e-08 9.700559e-09 8.755231e-14 2.405634e-08 _259_
1.210861e-08 1.098360e-08 1.897652e-13 2.309240e-08 _318_
1.182871e-08 1.098360e-08 1.897652e-13 2.281250e-08 _330_
1.182565e-08 1.098360e-08 1.897652e-13 2.280944e-08 _341_
1.180448e-08 1.098360e-08 1.897652e-13 2.278827e-08 _327_
1.726436e-08 0.000000e+00 7.789877e-14 1.726444e-08 _320_
1.726436e-08 0.000000e+00 7.789877e-14 1.726444e-08 _323_
1.726436e-08 0.000000e+00 7.789877e-14 1.726444e-08 _346_
--- Test 6: manual activity override ---
Group Internal Switching Leakage Total
Power Power Power Power (Watts)

6
power/test/power_vcd_detailed.tcl
View File

@ -80,7 +80,11 @@ report_power -instances $some_cells
report_power -instances $some_cells -format json
report_power -instances $some_cells -digits 6
# Per instance power at 6 digits differs in the last digit between linux
# and macos, so exercise the option without comparing the values.
report_power -instances $some_cells -digits 6 \
> [make_result_file power_vcd_detailed_insts_digits6.txt]
assert_file_nonempty [make_result_file power_vcd_detailed_insts_digits6.txt]
#---------------------------------------------------------------
# Test 6: Override VCD with manual activity

2
search/Bfs.cc
View File

@ -163,7 +163,7 @@ BfsIterator::visitParallel(Level to_level,
else {
std::vector<VertexVisitor *> visitors;
visitors.reserve(thread_count_);
for (int k = 0; k < thread_count_; k++)
for (size_t k = 0; k < thread_count_; k++)
visitors.push_back(visitor->copy());
while (levelLessOrEqual(first_level_, last_level_)
&& levelLessOrEqual(first_level_, to_level)) {

9
search/ClkInfo.cc
View File

@ -118,6 +118,15 @@ ClkInfo::crprClkVertexId(const StaState *sta) const
return crpr_clk_path_.vertexId(sta);
}
const MinMax *
ClkInfo::crprClkMinMax(const StaState *sta) const
{
if (crpr_clk_path_.isNull())
return nullptr;
else
return crpr_clk_path_.tag(sta)->minMax();
}
Path *
ClkInfo::crprClkPath(const StaState *sta)
{

3
search/ClkInfo.hh
View File

@ -78,13 +78,14 @@ public:
// Null for clocks because the path cannot point to itself.
Path *crprClkPath(const StaState *sta);
const Path *crprClkPath(const StaState *sta) const;
const Path *crprClkPathRaw() const;
VertexId crprClkVertexId(const StaState *sta) const;
const MinMax *crprClkMinMax(const StaState *sta) const;
bool hasCrprClkPin() const { return !crpr_clk_path_.isNull(); }
// This clk_info/tag is used for a generated clock source path.
bool isGenClkSrcPath() const { return is_gen_clk_src_path_; }
size_t hash() const { return hash_; }
bool crprPathRefsFilter() const { return crpr_path_refs_filter_; }
const Path *crprClkPathRaw() const;
static int cmp(const ClkInfo *clk_info1,
const ClkInfo *clk_info2,

15
search/Search.cc
View File

@ -1396,13 +1396,15 @@ ArrivalVisitor::pruneCrprArrivals()
size_t path_index = path_itr->second;
const ClkInfo *clk_info = tag->clkInfo();
bool deleted_tag = false;
if (!tag->isClock() && clk_info->hasCrprClkPin()) {
const MinMax *min_max = tag->minMax();
if (!tag->isClock()
&& clk_info->hasCrprClkPin()) {
Path *path_no_crpr = tag_bldr_no_crpr_->tagMatchPath(tag);
if (path_no_crpr) {
if (path_no_crpr
&& path_no_crpr->tag(this) != tag) {
Arrival max_arrival = path_no_crpr->arrival();
const ClkInfo *clk_info_no_crpr = path_no_crpr->clkInfo(this);
Arrival max_crpr = crpr->maxCrpr(clk_info_no_crpr);
const MinMax *min_max = tag->minMax();
Arrival max_arrival_max_crpr = (min_max == MinMax::max())
? delayDiff(max_arrival, max_crpr, this)
: delaySum(max_arrival, max_crpr, this);
@ -1412,11 +1414,10 @@ ArrivalVisitor::pruneCrprArrivals()
delayAsString(max_crpr, this),
delayAsString(max_arrival_max_crpr, this));
Arrival arrival = tag_bldr_->arrival(path_index);
// Latch D->Q path uses enable min so crpr clk path min/max
// does not match the path min/max.
if (delayGreater(max_arrival_max_crpr, arrival, min_max, this)
&& clk_info_no_crpr->crprClkPath(this)->minMax(this)
== clk_info->crprClkPath(this)->minMax(this)) {
// Latch D->Q path uses enable min so crpr clk path min/max
// does not match the path min/max.
&& clk_info_no_crpr->crprClkMinMax(this) == clk_info->crprClkMinMax(this)) {
debugPrint(debug_, "search", 3, " pruned {}",
tag->to_string(this));
path_itr = path_index_map.erase(path_itr);

8
search/Sta.cc
View File

@ -2862,6 +2862,14 @@ Sta::reportPath(const Path *path)
report_path_->reportPath(path);
}
void
Sta::reportPathVerbose(const Path *path)
{
const StringSeq field_names = {"input_pins", "slew", "capacitance"};
setReportPathFields(field_names);
report_path_->reportPath(path);
}
void
Sta::updateTiming(bool full)
{

8
search/test/search_network_sta_deep.ok
View File

@ -221,7 +221,6 @@ Path Type: max
17 default vmin clk ^ clk_src clk crpr_pin null
18 default ^max clk ^ clk_src clk crpr_pin null
19 default vmax clk ^ clk_src clk crpr_pin null
Longest hash bucket length 1 hash=6
--- report_clk_infos ---
default/min clk ^ clk_src clk uncertain
default/max clk ^ clk_src clk uncertain
@ -229,25 +228,24 @@ default/min clk v clk_src clk uncertain
default/max clk v clk_src clk uncertain
4 clk infos
--- report_tag_groups ---
Group 0 hash = 2697898004198490802 ( 79)
Group 0 hash = <hash> (<bucket>)
0 0 default ^min clk ^ clk_src clk crpr_pin null input in2
1 2 default ^max clk ^ clk_src clk crpr_pin null input in2
2 1 default vmin clk ^ clk_src clk crpr_pin null input in2
3 3 default vmax clk ^ clk_src clk crpr_pin null input in2
Group 1 hash = 17966741373156438452 ( 88)
Group 1 hash = <hash> (<bucket>)
0 8 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
1 12 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
2 11 default vmin clk v (clock ideal) clk_src clk crpr_pin null
3 15 default vmax clk v (clock ideal) clk_src clk crpr_pin null
Group 2 hash = 17969506314027398258 ( 127)
Group 2 hash = <hash> (<bucket>)
0 16 default ^min clk ^ clk_src clk crpr_pin null
1 18 default ^max clk ^ clk_src clk crpr_pin null
2 17 default vmin clk ^ clk_src clk crpr_pin null
3 19 default vmax clk ^ clk_src clk crpr_pin null
Longest hash bucket length 1 hash=79
--- report_path_count_histogram ---
4 15
--- tag/group/path counts ---

6
search/test/search_network_sta_deep.tcl
View File

@ -74,13 +74,15 @@ report_checks -path_delay max
# Tag, group, info reporting
############################################################
puts "--- report_tags ---"
sta::report_tags
report_masked_hashes [make_result_file search_network_sta_deep_tags.txt] \
sta::report_tags
puts "--- report_clk_infos ---"
sta::report_clk_infos
puts "--- report_tag_groups ---"
sta::report_tag_groups
report_masked_hashes [make_result_file search_network_sta_deep_tag_groups.txt] \
sta::report_tag_groups
puts "--- report_path_count_histogram ---"
sta::report_path_count_histogram

14
search/test/search_report_path_detail.ok
View File

@ -201,37 +201,37 @@ Endpoint count: 3
Path group names: clk out_group reg_group asynchronous {path delay} {gated clock} unconstrained
--- find_requireds ---
--- report internal debug ---
Group 0 hash = 2697898004198490802 ( 79)
Group 0 hash = <hash> (<bucket>)
0 0 default ^min clk ^ clk_src clk crpr_pin null input in2
1 2 default ^max clk ^ clk_src clk crpr_pin null input in2
2 1 default vmin clk ^ clk_src clk crpr_pin null input in2
3 3 default vmax clk ^ clk_src clk crpr_pin null input in2
Group 1 hash = 1860950969858666218 ( 107)
Group 1 hash = <hash> (<bucket>)
0 4 default ^min clk ^ clk_src clk crpr_pin null input in1 Group -from {in1}
1 6 default ^max clk ^ clk_src clk crpr_pin null input in1 Group -from {in1}
2 5 default vmin clk ^ clk_src clk crpr_pin null input in1 Group -from {in1}
3 7 default vmax clk ^ clk_src clk crpr_pin null input in1 Group -from {in1}
Group 2 hash = 17966741373156438452 ( 88)
Group 2 hash = <hash> (<bucket>)
0 8 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
1 12 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
2 11 default vmin clk v (clock ideal) clk_src clk crpr_pin null
3 15 default vmax clk v (clock ideal) clk_src clk crpr_pin null
Group 3 hash = 17944144282683767210 ( 132)
Group 3 hash = <hash> (<bucket>)
0 16 default ^min clk ^ clk_src clk crpr_pin null Group -from {in1}
1 18 default ^max clk ^ clk_src clk crpr_pin null Group -from {in1}
2 17 default vmin clk ^ clk_src clk crpr_pin null Group -from {in1}
3 19 default vmax clk ^ clk_src clk crpr_pin null Group -from {in1}
Group 4 hash = 17969506314027398258 ( 127)
Group 4 hash = <hash> (<bucket>)
0 20 default ^min clk ^ clk_src clk crpr_pin null
1 22 default ^max clk ^ clk_src clk crpr_pin null
2 21 default vmin clk ^ clk_src clk crpr_pin null
3 23 default vmax clk ^ clk_src clk crpr_pin null
Group 5 hash = 17466906523001613852 ( 62)
Group 5 hash = <hash> (<bucket>)
0 20 default ^min clk ^ clk_src clk crpr_pin null
1 16 default ^min clk ^ clk_src clk crpr_pin null Group -from {in1}
2 22 default ^max clk ^ clk_src clk crpr_pin null
@ -241,7 +241,6 @@ Group 5 hash = 17466906523001613852 ( 62)
6 23 default vmax clk ^ clk_src clk crpr_pin null
7 19 default vmax clk ^ clk_src clk crpr_pin null Group -from {in1}
Longest hash bucket length 1 hash=62
0 default ^min clk ^ clk_src clk crpr_pin null input in2
1 default vmin clk ^ clk_src clk crpr_pin null input in2
2 default ^max clk ^ clk_src clk crpr_pin null input in2
@ -266,7 +265,6 @@ Longest hash bucket length 1 hash=62
21 default vmin clk ^ clk_src clk crpr_pin null
22 default ^max clk ^ clk_src clk crpr_pin null
23 default vmax clk ^ clk_src clk crpr_pin null
Longest hash bucket length 1 hash=6
default/min clk ^ clk_src clk uncertain
default/max clk ^ clk_src clk uncertain
default/min clk v clk_src clk uncertain

8
search/test/search_report_path_detail.tcl
View File

@ -1,5 +1,7 @@
# Test ReportPath.cc, PathEnum.cc, PathExpanded.cc, PathGroup.cc
# Exercises uncovered report path formats and path enumeration
source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog search_test1.v
link_design search_test1
@ -134,8 +136,10 @@ puts "--- find_requireds ---"
sta::find_requireds
puts "--- report internal debug ---"
sta::report_tag_groups
sta::report_tags
report_masked_hashes [make_result_file search_report_path_detail_tag_groups.txt] \
sta::report_tag_groups
report_masked_hashes [make_result_file search_report_path_detail_tags.txt] \
sta::report_tags
sta::report_clk_infos
sta::report_arrival_entries
sta::report_required_entries

8
search/test/search_search_arrival_required.ok
View File

@ -23,7 +23,6 @@ min violations: 0
17 default vmin clk ^ clk_src clk crpr_pin null
18 default ^max clk ^ clk_src clk crpr_pin null
19 default vmax clk ^ clk_src clk crpr_pin null
Longest hash bucket length 1 hash=6
--- report_clk_infos ---
default/min clk ^ clk_src clk uncertain
default/max clk ^ clk_src clk uncertain
@ -31,25 +30,24 @@ default/min clk v clk_src clk uncertain
default/max clk v clk_src clk uncertain
4 clk infos
--- report_tag_groups ---
Group 0 hash = 2697898004198490802 ( 79)
Group 0 hash = <hash> (<bucket>)
0 0 default ^min clk ^ clk_src clk crpr_pin null input in2
1 2 default ^max clk ^ clk_src clk crpr_pin null input in2
2 1 default vmin clk ^ clk_src clk crpr_pin null input in2
3 3 default vmax clk ^ clk_src clk crpr_pin null input in2
Group 1 hash = 17966741373156438452 ( 88)
Group 1 hash = <hash> (<bucket>)
0 8 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
1 12 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
2 11 default vmin clk v (clock ideal) clk_src clk crpr_pin null
3 15 default vmax clk v (clock ideal) clk_src clk crpr_pin null
Group 2 hash = 17969506314027398258 ( 127)
Group 2 hash = <hash> (<bucket>)
0 16 default ^min clk ^ clk_src clk crpr_pin null
1 18 default ^max clk ^ clk_src clk crpr_pin null
2 17 default vmin clk ^ clk_src clk crpr_pin null
3 19 default vmax clk ^ clk_src clk crpr_pin null
Longest hash bucket length 1 hash=79
--- report_path_count_histogram ---
4 15
--- report_arrival_entries ---

6
search/test/search_search_arrival_required.tcl
View File

@ -39,13 +39,15 @@ puts "min violations: [sta::endpoint_violation_count min]"
# report internal structures
############################################################
puts "--- report_tags ---"
sta::report_tags
report_masked_hashes [make_result_file search_search_arrival_required_tags.txt] \
sta::report_tags
puts "--- report_clk_infos ---"
sta::report_clk_infos
puts "--- report_tag_groups ---"
sta::report_tag_groups
report_masked_hashes [make_result_file search_search_arrival_required_tag_groups.txt] \
sta::report_tag_groups
puts "--- report_path_count_histogram ---"
sta::report_path_count_histogram

24
test/helpers.tcl
View File

@ -67,6 +67,30 @@ proc diff_files_sorted { file1 file2 } {
}
}
# Run cmd with its report output captured to file, then echo the output
# with hash values masked and hash bucket reports dropped.
# std::unordered_set bucket counts and std::hash<float> results are
# implementation defined, so report_tags/report_tag_groups hashes differ
# between libstdc++ (linux) and libc++ (macos).
proc report_masked_hashes { file cmd } {
sta::redirect_file_begin $file
set code [catch { uplevel 1 $cmd } result]
sta::redirect_file_end
if { $code } {
return -code $code $result
}
set stream [open $file r]
gets $stream line
while { ![eof $stream] } {
if { ![regexp {^Longest hash bucket} $line] } {
regsub {hash = \d+ \(\s*\d+\)} $line {hash = <hash> (<bucket>)} line
puts $line
}
gets $stream line
}
close $stream
}
proc assert_file_nonempty { path } {
if { ![file exists $path] || [file size $path] <= 0 } {
error "expected non-empty file: $path"