write_verilog fails for missing pins

This commit is contained in:
James Cherry 2019-06-27 18:04:57 -07:00
parent 5d7ad0a1ef
commit d108a15c56
1 changed files with 20 additions and 16 deletions

View File

@ -205,12 +205,14 @@ VerilogWriter::writeChild(Instance *child)
while (member_iter->hasNext()) { while (member_iter->hasNext()) {
Port *member = member_iter->next(); Port *member = member_iter->next();
Pin *pin = network_->findPin(child, member); Pin *pin = network_->findPin(child, member);
Net *net = network_->net(pin); const char *net_name = nullptr;
const char *net_name; if (pin) {
if (net) Net *net = network_->net(pin);
net_name = network_->name(net); if (net)
else net_name = network_->name(net);
// I can't see the verilog syntax to "skip" a bit in the concatentation. }
if (net_name == nullptr)
// There is no verilog syntax to "skip" a bit in the concatentation.
net_name = stringPrintTmp("_NC%d", unconnected_net_index_++); net_name = stringPrintTmp("_NC%d", unconnected_net_index_++);
const char *net_vname = netVerilogName(net_name, network_->pathEscape()); const char *net_vname = netVerilogName(net_name, network_->pathEscape());
if (!first_member) if (!first_member)
@ -223,16 +225,18 @@ VerilogWriter::writeChild(Instance *child)
} }
else { else {
Pin *pin = network_->findPin(child, port); Pin *pin = network_->findPin(child, port);
Net *net = network_->net(pin); if (pin) {
if (net) { Net *net = network_->net(pin);
const char *net_name = network_->name(net); if (net) {
const char *net_vname = netVerilogName(net_name, network_->pathEscape()); const char *net_name = network_->name(net);
if (!first_port) const char *net_vname = netVerilogName(net_name, network_->pathEscape());
fprintf(stream_, ",\n "); if (!first_port)
fprintf(stream_, ".%s(%s)", fprintf(stream_, ",\n ");
port_name, fprintf(stream_, ".%s(%s)",
net_vname); port_name,
first_port = false; net_vname);
first_port = false;
}
} }
} }
} }