set_data_check -from input port arrival
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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e0998d590c
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cdf590deb1
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@ -520,6 +520,7 @@ public:
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virtual void reportShort(ReportPath *report) const;
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virtual void reportFull(ReportPath *report) const;
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virtual bool isDataCheck() const { return true; }
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virtual ClockEdge *targetClkEdge(const StaState *sta) const;
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virtual TimingRole *checkRole(const StaState *sta) const;
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virtual ArcDelay margin(const StaState *sta) const;
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virtual int exceptPathCmp(const PathEnd *path_end,
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@ -1606,6 +1606,13 @@ PathEndDataCheck::typeName() const
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return "data_check";
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}
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ClockEdge *
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PathEndDataCheck::targetClkEdge(const StaState *sta) const
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{
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// clk_path_ can be null if data_clk_path is from an input port.
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return data_clk_path_.clkEdge(sta);
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}
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Arrival
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PathEndDataCheck::requiredTimeNoCrpr(const StaState *sta) const
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{
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@ -540,13 +540,14 @@ VisitPathEnds::visitDataCheckEnd1(DataCheck *check,
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while (tgt_clk_path_iter.hasNext()) {
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PathVertex *tgt_clk_path = tgt_clk_path_iter.next();
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const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this);
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const Clock *tgt_clk = tgt_clk_edge ? tgt_clk_edge->clock() : nullptr;
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ExceptionPath *exception = exceptionTo(path, pin, end_rf,
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tgt_clk_edge, min_max);
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// Ignore generated clock source paths.
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if (!tgt_clk_path->clkInfo(this)->isGenClkSrcPath()
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if (tgt_clk_edge
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&& !tgt_clk_path->clkInfo(this)->isGenClkSrcPath()
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&& !search_->pathPropagatedToClkSrc(from_pin, tgt_clk_path)) {
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found_from_path = true;
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const Clock *tgt_clk = tgt_clk_edge->clock();
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ExceptionPath *exception = exceptionTo(path, pin, end_rf,
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tgt_clk_edge, min_max);
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if (sdc_->sameClockGroup(src_clk, tgt_clk)
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&& !sdc_->clkStopPropagation(from_pin, tgt_clk)
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// False paths and path delays override.
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