set_data_check -from input port arrival

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2021-12-14 08:18:53 -07:00
parent e0998d590c
commit cdf590deb1
3 changed files with 13 additions and 4 deletions

View File

@ -520,6 +520,7 @@ public:
virtual void reportShort(ReportPath *report) const;
virtual void reportFull(ReportPath *report) const;
virtual bool isDataCheck() const { return true; }
virtual ClockEdge *targetClkEdge(const StaState *sta) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual ArcDelay margin(const StaState *sta) const;
virtual int exceptPathCmp(const PathEnd *path_end,

View File

@ -1606,6 +1606,13 @@ PathEndDataCheck::typeName() const
return "data_check";
}
ClockEdge *
PathEndDataCheck::targetClkEdge(const StaState *sta) const
{
// clk_path_ can be null if data_clk_path is from an input port.
return data_clk_path_.clkEdge(sta);
}
Arrival
PathEndDataCheck::requiredTimeNoCrpr(const StaState *sta) const
{

View File

@ -540,13 +540,14 @@ VisitPathEnds::visitDataCheckEnd1(DataCheck *check,
while (tgt_clk_path_iter.hasNext()) {
PathVertex *tgt_clk_path = tgt_clk_path_iter.next();
const ClockEdge *tgt_clk_edge = tgt_clk_path->clkEdge(this);
const Clock *tgt_clk = tgt_clk_edge ? tgt_clk_edge->clock() : nullptr;
ExceptionPath *exception = exceptionTo(path, pin, end_rf,
tgt_clk_edge, min_max);
// Ignore generated clock source paths.
if (!tgt_clk_path->clkInfo(this)->isGenClkSrcPath()
if (tgt_clk_edge
&& !tgt_clk_path->clkInfo(this)->isGenClkSrcPath()
&& !search_->pathPropagatedToClkSrc(from_pin, tgt_clk_path)) {
found_from_path = true;
const Clock *tgt_clk = tgt_clk_edge->clock();
ExceptionPath *exception = exceptionTo(path, pin, end_rf,
tgt_clk_edge, min_max);
if (sdc_->sameClockGroup(src_clk, tgt_clk)
&& !sdc_->clkStopPropagation(from_pin, tgt_clk)
// False paths and path delays override.