Merge pull request #302 from The-OpenROAD-Project-staging/sta_follow_up_write_verilog

Sta follow up write verilog

test/helpers.tcl

@@ -0,0 +1,41 @@
+# Helper functions common to multiple regressions.
+
+set test_dir [file dirname [file normalize [info script]]]
+set result_dir [file join $test_dir "results"]
+
+# puts [exec cat $file] without forking.
+proc report_file { file } {
+  set stream [open $file r]
+  if { [file extension $file] == ".gz" } {
+    zlib push gunzip $stream
+  }
+  gets $stream line
+  while { ![eof $stream] } {
+    puts $line
+    gets $stream line
+  }
+  close $stream
+}
+
+proc report_file_filter { file filter } {
+  set stream [open $file r]
+  gets $stream line
+  while { ![eof $stream] } {
+    set index [string first $filter $line]
+    if { $index != -1 } {
+      set line [string replace $line $index [expr $index + [string length $filter] - 1]]
+    }
+    puts $line
+    gets $stream line
+  }
+  close $stream
+}
+
+proc make_result_file { filename } {
+  variable result_dir
+  return [file join $result_dir $filename]
+}
+
+proc sort_objects { objects } {
+  return [sta::sort_by_full_name $objects]
+}

test/verilog_write_escape.tcl

@@ -1,14 +1,10 @@
 # Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
+source helpers.tcl
 read_liberty gf180mcu_sram.lib.gz
 read_liberty asap7_small.lib.gz
 read_verilog verilog_write_escape.v
 link_design multi_sink
-set output_file "verilog_write_escape_out.v"
-write_verilog $output_file
-set fp [open $output_file r]
-while {[gets $fp line] >= 0} {
-    puts $line
-}
-close $fp
-read_verilog $output_file
-file delete $output_file
+set verilog_file [make_result_file "verilog_write_escape.v"]
+write_verilog $verilog_file
+report_file $verilog_file
+read_verilog $verilog_file

test/verilog_write_escape.v

@@ -1,10 +1,10 @@
-module \multi_sink (clk);
+module multi_sink (clk);
  input clk;
  wire \alu_adder_result_ex[0] ;
  \hier_block \h1\x (.childclk(clk),  .\Y[2:1] ({ \alu_adder_result_ex[0] , \alu_adder_result_ex[0]  }) );
 endmodule // multi_sink
 
-module \hier_block (childclk, \Y[2:1] );
+module hier_block (childclk, \Y[2:1] );
    input childclk; 
    output [1:0] \Y[2:1] ;
    wire [1:0] \Y[2:1] ;

verilog/VerilogWriter.cc

@@ -389,7 +389,7 @@ VerilogWriter::writeInstBusPin(const Instance *inst,
   if (!first_port)
     fprintf(stream_, ",\n    ");
 
-  string port_vname = portVerilogName(network_->name(port)); 
+  std::string port_vname = portVerilogName(network_->name(port));
   fprintf(stream_, ".%s({", port_vname.c_str());
   first_port = false;
   bool first_member = true;