replaceEquivCellBefore non-liberty port
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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@ -4080,30 +4080,32 @@ Sta::replaceEquivCellBefore(Instance *inst,
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while (pin_iter->hasNext()) {
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Pin *pin = pin_iter->next();
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LibertyPort *port = network_->libertyPort(pin);
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if (port->direction()->isAnyInput()) {
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Vertex *vertex = graph_->pinLoadVertex(pin);
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replaceCellPinInvalidate(port, vertex, to_cell);
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if (port) {
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if (port->direction()->isAnyInput()) {
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Vertex *vertex = graph_->pinLoadVertex(pin);
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replaceCellPinInvalidate(port, vertex, to_cell);
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// Replace the timing arc sets in the graph edges.
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VertexOutEdgeIterator edge_iter(vertex, graph_);
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while (edge_iter.hasNext()) {
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Edge *edge = edge_iter.next();
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Vertex *to_vertex = edge->to(graph_);
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if (network_->instance(to_vertex->pin()) == inst) {
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TimingArcSet *from_set = edge->timingArcSet();
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// Find corresponding timing arc set.
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TimingArcSet *to_set = to_cell->findTimingArcSet(from_set);
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if (to_set)
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edge->setTimingArcSet(to_set);
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else
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report_->critical(264, "corresponding timing arc set not found in equiv cells");
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}
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}
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}
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else {
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// Force delay calculation on output pins.
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Vertex *vertex = graph_->pinDrvrVertex(pin);
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graph_delay_calc_->delayInvalid(vertex);
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// Replace the timing arc sets in the graph edges.
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VertexOutEdgeIterator edge_iter(vertex, graph_);
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while (edge_iter.hasNext()) {
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Edge *edge = edge_iter.next();
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Vertex *to_vertex = edge->to(graph_);
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if (network_->instance(to_vertex->pin()) == inst) {
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TimingArcSet *from_set = edge->timingArcSet();
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// Find corresponding timing arc set.
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TimingArcSet *to_set = to_cell->findTimingArcSet(from_set);
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if (to_set)
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edge->setTimingArcSet(to_set);
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else
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report_->critical(264, "corresponding timing arc set not found in equiv cells");
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}
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}
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}
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else {
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// Force delay calculation on output pins.
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Vertex *vertex = graph_->pinDrvrVertex(pin);
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graph_delay_calc_->delayInvalid(vertex);
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}
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}
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}
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delete pin_iter;
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