SearchPred0 not thru timing checks
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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@ -673,7 +673,6 @@ protected:
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// Eval across latch D->Q edges.
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// Eval across latch D->Q edges.
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// SearchPred0 unless
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// SearchPred0 unless
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// timing check edge
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// disabled loop
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// disabled loop
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// disabled converging clock edge (Xilinx)
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// disabled converging clock edge (Xilinx)
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// clk source pin
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// clk source pin
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@ -34,10 +34,12 @@ namespace sta {
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// Class hierarchy:
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// Class hierarchy:
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// SearchPred
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// SearchPred
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// SearchAdj (unless loop disabled, latch D->Q, timing check, dynamic loop)
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// SearchAdj (unless loop disabled, latch D->Q, timing check, dynamic loop)
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// SearchPred0 (unless disabled or constant)
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// SearchPred0 (unless timing check, disabled or constant)
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// EvalPred (unless timing check)
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// EvalPred (unless dynamic loop breaking)
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// SearchThru (unless latch D->Q)
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// SearchThru (unless latch D->Q)
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// GenClkInsertionSearchPred
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// SearchPred1 (unless loop disabled)
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// SearchPred1 (unless loop disabled)
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// FanOutSrchPred
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// ClkTreeSearchPred (only wire or combinational)
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// ClkTreeSearchPred (only wire or combinational)
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// Virtual base class for search predicates.
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// Virtual base class for search predicates.
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@ -96,7 +96,6 @@ EvalPred::searchThru(Edge *edge,
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return SearchPred0::searchThru(edge, mode)
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return SearchPred0::searchThru(edge, mode)
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&& (sta_->variables()->dynamicLoopBreaking()
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&& (sta_->variables()->dynamicLoopBreaking()
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|| !edge->isDisabledLoop())
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|| !edge->isDisabledLoop())
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&& !role->isTimingCheck()
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&& (search_thru_latches_
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&& (search_thru_latches_
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|| role->isLatchDtoQ()
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|| role->isLatchDtoQ()
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|| sta_->latches()->latchDtoQState(edge, mode) == LatchEnableState::open);
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|| sta_->latches()->latchDtoQState(edge, mode) == LatchEnableState::open);
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@ -116,7 +116,8 @@ SearchPred0::searchThru(Edge *edge,
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const Variables *variables = sta_->variables();
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const Variables *variables = sta_->variables();
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const Sdc *sdc = mode->sdc();
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const Sdc *sdc = mode->sdc();
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const Sim *sim = mode->sim();
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const Sim *sim = mode->sim();
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return !(sdc->isDisabledConstraint(edge)
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return !(role->isTimingCheck()
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|| sdc->isDisabledConstraint(edge)
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// Constants disable edge cond expression.
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// Constants disable edge cond expression.
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|| sim->isDisabledCond(edge)
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|| sim->isDisabledCond(edge)
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|| sdc->isDisabledCondDefault(edge)
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|| sdc->isDisabledCondDefault(edge)
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