SearchPred0 not thru timing checks

Signed-off-by: James Cherry <cherry@parallaxsw.com>

include/sta/Search.hh

@@ -673,7 +673,6 @@ protected:
 
 // Eval across latch D->Q edges.
 // SearchPred0 unless
-//  timing check edge
 //  disabled loop
 //  disabled converging clock edge (Xilinx)
 //  clk source pin

include/sta/SearchPred.hh

@@ -34,10 +34,12 @@ namespace sta {
 // Class hierarchy:
 // SearchPred
 //  SearchAdj (unless loop disabled, latch D->Q, timing check, dynamic loop)
-//  SearchPred0 (unless disabled or constant)
-//   EvalPred (unless timing check)
+//  SearchPred0 (unless timing check, disabled or constant)
+//   EvalPred (unless dynamic loop breaking)
 //    SearchThru (unless latch D->Q)
+//   GenClkInsertionSearchPred
 //   SearchPred1 (unless loop disabled)
+//    FanOutSrchPred
 //  ClkTreeSearchPred (only wire or combinational)
 
 // Virtual base class for search predicates.

search/Search.cc

@@ -96,7 +96,6 @@ EvalPred::searchThru(Edge *edge,
   return SearchPred0::searchThru(edge, mode)
     && (sta_->variables()->dynamicLoopBreaking()
         || !edge->isDisabledLoop())
-    && !role->isTimingCheck()
     && (search_thru_latches_
         || role->isLatchDtoQ()
         || sta_->latches()->latchDtoQState(edge, mode) == LatchEnableState::open);

search/SearchPred.cc

@@ -116,7 +116,8 @@ SearchPred0::searchThru(Edge *edge,
   const Variables *variables = sta_->variables();
   const Sdc *sdc = mode->sdc();
   const Sim *sim = mode->sim();
-  return !(sdc->isDisabledConstraint(edge)
+  return !(role->isTimingCheck()
+           || sdc->isDisabledConstraint(edge)
            // Constants disable edge cond expression.
            || sim->isDisabledCond(edge)
            || sdc->isDisabledCondDefault(edge)