move sdc/liberty code out of StaTcl.i
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry
parent
0e0a0624fe
commit
bd42dc5596
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@ -27,6 +27,83 @@ using namespace sta;
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%}
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////////////////////////////////////////////////////////////////
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//
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// Empty class definitions to make swig happy.
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// Private constructor/destructor so swig doesn't emit them.
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//
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////////////////////////////////////////////////////////////////
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class LibertyLibrary
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{
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private:
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LibertyLibrary();
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~LibertyLibrary();
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};
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class LibertyLibraryIterator
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{
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private:
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LibertyLibraryIterator();
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~LibertyLibraryIterator();
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};
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class LibertyCell
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{
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private:
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LibertyCell();
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~LibertyCell();
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};
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class LibertyPort
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{
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private:
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LibertyPort();
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~LibertyPort();
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};
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class LibertyCellPortIterator
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{
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private:
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LibertyCellPortIterator();
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~LibertyCellPortIterator();
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};
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class LibertyPortMemberIterator
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{
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private:
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LibertyPortMemberIterator();
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~LibertyPortMemberIterator();
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};
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class TimingArcSet
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{
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private:
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TimingArcSet();
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~TimingArcSet();
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};
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class TimingArc
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{
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private:
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TimingArc();
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~TimingArc();
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};
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class Wireload
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{
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private:
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Wireload();
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~Wireload();
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};
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class WireloadSelection
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{
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private:
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WireloadSelection();
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~WireloadSelection();
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};
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%inline %{
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bool
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@ -103,3 +180,333 @@ liberty_supply_exists(const char *supply_name)
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}
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%} // inline
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%extend LibertyLibrary {
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const char *name() { return self->name(); }
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LibertyCell *
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find_liberty_cell(const char *name)
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{
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return self->findLibertyCell(name);
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}
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LibertyCellSeq
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find_liberty_cells_matching(const char *pattern,
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bool regexp,
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bool nocase)
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{
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PatternMatch matcher(pattern, regexp, nocase, Sta::sta()->tclInterp());
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return self->findLibertyCellsMatching(&matcher);
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}
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Wireload *
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find_wireload(const char *model_name)
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{
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return self->findWireload(model_name);
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}
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WireloadSelection *
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find_wireload_selection(const char *selection_name)
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{
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return self->findWireloadSelection(selection_name);
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}
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OperatingConditions *
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find_operating_conditions(const char *op_cond_name)
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{
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return self->findOperatingConditions(op_cond_name);
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}
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OperatingConditions *
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default_operating_conditions()
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{
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return self->defaultOperatingConditions();
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}
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} // LibertyLibrary methods
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%extend LibertyCell {
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const char *name() { return self->name(); }
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bool is_leaf() { return self->isLeaf(); }
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bool is_buffer() { return self->isBuffer(); }
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bool is_inverter() { return self->isInverter(); }
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LibertyLibrary *liberty_library() { return self->libertyLibrary(); }
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Cell *cell() { return reinterpret_cast<Cell*>(self); }
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LibertyPort *
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find_liberty_port(const char *name)
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{
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return self->findLibertyPort(name);
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}
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LibertyPortSeq
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find_liberty_ports_matching(const char *pattern,
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bool regexp,
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bool nocase)
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{
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PatternMatch matcher(pattern, regexp, nocase, Sta::sta()->tclInterp());
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return self->findLibertyPortsMatching(&matcher);
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}
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LibertyCellPortIterator *
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liberty_port_iterator() { return new LibertyCellPortIterator(self); }
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const TimingArcSetSeq &
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timing_arc_sets()
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{
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return self->timingArcSets();
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}
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void
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ensure_voltage_waveforms()
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{
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Corner *corner = Sta::sta()->cmdCorner();
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DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max());
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self->ensureVoltageWaveforms(dcalc_ap);
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}
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} // LibertyCell methods
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%extend LibertyPort {
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const char *bus_name() { return self->busName(); }
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Cell *cell() { return self->cell(); }
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bool is_bus() { return self->isBus(); }
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LibertyPortMemberIterator *
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member_iterator() { return new LibertyPortMemberIterator(self); }
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const char *
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function()
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{
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FuncExpr *func = self->function();
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if (func)
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return func->asString();
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else
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return nullptr;
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}
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const char *
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tristate_enable()
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{
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FuncExpr *enable = self->tristateEnable();
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if (enable)
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return enable->asString();
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else
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return nullptr;
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}
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float
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capacitance(Corner *corner,
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const MinMax *min_max)
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{
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Sta *sta = Sta::sta();
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return sta->capacitance(self, corner, min_max);
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}
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void
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set_direction(const char *dir)
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{
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self->setDirection(PortDirection::find(dir));
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}
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} // LibertyPort methods
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%extend TimingArcSet {
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LibertyPort *from() { return self->from(); }
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LibertyPort *to() { return self->to(); }
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TimingRole *role() { return self->role(); }
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const char *sdf_cond() { return self->sdfCond(); }
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const char *
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full_name()
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{
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const char *from = self->from()->name();
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const char *to = self->to()->name();
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const char *cell_name = self->libertyCell()->name();
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return stringPrintTmp("%s %s -> %s",
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cell_name,
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from,
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to);
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}
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TimingArcSeq &
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timing_arcs() { return self->arcs(); }
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} // TimingArcSet methods
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%extend TimingArc {
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LibertyPort *from() { return self->from(); }
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LibertyPort *to() { return self->to(); }
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Transition *from_edge() { return self->fromEdge(); }
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const char *from_edge_name() { return self->fromEdge()->asRiseFall()->name(); }
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Transition *to_edge() { return self->toEdge(); }
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const char *to_edge_name() { return self->toEdge()->asRiseFall()->name(); }
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TimingRole *role() { return self->role(); }
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float
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time_voltage(float in_slew,
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float load_cap,
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float time)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms)
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return waveforms->timeVoltage(in_slew, load_cap, time);
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}
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return 0.0;
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}
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float
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time_current(float in_slew,
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float load_cap,
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float time)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms)
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return waveforms->timeCurrent(in_slew, load_cap, time);
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}
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return 0.0;
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}
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float
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voltage_current(float in_slew,
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float load_cap,
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float voltage)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms)
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return waveforms->voltageCurrent(in_slew, load_cap, voltage);
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}
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return 0.0;
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}
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float
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voltage_time(float in_slew,
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float load_cap,
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float voltage)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms)
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return waveforms->voltageTime(in_slew, load_cap, voltage);
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}
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return 0.0;
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}
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Table1
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voltage_waveform(float in_slew,
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float load_cap)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms) {
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Table1 waveform = waveforms->voltageWaveform(in_slew, load_cap);
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return waveform;
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}
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}
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return Table1();
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}
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const Table1 *
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voltage_waveform_raw(float in_slew,
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float load_cap)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms) {
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const Table1 *waveform = waveforms->voltageWaveformRaw(in_slew, load_cap);
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return waveform;
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}
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}
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return nullptr;
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}
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Table1
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current_waveform(float in_slew,
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float load_cap)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms) {
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Table1 waveform = waveforms->currentWaveform(in_slew, load_cap);
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return waveform;
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}
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}
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return Table1();
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}
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const Table1 *
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current_waveform_raw(float in_slew,
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float load_cap)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms) {
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const Table1 *waveform = waveforms->currentWaveformRaw(in_slew, load_cap);
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return waveform;
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}
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}
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return nullptr;
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}
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Table1
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voltage_current_waveform(float in_slew,
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float load_cap)
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms) {
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Table1 waveform = waveforms->voltageCurrentWaveform(in_slew, load_cap);
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return waveform;
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}
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}
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return Table1();
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}
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float
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final_resistance()
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{
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GateTableModel *gate_model = self->gateTableModel();
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if (gate_model) {
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OutputWaveforms *waveforms = gate_model->outputWaveforms();
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if (waveforms) {
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return waveforms->finalResistance();
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}
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}
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return 0.0;
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}
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} // TimingArc methods
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%extend OperatingConditions {
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float process() { return self->process(); }
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float voltage() { return self->voltage(); }
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float temperature() { return self->temperature(); }
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}
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%extend LibertyLibraryIterator {
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bool has_next() { return self->hasNext(); }
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LibertyLibrary *next() { return self->next(); }
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void finish() { delete self; }
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} // LibertyLibraryIterator methods
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%extend LibertyCellPortIterator {
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bool has_next() { return self->hasNext(); }
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LibertyPort *next() { return self->next(); }
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void finish() { delete self; }
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} // LibertyCellPortIterator methods
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%extend LibertyPortMemberIterator {
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bool has_next() { return self->hasNext(); }
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LibertyPort *next() { return self->next(); }
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void finish() { delete self; }
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} // LibertyPortMemberIterator methods
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206
sdc/Sdc.i
206
sdc/Sdc.i
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@ -19,14 +19,77 @@
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include "Sdc.hh"
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#include "Clock.hh"
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#include "PortDelay.hh"
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#include "Sta.hh"
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using namespace sta;
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%}
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////////////////////////////////////////////////////////////////
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//
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// Empty class definitions to make swig happy.
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// Private constructor/destructor so swig doesn't emit them.
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//
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////////////////////////////////////////////////////////////////
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class Clock
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{
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private:
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Clock();
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~Clock();
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};
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class ClockEdge
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{
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private:
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ClockEdge();
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~ClockEdge();
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};
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class ExceptionFrom
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{
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private:
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ExceptionFrom();
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~ExceptionFrom();
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};
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class ExceptionThru
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{
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private:
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ExceptionThru();
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~ExceptionThru();
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};
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class ExceptionTo
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{
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private:
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ExceptionTo();
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~ExceptionTo();
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};
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class OperatingConditions
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{
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private:
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OperatingConditions();
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~OperatingConditions();
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};
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%inline %{
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void
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write_sdc_cmd(const char *filename,
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bool leaf,
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bool compatible,
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int digits,
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bool gzip,
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bool no_timestamp)
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{
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cmdLinkedNetwork();
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Sta::sta()->writeSdc(filename, leaf, compatible, digits, gzip, no_timestamp);
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}
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void
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set_analysis_type_cmd(const char *analysis_type)
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{
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|
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@ -627,6 +690,21 @@ unset_disable_clock_gating_check_pin(Pin *pin)
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Sta::sta()->removeDisableClockGatingCheck(pin);
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}
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EdgeSeq
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disabled_edges_sorted()
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{
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cmdLinkedNetwork();
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return Sta::sta()->disabledEdgesSorted();
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}
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bool
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timing_arc_disabled(Edge *edge,
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TimingArc *arc)
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{
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Graph *graph = Sta::sta()->graph();
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return !searchThru(edge, arc, graph);
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}
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void
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make_false_path(ExceptionFrom *from,
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ExceptionThruSeq *thrus,
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|
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@ -767,6 +845,72 @@ check_exception_to_pins(ExceptionTo *to,
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Sta::sta()->checkExceptionToPins(to, file, line);
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}
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ClockGroups *
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make_clock_groups(const char *name,
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bool logically_exclusive,
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bool physically_exclusive,
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bool asynchronous,
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bool allow_paths,
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const char *comment)
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{
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return Sta::sta()->makeClockGroups(name, logically_exclusive,
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physically_exclusive, asynchronous,
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allow_paths, comment);
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}
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void
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clock_groups_make_group(ClockGroups *clk_groups,
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ClockSet *clks)
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{
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Sta::sta()->makeClockGroup(clk_groups, clks);
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}
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void
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unset_clock_groups_logically_exclusive(const char *name)
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{
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Sta::sta()->removeClockGroupsLogicallyExclusive(name);
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}
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void
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unset_clock_groups_physically_exclusive(const char *name)
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{
|
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Sta::sta()->removeClockGroupsPhysicallyExclusive(name);
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}
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void
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unset_clock_groups_asynchronous(const char *name)
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{
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Sta::sta()->removeClockGroupsAsynchronous(name);
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}
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|
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// Debugging function.
|
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bool
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same_clk_group(Clock *clk1,
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Clock *clk2)
|
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{
|
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Sta *sta = Sta::sta();
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Sdc *sdc = sta->sdc();
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return sdc->sameClockGroupExplicit(clk1, clk2);
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}
|
||||
|
||||
void
|
||||
set_clock_sense_cmd(PinSet *pins,
|
||||
ClockSet *clks,
|
||||
bool positive,
|
||||
bool negative,
|
||||
bool stop_propagation)
|
||||
{
|
||||
Sta *sta = Sta::sta();
|
||||
if (positive)
|
||||
sta->setClockSense(pins, clks, ClockSense::positive);
|
||||
else if (negative)
|
||||
sta->setClockSense(pins, clks, ClockSense::negative);
|
||||
else if (stop_propagation)
|
||||
sta->setClockSense(pins, clks, ClockSense::stop);
|
||||
else
|
||||
sta->report()->critical(1577, "unknown clock sense");
|
||||
}
|
||||
|
||||
void
|
||||
set_input_slew_cmd(Port *port,
|
||||
const RiseFallBoth *rf,
|
||||
|
|
@ -1073,4 +1217,66 @@ is_genclk_src(const Pin *pin)
|
|||
return search->isGenClkSrc(vertex);
|
||||
}
|
||||
|
||||
bool
|
||||
pin_is_constrained(Pin *pin)
|
||||
{
|
||||
return Sta::sta()->sdc()->isConstrained(pin);
|
||||
}
|
||||
|
||||
bool
|
||||
instance_is_constrained(Instance *inst)
|
||||
{
|
||||
return Sta::sta()->sdc()->isConstrained(inst);
|
||||
}
|
||||
|
||||
bool
|
||||
net_is_constrained(Net *net)
|
||||
{
|
||||
return Sta::sta()->sdc()->isConstrained(net);
|
||||
}
|
||||
|
||||
bool
|
||||
clk_thru_tristate_enabled()
|
||||
{
|
||||
return Sta::sta()->clkThruTristateEnabled();
|
||||
}
|
||||
|
||||
void
|
||||
set_clk_thru_tristate_enabled(bool enabled)
|
||||
{
|
||||
Sta::sta()->setClkThruTristateEnabled(enabled);
|
||||
}
|
||||
|
||||
void
|
||||
remove_constraints()
|
||||
{
|
||||
Sta::sta()->removeConstraints();
|
||||
}
|
||||
|
||||
%} // inline
|
||||
|
||||
%extend Clock {
|
||||
float period() { return self->period(); }
|
||||
FloatSeq *waveform() { return self->waveform(); }
|
||||
float time(RiseFall *rf) { return self->edge(rf)->time(); }
|
||||
bool is_generated() { return self->isGenerated(); }
|
||||
bool waveform_valid() { return self->waveformValid(); }
|
||||
bool is_virtual() { return self->isVirtual(); }
|
||||
bool is_propagated() { return self->isPropagated(); }
|
||||
const PinSet &sources() { return self->pins(); }
|
||||
|
||||
float
|
||||
slew(const RiseFall *rf,
|
||||
const MinMax *min_max)
|
||||
{
|
||||
return self->slew(rf, min_max);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
%extend ClockEdge {
|
||||
Clock *clock() { return self->clock(); }
|
||||
RiseFall *transition() { return self->transition(); }
|
||||
float time() { return self->time(); }
|
||||
}
|
||||
|
||||
|
|
|
|||
598
tcl/StaTcl.i
598
tcl/StaTcl.i
|
|
@ -52,8 +52,6 @@
|
|||
#include "Wireload.hh"
|
||||
#include "PortDirection.hh"
|
||||
#include "Network.hh"
|
||||
#include "Clock.hh"
|
||||
#include "PortDelay.hh"
|
||||
#include "ExceptionPath.hh"
|
||||
#include "Sdc.hh"
|
||||
#include "Graph.hh"
|
||||
|
|
@ -172,13 +170,6 @@ private:
|
|||
~CellPortIterator();
|
||||
};
|
||||
|
||||
class LibertyCellPortIterator
|
||||
{
|
||||
private:
|
||||
LibertyCellPortIterator();
|
||||
~LibertyCellPortIterator();
|
||||
};
|
||||
|
||||
class Port
|
||||
{
|
||||
private:
|
||||
|
|
@ -193,69 +184,6 @@ private:
|
|||
~PortMemberIterator();
|
||||
};
|
||||
|
||||
class LibertyLibrary
|
||||
{
|
||||
private:
|
||||
LibertyLibrary();
|
||||
~LibertyLibrary();
|
||||
};
|
||||
|
||||
class LibertyLibraryIterator
|
||||
{
|
||||
private:
|
||||
LibertyLibraryIterator();
|
||||
~LibertyLibraryIterator();
|
||||
};
|
||||
|
||||
class LibertyCell
|
||||
{
|
||||
private:
|
||||
LibertyCell();
|
||||
~LibertyCell();
|
||||
};
|
||||
|
||||
class LibertyPort
|
||||
{
|
||||
private:
|
||||
LibertyPort();
|
||||
~LibertyPort();
|
||||
};
|
||||
|
||||
class LibertyPortMemberIterator
|
||||
{
|
||||
private:
|
||||
LibertyPortMemberIterator();
|
||||
~LibertyPortMemberIterator();
|
||||
};
|
||||
|
||||
class TimingArcSet
|
||||
{
|
||||
private:
|
||||
TimingArcSet();
|
||||
~TimingArcSet();
|
||||
};
|
||||
|
||||
class TimingArc
|
||||
{
|
||||
private:
|
||||
TimingArc();
|
||||
~TimingArc();
|
||||
};
|
||||
|
||||
class Wireload
|
||||
{
|
||||
private:
|
||||
Wireload();
|
||||
~Wireload();
|
||||
};
|
||||
|
||||
class WireloadSelection
|
||||
{
|
||||
private:
|
||||
WireloadSelection();
|
||||
~WireloadSelection();
|
||||
};
|
||||
|
||||
class Transition
|
||||
{
|
||||
private:
|
||||
|
|
@ -347,20 +275,6 @@ private:
|
|||
~PinConnectedPinIterator();
|
||||
};
|
||||
|
||||
class Clock
|
||||
{
|
||||
private:
|
||||
Clock();
|
||||
~Clock();
|
||||
};
|
||||
|
||||
class ClockEdge
|
||||
{
|
||||
private:
|
||||
ClockEdge();
|
||||
~ClockEdge();
|
||||
};
|
||||
|
||||
class Vertex
|
||||
{
|
||||
private:
|
||||
|
|
@ -438,34 +352,6 @@ private:
|
|||
~VertexPathIterator();
|
||||
};
|
||||
|
||||
class ExceptionFrom
|
||||
{
|
||||
private:
|
||||
ExceptionFrom();
|
||||
~ExceptionFrom();
|
||||
};
|
||||
|
||||
class ExceptionThru
|
||||
{
|
||||
private:
|
||||
ExceptionThru();
|
||||
~ExceptionThru();
|
||||
};
|
||||
|
||||
class ExceptionTo
|
||||
{
|
||||
private:
|
||||
ExceptionTo();
|
||||
~ExceptionTo();
|
||||
};
|
||||
|
||||
class OperatingConditions
|
||||
{
|
||||
private:
|
||||
OperatingConditions();
|
||||
~OperatingConditions();
|
||||
};
|
||||
|
||||
class Corner
|
||||
{
|
||||
private:
|
||||
|
|
@ -657,36 +543,6 @@ fall_short_name()
|
|||
return RiseFall::fall()->shortName();
|
||||
}
|
||||
|
||||
bool
|
||||
pin_is_constrained(Pin *pin)
|
||||
{
|
||||
return Sta::sta()->sdc()->isConstrained(pin);
|
||||
}
|
||||
|
||||
bool
|
||||
instance_is_constrained(Instance *inst)
|
||||
{
|
||||
return Sta::sta()->sdc()->isConstrained(inst);
|
||||
}
|
||||
|
||||
bool
|
||||
net_is_constrained(Net *net)
|
||||
{
|
||||
return Sta::sta()->sdc()->isConstrained(net);
|
||||
}
|
||||
|
||||
bool
|
||||
clk_thru_tristate_enabled()
|
||||
{
|
||||
return Sta::sta()->clkThruTristateEnabled();
|
||||
}
|
||||
|
||||
void
|
||||
set_clk_thru_tristate_enabled(bool enabled)
|
||||
{
|
||||
Sta::sta()->setClkThruTristateEnabled(enabled);
|
||||
}
|
||||
|
||||
bool
|
||||
network_is_linked()
|
||||
{
|
||||
|
|
@ -1918,12 +1774,6 @@ delete_path_ref(PathRef *path)
|
|||
delete path;
|
||||
}
|
||||
|
||||
void
|
||||
remove_constraints()
|
||||
{
|
||||
Sta::sta()->removeConstraints();
|
||||
}
|
||||
|
||||
void
|
||||
report_path_cmd(PathRef *path)
|
||||
{
|
||||
|
|
@ -2421,25 +2271,6 @@ report_capacitance_limit_verbose(Pin *pin,
|
|||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
EdgeSeq
|
||||
disabled_edges_sorted()
|
||||
{
|
||||
cmdLinkedNetwork();
|
||||
return Sta::sta()->disabledEdgesSorted();
|
||||
}
|
||||
|
||||
void
|
||||
write_sdc_cmd(const char *filename,
|
||||
bool leaf,
|
||||
bool compatible,
|
||||
int digits,
|
||||
bool gzip,
|
||||
bool no_timestamp)
|
||||
{
|
||||
cmdLinkedNetwork();
|
||||
Sta::sta()->writeSdc(filename, leaf, compatible, digits, gzip, no_timestamp);
|
||||
}
|
||||
|
||||
void
|
||||
write_timing_model_cmd(const char *lib_name,
|
||||
const char *cell_name,
|
||||
|
|
@ -2502,80 +2333,6 @@ slow_drivers(int count)
|
|||
return Sta::sta()->slowDrivers(count);
|
||||
}
|
||||
|
||||
bool
|
||||
timing_arc_disabled(Edge *edge,
|
||||
TimingArc *arc)
|
||||
{
|
||||
Graph *graph = Sta::sta()->graph();
|
||||
return !searchThru(edge, arc, graph);
|
||||
}
|
||||
|
||||
ClockGroups *
|
||||
make_clock_groups(const char *name,
|
||||
bool logically_exclusive,
|
||||
bool physically_exclusive,
|
||||
bool asynchronous,
|
||||
bool allow_paths,
|
||||
const char *comment)
|
||||
{
|
||||
return Sta::sta()->makeClockGroups(name, logically_exclusive,
|
||||
physically_exclusive, asynchronous,
|
||||
allow_paths, comment);
|
||||
}
|
||||
|
||||
void
|
||||
clock_groups_make_group(ClockGroups *clk_groups,
|
||||
ClockSet *clks)
|
||||
{
|
||||
Sta::sta()->makeClockGroup(clk_groups, clks);
|
||||
}
|
||||
|
||||
void
|
||||
unset_clock_groups_logically_exclusive(const char *name)
|
||||
{
|
||||
Sta::sta()->removeClockGroupsLogicallyExclusive(name);
|
||||
}
|
||||
|
||||
void
|
||||
unset_clock_groups_physically_exclusive(const char *name)
|
||||
{
|
||||
Sta::sta()->removeClockGroupsPhysicallyExclusive(name);
|
||||
}
|
||||
|
||||
void
|
||||
unset_clock_groups_asynchronous(const char *name)
|
||||
{
|
||||
Sta::sta()->removeClockGroupsAsynchronous(name);
|
||||
}
|
||||
|
||||
// Debugging function.
|
||||
bool
|
||||
same_clk_group(Clock *clk1,
|
||||
Clock *clk2)
|
||||
{
|
||||
Sta *sta = Sta::sta();
|
||||
Sdc *sdc = sta->sdc();
|
||||
return sdc->sameClockGroupExplicit(clk1, clk2);
|
||||
}
|
||||
|
||||
void
|
||||
set_clock_sense_cmd(PinSet *pins,
|
||||
ClockSet *clks,
|
||||
bool positive,
|
||||
bool negative,
|
||||
bool stop_propagation)
|
||||
{
|
||||
Sta *sta = Sta::sta();
|
||||
if (positive)
|
||||
sta->setClockSense(pins, clks, ClockSense::positive);
|
||||
else if (negative)
|
||||
sta->setClockSense(pins, clks, ClockSense::negative);
|
||||
else if (stop_propagation)
|
||||
sta->setClockSense(pins, clks, ClockSense::stop);
|
||||
else
|
||||
sta->report()->critical(1577, "unknown clock sense");
|
||||
}
|
||||
|
||||
bool
|
||||
timing_role_is_check(TimingRole *role)
|
||||
{
|
||||
|
|
@ -3003,62 +2760,12 @@ find_cells_matching(const char *pattern,
|
|||
|
||||
} // Library methods
|
||||
|
||||
%extend LibertyLibrary {
|
||||
const char *name() { return self->name(); }
|
||||
|
||||
LibertyCell *
|
||||
find_liberty_cell(const char *name)
|
||||
{
|
||||
return self->findLibertyCell(name);
|
||||
}
|
||||
|
||||
LibertyCellSeq
|
||||
find_liberty_cells_matching(const char *pattern,
|
||||
bool regexp,
|
||||
bool nocase)
|
||||
{
|
||||
PatternMatch matcher(pattern, regexp, nocase, Sta::sta()->tclInterp());
|
||||
return self->findLibertyCellsMatching(&matcher);
|
||||
}
|
||||
|
||||
Wireload *
|
||||
find_wireload(const char *model_name)
|
||||
{
|
||||
return self->findWireload(model_name);
|
||||
}
|
||||
|
||||
WireloadSelection *
|
||||
find_wireload_selection(const char *selection_name)
|
||||
{
|
||||
return self->findWireloadSelection(selection_name);
|
||||
}
|
||||
|
||||
OperatingConditions *
|
||||
find_operating_conditions(const char *op_cond_name)
|
||||
{
|
||||
return self->findOperatingConditions(op_cond_name);
|
||||
}
|
||||
|
||||
OperatingConditions *
|
||||
default_operating_conditions()
|
||||
{
|
||||
return self->defaultOperatingConditions();
|
||||
}
|
||||
|
||||
} // LibertyLibrary methods
|
||||
|
||||
%extend LibraryIterator {
|
||||
bool has_next() { return self->hasNext(); }
|
||||
Library *next() { return self->next(); }
|
||||
void finish() { delete self; }
|
||||
} // LibraryIterator methods
|
||||
|
||||
%extend LibertyLibraryIterator {
|
||||
bool has_next() { return self->hasNext(); }
|
||||
LibertyLibrary *next() { return self->next(); }
|
||||
void finish() { delete self; }
|
||||
} // LibertyLibraryIterator methods
|
||||
|
||||
%extend Cell {
|
||||
const char *name() { return cmdNetwork()->name(self); }
|
||||
Library *library() { return cmdNetwork()->library(self); }
|
||||
|
|
@ -3085,59 +2792,12 @@ find_ports_matching(const char *pattern,
|
|||
|
||||
} // Cell methods
|
||||
|
||||
%extend LibertyCell {
|
||||
const char *name() { return self->name(); }
|
||||
bool is_leaf() { return self->isLeaf(); }
|
||||
bool is_buffer() { return self->isBuffer(); }
|
||||
bool is_inverter() { return self->isInverter(); }
|
||||
LibertyLibrary *liberty_library() { return self->libertyLibrary(); }
|
||||
Cell *cell() { return reinterpret_cast<Cell*>(self); }
|
||||
LibertyPort *
|
||||
find_liberty_port(const char *name)
|
||||
{
|
||||
return self->findLibertyPort(name);
|
||||
}
|
||||
|
||||
LibertyPortSeq
|
||||
find_liberty_ports_matching(const char *pattern,
|
||||
bool regexp,
|
||||
bool nocase)
|
||||
{
|
||||
PatternMatch matcher(pattern, regexp, nocase, Sta::sta()->tclInterp());
|
||||
return self->findLibertyPortsMatching(&matcher);
|
||||
}
|
||||
|
||||
LibertyCellPortIterator *
|
||||
liberty_port_iterator() { return new LibertyCellPortIterator(self); }
|
||||
|
||||
const TimingArcSetSeq &
|
||||
timing_arc_sets()
|
||||
{
|
||||
return self->timingArcSets();
|
||||
}
|
||||
|
||||
void
|
||||
ensure_voltage_waveforms()
|
||||
{
|
||||
Corner *corner = Sta::sta()->cmdCorner();
|
||||
DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max());
|
||||
self->ensureVoltageWaveforms(dcalc_ap);
|
||||
}
|
||||
|
||||
} // LibertyCell methods
|
||||
|
||||
%extend CellPortIterator {
|
||||
bool has_next() { return self->hasNext(); }
|
||||
Port *next() { return self->next(); }
|
||||
void finish() { delete self; }
|
||||
} // CellPortIterator methods
|
||||
|
||||
%extend LibertyCellPortIterator {
|
||||
bool has_next() { return self->hasNext(); }
|
||||
LibertyPort *next() { return self->next(); }
|
||||
void finish() { delete self; }
|
||||
} // LibertyCellPortIterator methods
|
||||
|
||||
%extend Port {
|
||||
const char *bus_name() { return cmdNetwork()->busName(self); }
|
||||
Cell *cell() { return cmdNetwork()->cell(self); }
|
||||
|
|
@ -3148,245 +2808,12 @@ member_iterator() { return cmdNetwork()->memberIterator(self); }
|
|||
|
||||
} // Port methods
|
||||
|
||||
%extend LibertyPort {
|
||||
const char *bus_name() { return self->busName(); }
|
||||
Cell *cell() { return self->cell(); }
|
||||
bool is_bus() { return self->isBus(); }
|
||||
LibertyPortMemberIterator *
|
||||
member_iterator() { return new LibertyPortMemberIterator(self); }
|
||||
|
||||
const char *
|
||||
function()
|
||||
{
|
||||
FuncExpr *func = self->function();
|
||||
if (func)
|
||||
return func->asString();
|
||||
else
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
const char *
|
||||
tristate_enable()
|
||||
{
|
||||
FuncExpr *enable = self->tristateEnable();
|
||||
if (enable)
|
||||
return enable->asString();
|
||||
else
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
float
|
||||
capacitance(Corner *corner,
|
||||
const MinMax *min_max)
|
||||
{
|
||||
Sta *sta = Sta::sta();
|
||||
return sta->capacitance(self, corner, min_max);
|
||||
}
|
||||
|
||||
void
|
||||
set_direction(const char *dir)
|
||||
{
|
||||
self->setDirection(PortDirection::find(dir));
|
||||
}
|
||||
|
||||
} // LibertyPort methods
|
||||
|
||||
%extend OperatingConditions {
|
||||
float process() { return self->process(); }
|
||||
float voltage() { return self->voltage(); }
|
||||
float temperature() { return self->temperature(); }
|
||||
}
|
||||
|
||||
%extend PortMemberIterator {
|
||||
bool has_next() { return self->hasNext(); }
|
||||
Port *next() { return self->next(); }
|
||||
void finish() { delete self; }
|
||||
} // PortMemberIterator methods
|
||||
|
||||
%extend LibertyPortMemberIterator {
|
||||
bool has_next() { return self->hasNext(); }
|
||||
LibertyPort *next() { return self->next(); }
|
||||
void finish() { delete self; }
|
||||
} // LibertyPortMemberIterator methods
|
||||
|
||||
%extend TimingArcSet {
|
||||
LibertyPort *from() { return self->from(); }
|
||||
LibertyPort *to() { return self->to(); }
|
||||
TimingRole *role() { return self->role(); }
|
||||
const char *sdf_cond() { return self->sdfCond(); }
|
||||
|
||||
const char *
|
||||
full_name()
|
||||
{
|
||||
const char *from = self->from()->name();
|
||||
const char *to = self->to()->name();
|
||||
const char *cell_name = self->libertyCell()->name();
|
||||
return stringPrintTmp("%s %s -> %s",
|
||||
cell_name,
|
||||
from,
|
||||
to);
|
||||
}
|
||||
|
||||
TimingArcSeq &
|
||||
timing_arcs() { return self->arcs(); }
|
||||
|
||||
} // TimingArcSet methods
|
||||
|
||||
%extend TimingArc {
|
||||
LibertyPort *from() { return self->from(); }
|
||||
LibertyPort *to() { return self->to(); }
|
||||
Transition *from_edge() { return self->fromEdge(); }
|
||||
const char *from_edge_name() { return self->fromEdge()->asRiseFall()->name(); }
|
||||
Transition *to_edge() { return self->toEdge(); }
|
||||
const char *to_edge_name() { return self->toEdge()->asRiseFall()->name(); }
|
||||
TimingRole *role() { return self->role(); }
|
||||
|
||||
float
|
||||
time_voltage(float in_slew,
|
||||
float load_cap,
|
||||
float time)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms)
|
||||
return waveforms->timeVoltage(in_slew, load_cap, time);
|
||||
}
|
||||
return 0.0;
|
||||
}
|
||||
|
||||
float
|
||||
time_current(float in_slew,
|
||||
float load_cap,
|
||||
float time)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms)
|
||||
return waveforms->timeCurrent(in_slew, load_cap, time);
|
||||
}
|
||||
return 0.0;
|
||||
}
|
||||
|
||||
float
|
||||
voltage_current(float in_slew,
|
||||
float load_cap,
|
||||
float voltage)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms)
|
||||
return waveforms->voltageCurrent(in_slew, load_cap, voltage);
|
||||
}
|
||||
return 0.0;
|
||||
}
|
||||
|
||||
float
|
||||
voltage_time(float in_slew,
|
||||
float load_cap,
|
||||
float voltage)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms)
|
||||
return waveforms->voltageTime(in_slew, load_cap, voltage);
|
||||
}
|
||||
return 0.0;
|
||||
}
|
||||
|
||||
Table1
|
||||
voltage_waveform(float in_slew,
|
||||
float load_cap)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms) {
|
||||
Table1 waveform = waveforms->voltageWaveform(in_slew, load_cap);
|
||||
return waveform;
|
||||
}
|
||||
}
|
||||
return Table1();
|
||||
}
|
||||
|
||||
const Table1 *
|
||||
voltage_waveform_raw(float in_slew,
|
||||
float load_cap)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms) {
|
||||
const Table1 *waveform = waveforms->voltageWaveformRaw(in_slew, load_cap);
|
||||
return waveform;
|
||||
}
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
Table1
|
||||
current_waveform(float in_slew,
|
||||
float load_cap)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms) {
|
||||
Table1 waveform = waveforms->currentWaveform(in_slew, load_cap);
|
||||
return waveform;
|
||||
}
|
||||
}
|
||||
return Table1();
|
||||
}
|
||||
|
||||
const Table1 *
|
||||
current_waveform_raw(float in_slew,
|
||||
float load_cap)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms) {
|
||||
const Table1 *waveform = waveforms->currentWaveformRaw(in_slew, load_cap);
|
||||
return waveform;
|
||||
}
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
Table1
|
||||
voltage_current_waveform(float in_slew,
|
||||
float load_cap)
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms) {
|
||||
Table1 waveform = waveforms->voltageCurrentWaveform(in_slew, load_cap);
|
||||
return waveform;
|
||||
}
|
||||
}
|
||||
return Table1();
|
||||
}
|
||||
|
||||
float
|
||||
final_resistance()
|
||||
{
|
||||
GateTableModel *gate_model = self->gateTableModel();
|
||||
if (gate_model) {
|
||||
OutputWaveforms *waveforms = gate_model->outputWaveforms();
|
||||
if (waveforms) {
|
||||
return waveforms->finalResistance();
|
||||
}
|
||||
}
|
||||
return 0.0;
|
||||
}
|
||||
|
||||
} // TimingArc methods
|
||||
|
||||
%extend Instance {
|
||||
Instance *parent() { return cmdLinkedNetwork()->parent(self); }
|
||||
Cell *cell() { return cmdLinkedNetwork()->cell(self); }
|
||||
|
|
@ -3550,31 +2977,6 @@ const Pin *next() { return self->next(); }
|
|||
void finish() { delete self; }
|
||||
} // NetConnectedPinIterator methods
|
||||
|
||||
%extend Clock {
|
||||
float period() { return self->period(); }
|
||||
FloatSeq *waveform() { return self->waveform(); }
|
||||
float time(RiseFall *rf) { return self->edge(rf)->time(); }
|
||||
bool is_generated() { return self->isGenerated(); }
|
||||
bool waveform_valid() { return self->waveformValid(); }
|
||||
bool is_virtual() { return self->isVirtual(); }
|
||||
bool is_propagated() { return self->isPropagated(); }
|
||||
const PinSet &sources() { return self->pins(); }
|
||||
|
||||
float
|
||||
slew(const RiseFall *rf,
|
||||
const MinMax *min_max)
|
||||
{
|
||||
return self->slew(rf, min_max);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
%extend ClockEdge {
|
||||
Clock *clock() { return self->clock(); }
|
||||
RiseFall *transition() { return self->transition(); }
|
||||
float time() { return self->time(); }
|
||||
}
|
||||
|
||||
%extend Vertex {
|
||||
Pin *pin() { return self->pin(); }
|
||||
bool is_bidirect_driver() { return self->isBidirectDriver(); }
|
||||
|
|
|
|||
Loading…
Reference in New Issue