crpr for clk paths
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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bbffa9b493
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@ -238,25 +238,26 @@ public:
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const RiseFall *to_rf,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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virtual Tag *thruTag(Tag *from_tag,
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Edge *edge,
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const RiseFall *to_rf,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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virtual Tag *thruClkTag(PathVertex *from_path,
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Tag *from_tag,
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bool to_propagates_clk,
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Edge *edge,
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const RiseFall *to_rf,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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Tag *thruTag(Tag *from_tag,
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Edge *edge,
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const RiseFall *to_rf,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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Tag *thruClkTag(PathVertex *from_path,
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Tag *from_tag,
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bool to_propagates_clk,
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Edge *edge,
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const RiseFall *to_rf,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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ClkInfo *thruClkInfo(PathVertex *from_path,
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ClkInfo *from_tag_clk,
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Edge *edge,
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Vertex *to_vertex,
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const Pin *to_pin,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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ClkInfo *from_clk_info,
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bool from_is_clk,
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Edge *edge,
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const Pin *to_pin,
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bool to_is_clk,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap);
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ClkInfo *clkInfoWithCrprClkPath(ClkInfo *from_clk_info,
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PathVertex *from_path,
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const PathAnalysisPt *path_ap);
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@ -54,8 +54,8 @@ public:
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const Arrival &insertion() const { return insertion_; }
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ClockUncertainties *uncertainties() const { return uncertainties_; }
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PathAPIndex pathAPIndex() const { return path_ap_index_; }
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// Clock path for the last driver in the clock network used for
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// crpr resolution.
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// Clock path used for crpr resolution.
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// Null for clocks because the path cannot point to itself.
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PathVertexRep &crprClkPath() { return crpr_clk_path_; }
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const PathVertexRep &crprClkPath() const { return crpr_clk_path_; }
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VertexId crprClkVertexId() const;
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@ -152,13 +152,22 @@ CheckCrpr::checkCrpr1(const Path *src_path,
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{
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crpr = 0.0;
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crpr_pin = nullptr;
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ClkInfo *src_clk_info = src_path->tag(this)->clkInfo();
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const Tag *src_tag = src_path->tag(this);
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ClkInfo *src_clk_info = src_tag->clkInfo();
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ClkInfo *tgt_clk_info = tgt_clk_path->tag(this)->clkInfo();
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const Clock *src_clk = src_clk_info->clock();
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const Clock *tgt_clk = tgt_clk_info->clock();
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const PathVertex src_clk_path1(src_clk_info->crprClkPath(), this);
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const PathVertex *src_clk_path =
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src_clk_path1.isNull() ? nullptr : &src_clk_path1;
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PathVertex src_clk_path1;
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PathVertexRep &src_crpr_clk_path = src_clk_info->crprClkPath();
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const PathVertex *src_clk_path = nullptr;
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if (src_tag->isClock()) {
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src_clk_path1.init(src_path->vertex(this), src_path->tag(this), this);
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src_clk_path = &src_clk_path1;
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}
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else if (!src_crpr_clk_path.isNull()) {
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src_clk_path1.init(src_crpr_clk_path, this);
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src_clk_path = &src_clk_path1;
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}
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const MinMax *src_clk_min_max =
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src_clk_path ? src_clk_path->minMax(this) : src_path->minMax(this);
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if (src_clk && tgt_clk
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@ -2417,8 +2417,9 @@ Search::thruClkTag(PathVertex *from_path,
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&& to_propagates_clk
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&& (role->isWire()
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|| role == TimingRole::combinational()));
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ClkInfo *to_clk_info = thruClkInfo(from_path, from_clk_info,
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edge, to_vertex, to_pin, min_max, path_ap);
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ClkInfo *to_clk_info = thruClkInfo(from_path, from_clk_info, from_is_clk,
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edge, to_pin, to_is_clk,
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min_max, path_ap);
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Tag *to_tag = mutateTag(from_tag,from_pin,from_rf,from_is_clk,from_clk_info,
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to_pin, to_rf, to_is_clk, to_is_reg_clk, false,
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to_clk_info, nullptr, min_max, path_ap);
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@ -2429,9 +2430,10 @@ Search::thruClkTag(PathVertex *from_path,
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ClkInfo *
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Search::thruClkInfo(PathVertex *from_path,
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ClkInfo *from_clk_info,
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bool from_is_clk,
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Edge *edge,
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Vertex *to_vertex,
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const Pin *to_pin,
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bool to_is_clk,
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const MinMax *min_max,
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const PathAnalysisPt *path_ap)
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{
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@ -2462,7 +2464,7 @@ Search::thruClkInfo(PathVertex *from_path,
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PathVertex *to_crpr_clk_path = nullptr;
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if (sdc_->crprActive()
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&& to_vertex->isRegClk()) {
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&& from_is_clk && !to_is_clk) {
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to_crpr_clk_path = from_path;
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changed = true;
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}
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