liberty support for write_liberty
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry
parent
4b0e6e8e0d
commit
b292796116
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@ -49,6 +49,7 @@ class StaState;
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typedef Set<Library*> LibrarySet;
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typedef Map<const char*, TableTemplate*, CharPtrLess> TableTemplateMap;
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typedef Map<const char*, BusDcl *, CharPtrLess> BusDclMap;
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typedef Vector<BusDcl *> BusDclSeq;
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typedef Map<const char*, ScaleFactors*, CharPtrLess> ScaleFactorsMap;
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typedef Map<const char*, Wireload*, CharPtrLess> WireloadMap;
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typedef Map<const char*, WireloadSelection*, CharPtrLess> WireloadSelectionMap;
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@ -129,6 +130,7 @@ public:
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void setDelayModelType(DelayModelType type);
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void addBusDcl(BusDcl *bus_dcl);
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BusDcl *findBusDcl(const char *name) const;
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BusDclSeq busDcls() const;
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void addTableTemplate(TableTemplate *tbl_template,
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TableTemplateType type);
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TableTemplate *findTableTemplate(const char *name,
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@ -642,6 +644,8 @@ public:
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LibertyLibrary *libertyLibrary() const { return liberty_cell_->libertyLibrary(); }
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LibertyPort *findLibertyMember(int index) const;
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LibertyPort *findLibertyBusBit(int index) const;
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BusDcl *busDcl() const { return bus_dcl_; }
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void setDirection(PortDirection *dir);
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void fanoutLoad(// Return values.
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float &fanout_load,
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bool &exists) const;
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@ -762,24 +766,25 @@ protected:
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LibertyPort(LibertyCell *cell,
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const char *name,
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bool is_bus,
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int from_index,
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BusDcl *bus_dcl,
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int from_index,
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int to_index,
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bool is_bundle,
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ConcretePortSeq *members);
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virtual ~LibertyPort();
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void setDirection(PortDirection *dir);
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void setMinPort(LibertyPort *min);
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void addScaledPort(OperatingConditions *op_cond,
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LibertyPort *scaled_port);
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LibertyCell *liberty_cell_;
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BusDcl *bus_dcl_;
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FuncExpr *function_;
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FuncExpr *tristate_enable_;
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ScaledPortMap *scaled_ports_;
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RiseFallMinMax capacitance_;
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MinMaxFloatValues slew_limit_; // inputs and outputs
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MinMaxFloatValues slew_limit_; // inputs and outputs
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MinMaxFloatValues cap_limit_; // outputs
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float fanout_load_; // inputs
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float fanout_load_; // inputs
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bool fanout_load_exists_;
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MinMaxFloatValues fanout_limit_; // outputs
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float min_period_;
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@ -172,9 +172,9 @@ public:
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int index) const = 0;
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virtual int fromIndex(const Port *port) const = 0;
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virtual int toIndex(const Port *port) const = 0;
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// Predicate to determine if subscript is within bus range.
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// (toIndex > fromIndex) && fromIndex <= subscript <= toIndex
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// || (fromIndex > toIndex) && fromIndex >= subscript >= toIndex
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// Predicate to determine if index is within bus range.
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// (toIndex > fromIndex) && fromIndex <= index <= toIndex
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// || (fromIndex > toIndex) && fromIndex >= index >= toIndex
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bool busIndexInRange(const Port *port,
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int index);
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// Find Bundle/bus member by index.
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@ -178,6 +178,15 @@ LibertyLibrary::findBusDcl(const char *name) const
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return bus_dcls_.findKey(name);
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}
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BusDclSeq
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LibertyLibrary::busDcls() const
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{
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BusDclSeq dcls;
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for (auto name_dcl : bus_dcls_)
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dcls.push_back(name_dcl.second);
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return dcls;
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}
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void
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LibertyLibrary::addTableTemplate(TableTemplate *tbl_template,
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TableTemplateType type)
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@ -1844,12 +1853,14 @@ LibertyCellPortBitIterator::next()
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LibertyPort::LibertyPort(LibertyCell *cell,
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const char *name,
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bool is_bus,
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int from_index,
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BusDcl *bus_dcl,
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int from_index,
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int to_index,
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bool is_bundle,
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ConcretePortSeq *members) :
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ConcretePort(cell, name, is_bus, from_index, to_index, is_bundle, members),
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liberty_cell_(cell),
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bus_dcl_(bus_dcl),
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function_(nullptr),
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tristate_enable_(nullptr),
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scaled_ports_(nullptr),
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@ -41,7 +41,7 @@ LibertyPort *
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LibertyBuilder::makePort(LibertyCell *cell,
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const char *name)
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{
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LibertyPort *port = new LibertyPort(cell, name, false, -1, -1, false, nullptr);
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LibertyPort *port = new LibertyPort(cell, name, false, nullptr, -1, -1, false, nullptr);
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cell->addPort(port);
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return port;
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}
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@ -49,10 +49,12 @@ LibertyBuilder::makePort(LibertyCell *cell,
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LibertyPort *
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LibertyBuilder::makeBusPort(LibertyCell *cell,
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const char *name,
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int from_index,
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int to_index)
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int from_index,
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int to_index,
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BusDcl *bus_dcl)
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{
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LibertyPort *port = new LibertyPort(cell, name, true, from_index, to_index,
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LibertyPort *port = new LibertyPort(cell, name, true, bus_dcl,
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from_index, to_index,
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false, new ConcretePortSeq);
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cell->addPort(port);
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makeBusPortBits(cell->library(), cell, port, name, from_index, to_index);
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@ -99,7 +101,7 @@ LibertyBuilder::makePort(LibertyCell *cell,
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const char *bit_name,
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int bit_index)
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{
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LibertyPort *port = new LibertyPort(cell, bit_name, false,
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LibertyPort *port = new LibertyPort(cell, bit_name, false, nullptr,
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bit_index, bit_index, false, nullptr);
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return port;
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}
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@ -109,7 +111,7 @@ LibertyBuilder::makeBundlePort(LibertyCell *cell,
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const char *name,
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ConcretePortSeq *members)
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{
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LibertyPort *port = new LibertyPort(cell, name, false, -1, -1, true, members);
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LibertyPort *port = new LibertyPort(cell, name, false, nullptr, -1, -1, true, members);
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cell->addPort(port);
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return port;
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}
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@ -40,7 +40,8 @@ public:
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virtual LibertyPort *makeBusPort(LibertyCell *cell,
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const char *name,
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int from_index,
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int to_index);
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int to_index,
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BusDcl *bus_dcl);
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virtual LibertyPort *makeBundlePort(LibertyCell *cell,
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const char *name,
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ConcretePortSeq *members);
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@ -2726,9 +2726,8 @@ LibertyReader::visitBusType(LibertyAttr *attr)
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while (name_iter.hasNext()) {
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const char *name = name_iter.next();
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debugPrint(debug_, "liberty", 1, " bus %s", name);
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LibertyPort *port = builder_->makeBusPort(cell_, name,
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bus_dcl->from(),
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bus_dcl->to());
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LibertyPort *port = builder_->makeBusPort(cell_, name, bus_dcl->from(),
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bus_dcl->to(), bus_dcl);
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ports_->push_back(port);
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}
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}
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@ -3360,14 +3359,14 @@ LibertyReader::beginSequential(LibertyGroup *group,
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LibertyPort *out_port_inv = nullptr;
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if (out_name) {
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if (has_size)
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out_port = builder_->makeBusPort(cell_, out_name, size - 1, 0);
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out_port = builder_->makeBusPort(cell_, out_name, size - 1, 0, nullptr);
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else
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out_port = builder_->makePort(cell_,out_name);
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out_port->setDirection(PortDirection::internal());
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}
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if (out_inv_name) {
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if (has_size)
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out_port_inv = builder_->makeBusPort(cell_, out_inv_name, size - 1, 0);
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out_port_inv = builder_->makeBusPort(cell_, out_inv_name, size - 1, 0, nullptr);
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else
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out_port_inv = builder_->makePort(cell_, out_inv_name);
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out_port_inv->setDirection(PortDirection::internal());
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126
messages.txt
126
messages.txt
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@ -1,9 +1,9 @@
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0001 DmpCeff.cc:1595 cell %s delay model not supported on SPF parasitics by DMP delay calculator
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0002 Liberty.cc:728 cell %s/%s port %s not found in cell %s/%s.
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0003 Liberty.cc:751 cell %s/%s %s -> %s timing group %s not found in cell %s/%s.
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0004 Liberty.cc:1646 cell %s/%s %s -> %s latch enable %s_edge timing arc is inconsistent with %s -> %s setup_%s check.
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0005 Liberty.cc:1661 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function positive sense.
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0006 Liberty.cc:1669 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function negative sense.
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0002 Liberty.cc:735 cell %s/%s port %s not found in cell %s/%s.
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0003 Liberty.cc:758 cell %s/%s %s -> %s timing group %s not found in cell %s/%s.
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0004 Liberty.cc:1653 cell %s/%s %s -> %s latch enable %s_edge timing arc is inconsistent with %s -> %s setup_%s check.
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0005 Liberty.cc:1668 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function positive sense.
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0006 Liberty.cc:1676 cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function negative sense.
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0007 LibertyExpr.cc:78 %s references unknown port %s.
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0008 ConcreteNetwork.cc:1855 cell type %s can not be linked.
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0009 CycleAccting.cc:87 No common period was found between clocks %s and %s.
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@ -96,65 +96,65 @@
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0101 LibertyReader.cc:2579 pin name is not a string.
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0102 LibertyReader.cc:2601 pin name is not a string.
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0103 LibertyReader.cc:2679 bus %s bus_type not found.
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0104 LibertyReader.cc:2736 bus_type %s not found.
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0105 LibertyReader.cc:2739 bus_type is not a string.
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0106 LibertyReader.cc:2757 bundle %s member not found.
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0107 LibertyReader.cc:2784 member is not a string.
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0108 LibertyReader.cc:2791 members attribute is missing values.
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0109 LibertyReader.cc:2834 unknown port direction.
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0110 LibertyReader.cc:3204 pulse_latch unknown pulse type.
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0111 LibertyReader.cc:3581 unknown timing_type %s.
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0112 LibertyReader.cc:3601 unknown timing_sense %s.
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0113 LibertyReader.cc:3641 mode value is not a string.
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0114 LibertyReader.cc:3644 missing mode value.
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0115 LibertyReader.cc:3647 mode name is not a string.
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0116 LibertyReader.cc:3650 mode missing values.
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0117 LibertyReader.cc:3653 mode missing mode name and value.
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0118 LibertyReader.cc:3728 unsupported model axis.
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0119 LibertyReader.cc:3756 unsupported model axis.
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0120 LibertyReader.cc:3786 unsupported model axis.
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0121 LibertyReader.cc:3822 unsupported model axis.
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0122 LibertyReader.cc:3874 table template %s not found.
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0123 LibertyReader.cc:3961 %s is missing values.
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0124 LibertyReader.cc:3986 %s is not a list of floats.
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0125 LibertyReader.cc:3988 table row has %u columns but axis has %d.
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0126 LibertyReader.cc:3998 table has %u rows but axis has %d.
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0127 LibertyReader.cc:4052 lut output is not a string.
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0128 LibertyReader.cc:4090 mode definition missing name.
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0129 LibertyReader.cc:4107 mode value missing name.
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0130 LibertyReader.cc:4121 when attribute inside table model.
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0131 LibertyReader.cc:4170 %s attribute is not a string.
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0132 LibertyReader.cc:4173 %s is not a simple attribute.
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0133 LibertyReader.cc:4196 %s is not a simple attribute.
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0134 LibertyReader.cc:4209 %s is not a simple attribute.
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0135 LibertyReader.cc:4233 %s value %s is not a float.
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0136 LibertyReader.cc:4262 %s missing values.
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0137 LibertyReader.cc:4266 %s missing values.
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0138 LibertyReader.cc:4269 %s is not a complex attribute.
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0139 LibertyReader.cc:4295 %s is not a float.
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0140 LibertyReader.cc:4314 %s is missing values.
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0141 LibertyReader.cc:4317 %s has more than one string.
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0142 LibertyReader.cc:4326 %s is missing values.
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0143 LibertyReader.cc:4351 %s attribute is not boolean.
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0144 LibertyReader.cc:4354 %s attribute is not boolean.
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0145 LibertyReader.cc:4357 %s is not a simple attribute.
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0146 LibertyReader.cc:4373 attribute %s value %s not recognized.
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0147 LibertyReader.cc:4403 unknown early/late value.
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0148 LibertyReader.cc:4627 OCV derate group named %s not found.
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0149 LibertyReader.cc:4643 ocv_derate missing name.
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0150 LibertyReader.cc:4696 unknown rise/fall.
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0151 LibertyReader.cc:4716 unknown derate type.
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0152 LibertyReader.cc:4747 unsupported model axis.
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0153 LibertyReader.cc:4780 unsupported model axis.
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0154 LibertyReader.cc:4813 unsupported model axis.
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0155 LibertyReader.cc:4886 unknown pg_type.
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0156 LibertyReader.cc:5263 port %s subscript out of range.
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0157 LibertyReader.cc:5267 port range %s of non-bus port %s.
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0158 LibertyReader.cc:5281 port %s not found.
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0159 LibertyReader.cc:5351 port %s not found.
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0104 LibertyReader.cc:2735 bus_type %s not found.
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0105 LibertyReader.cc:2738 bus_type is not a string.
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0106 LibertyReader.cc:2756 bundle %s member not found.
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0107 LibertyReader.cc:2783 member is not a string.
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0108 LibertyReader.cc:2790 members attribute is missing values.
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0109 LibertyReader.cc:2833 unknown port direction.
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0110 LibertyReader.cc:3203 pulse_latch unknown pulse type.
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0111 LibertyReader.cc:3580 unknown timing_type %s.
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0112 LibertyReader.cc:3600 unknown timing_sense %s.
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0113 LibertyReader.cc:3640 mode value is not a string.
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0114 LibertyReader.cc:3643 missing mode value.
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0115 LibertyReader.cc:3646 mode name is not a string.
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0116 LibertyReader.cc:3649 mode missing values.
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0117 LibertyReader.cc:3652 mode missing mode name and value.
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0118 LibertyReader.cc:3727 unsupported model axis.
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0119 LibertyReader.cc:3755 unsupported model axis.
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0120 LibertyReader.cc:3785 unsupported model axis.
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0121 LibertyReader.cc:3821 unsupported model axis.
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0122 LibertyReader.cc:3873 table template %s not found.
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0123 LibertyReader.cc:3960 %s is missing values.
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0124 LibertyReader.cc:3985 %s is not a list of floats.
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0125 LibertyReader.cc:3987 table row has %u columns but axis has %d.
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0126 LibertyReader.cc:3997 table has %u rows but axis has %d.
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0127 LibertyReader.cc:4051 lut output is not a string.
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0128 LibertyReader.cc:4089 mode definition missing name.
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0129 LibertyReader.cc:4106 mode value missing name.
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0130 LibertyReader.cc:4120 when attribute inside table model.
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0131 LibertyReader.cc:4169 %s attribute is not a string.
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0132 LibertyReader.cc:4172 %s is not a simple attribute.
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0133 LibertyReader.cc:4195 %s is not a simple attribute.
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0134 LibertyReader.cc:4208 %s is not a simple attribute.
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0135 LibertyReader.cc:4232 %s value %s is not a float.
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0136 LibertyReader.cc:4261 %s missing values.
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0137 LibertyReader.cc:4265 %s missing values.
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0138 LibertyReader.cc:4268 %s is not a complex attribute.
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0139 LibertyReader.cc:4294 %s is not a float.
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0140 LibertyReader.cc:4313 %s is missing values.
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0141 LibertyReader.cc:4316 %s has more than one string.
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0142 LibertyReader.cc:4325 %s is missing values.
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0143 LibertyReader.cc:4350 %s attribute is not boolean.
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0144 LibertyReader.cc:4353 %s attribute is not boolean.
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0145 LibertyReader.cc:4356 %s is not a simple attribute.
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0146 LibertyReader.cc:4372 attribute %s value %s not recognized.
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0147 LibertyReader.cc:4402 unknown early/late value.
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0148 LibertyReader.cc:4626 OCV derate group named %s not found.
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0149 LibertyReader.cc:4642 ocv_derate missing name.
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0150 LibertyReader.cc:4695 unknown rise/fall.
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0151 LibertyReader.cc:4715 unknown derate type.
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0152 LibertyReader.cc:4746 unsupported model axis.
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0153 LibertyReader.cc:4779 unsupported model axis.
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0154 LibertyReader.cc:4812 unsupported model axis.
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0155 LibertyReader.cc:4885 unknown pg_type.
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0156 LibertyReader.cc:5262 port %s subscript out of range.
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0157 LibertyReader.cc:5266 port range %s of non-bus port %s.
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0158 LibertyReader.cc:5280 port %s not found.
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0159 LibertyReader.cc:5350 port %s not found.
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0160 LibertyReader.cc:981 default_max_transition is 0.0.
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0161 LibertyReader.cc:3092 max_transition is 0.0.
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0162 LibertyReader.cc:4193 %s attribute is not an integer.
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0161 LibertyReader.cc:3091 max_transition is 0.0.
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0162 LibertyReader.cc:4192 %s attribute is not an integer.
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0163 LibertyReader.cc:1086 default_fanout_load is 0.0.
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0179 SpefReader.cc:728 %s.
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0190 VerilogReader.cc:1728 %s is not a verilog module.
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@ -20,7 +20,7 @@ namespace eval sta {
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define_cmd_args "read_verilog" {filename}
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proc_redirect read_verilog {
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read_verilog_cmd $args
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read_verilog_cmd [file nativename [lindex $args 0]]
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}
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define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\
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