LibertyBuilder::makeRegLatchArcs null ref resolves #368
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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@ -424,25 +424,27 @@ LibertyBuilder::makeRegLatchArcs(LibertyCell *cell,
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TimingArcAttrsPtr attrs)
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{
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FuncExpr *to_func = to_port->function();
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LibertyPortSet to_ports = to_func->ports();
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for (LibertyPort *func_port : to_ports) {
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Sequential *seq = cell->outputPortSequential(func_port);
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if (seq) {
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if (seq->clock() && seq->clock()->hasPort(from_port)) {
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const TimingRole *role = seq->isRegister() ?
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TimingRole::regClkToQ() : TimingRole::latchEnToQ();
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return makeFromTransitionArcs(cell, from_port, to_port, nullptr,
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from_rf, role, attrs);
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if (to_func) {
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LibertyPortSet to_ports = to_func->ports();
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for (LibertyPort *func_port : to_ports) {
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Sequential *seq = cell->outputPortSequential(func_port);
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if (seq) {
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if (seq->clock() && seq->clock()->hasPort(from_port)) {
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const TimingRole *role = seq->isRegister() ?
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TimingRole::regClkToQ() : TimingRole::latchEnToQ();
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return makeFromTransitionArcs(cell, from_port, to_port, nullptr,
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from_rf, role, attrs);
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}
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else if (seq->isLatch()
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&& seq->data()
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&& seq->data()->hasPort(from_port))
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return makeFromTransitionArcs(cell, from_port, to_port, nullptr,
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from_rf, TimingRole::latchDtoQ(), attrs);
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else if ((seq->clear() && seq->clear()->hasPort(from_port))
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|| (seq->preset() && seq->preset()->hasPort(from_port)))
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return makeFromTransitionArcs(cell, from_port, to_port, nullptr,
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from_rf, TimingRole::regSetClr(), attrs);
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}
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else if (seq->isLatch()
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&& seq->data()
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&& seq->data()->hasPort(from_port))
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return makeFromTransitionArcs(cell, from_port, to_port, nullptr,
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from_rf, TimingRole::latchDtoQ(), attrs);
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else if ((seq->clear() && seq->clear()->hasPort(from_port))
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|| (seq->preset() && seq->preset()->hasPort(from_port)))
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return makeFromTransitionArcs(cell, from_port, to_port, nullptr,
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from_rf, TimingRole::regSetClr(), attrs);
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}
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}
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// No associated ff/latch - assume register clk->q.
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