Merge branch 'master' into sta_update_upstream_lvf_stuff

network/test/CMakeLists.txt

@@ -0,0 +1,6 @@
+sta_module_tests("network"
+  TESTS
+    query
+)
+
+add_subdirectory(cpp)

network/test/cpp/CMakeLists.txt

@@ -0,0 +1,16 @@
+add_executable(TestNetwork TestNetwork.cc)
+target_link_libraries(TestNetwork
+  OpenSTA
+  GTest::gtest
+  GTest::gtest_main
+  ${TCL_LIBRARY}
+)
+target_include_directories(TestNetwork PRIVATE
+  ${STA_HOME}/include/sta
+  ${STA_HOME}
+  ${CMAKE_BINARY_DIR}/include/sta
+)
+gtest_discover_tests(TestNetwork
+  WORKING_DIRECTORY ${STA_HOME}
+  PROPERTIES LABELS "cpp\;module_network"
+)

network/test/network_query.ok

@@ -0,0 +1,3 @@
+Cells: 3
+Nets: 6
+Ports: 4

network/test/network_query.tcl

@@ -0,0 +1,35 @@
+# Read design and query network objects
+read_liberty ../../test/nangate45/Nangate45_typ.lib
+read_verilog network_test1.v
+link_design network_test1
+
+# Query cells
+set cells [get_cells *]
+puts "Cells: [llength $cells]"
+if { [llength $cells] != 3 } {
+  puts "FAIL: expected 3 cells"
+  exit 1
+}
+
+# Query nets
+set nets [get_nets *]
+puts "Nets: [llength $nets]"
+if { [llength $nets] == 0 } {
+  puts "FAIL: no nets found"
+  exit 1
+}
+
+# Query pins
+set pins [get_pins buf1/*]
+if { [llength $pins] == 0 } {
+  puts "FAIL: no pins found on buf1"
+  exit 1
+}
+
+# Query ports
+set ports [get_ports *]
+puts "Ports: [llength $ports]"
+if { [llength $ports] != 4 } {
+  puts "FAIL: expected 4 ports"
+  exit 1
+}

network/test/network_test1.v

@@ -0,0 +1,9 @@
+module network_test1 (clk, in1, in2, out1);
+  input clk, in1, in2;
+  output out1;
+  wire n1, n2;
+
+  BUF_X1 buf1 (.A(in1), .Z(n1));
+  AND2_X1 and1 (.A1(n1), .A2(in2), .ZN(n2));
+  DFF_X1 reg1 (.D(n2), .CK(clk), .Q(out1));
+endmodule

network/test/regression

@@ -0,0 +1 @@
+../../test/regression

network/test/save_ok

@@ -0,0 +1 @@
+../../test/shared/save_ok