Merge branch 'master' into sta_update_upstream_lvf_stuff

graph/test/CMakeLists.txt

@@ -0,0 +1,6 @@
+sta_module_tests("graph"
+  TESTS
+    make_verify
+)
+
+add_subdirectory(cpp)

graph/test/cpp/CMakeLists.txt

@@ -0,0 +1,16 @@
+add_executable(TestGraph TestGraph.cc)
+target_link_libraries(TestGraph
+  OpenSTA
+  GTest::gtest
+  GTest::gtest_main
+  ${TCL_LIBRARY}
+)
+target_include_directories(TestGraph PRIVATE
+  ${STA_HOME}/include/sta
+  ${STA_HOME}
+  ${CMAKE_BINARY_DIR}/include/sta
+)
+gtest_discover_tests(TestGraph
+  WORKING_DIRECTORY ${STA_HOME}
+  PROPERTIES LABELS "cpp\;module_graph"
+)

graph/test/graph_make_verify.ok

@@ -0,0 +1 @@
+No paths found.

graph/test/graph_make_verify.tcl

@@ -0,0 +1,10 @@
+# Read liberty and design, make graph, verify
+read_liberty ../../test/nangate45/Nangate45_typ.lib
+read_verilog graph_test1.v
+link_design graph_test1
+
+# Creating the timing graph implicitly tests graph construction
+create_clock -name clk -period 10 [get_ports clk]
+
+# report_checks exercises the graph
+report_checks -from [get_ports d] -to [get_ports q]

graph/test/graph_test1.v

@@ -0,0 +1,8 @@
+module graph_test1 (clk, d, q);
+  input clk, d;
+  output q;
+  wire n1;
+
+  DFF_X1 reg1 (.D(d), .CK(clk), .Q(n1));
+  DFF_X1 reg2 (.D(n1), .CK(clk), .Q(q));
+endmodule

graph/test/graph_test2.v

@@ -0,0 +1,14 @@
+module graph_test2 (clk, d1, d2, en, q1, q2);
+  input clk, d1, d2, en;
+  output q1, q2;
+  wire n1, n2, n3, n4, n5, n6;
+
+  BUF_X1 buf1 (.A(d1), .Z(n1));
+  BUF_X2 buf2 (.A(d2), .Z(n2));
+  INV_X1 inv1 (.A(n1), .ZN(n3));
+  AND2_X1 and1 (.A1(n3), .A2(en), .ZN(n4));
+  OR2_X1 or1 (.A1(n2), .A2(n4), .ZN(n5));
+  BUF_X1 buf3 (.A(n5), .Z(n6));
+  DFF_X1 reg1 (.D(n4), .CK(clk), .Q(q1));
+  DFF_X1 reg2 (.D(n6), .CK(clk), .Q(q2));
+endmodule

graph/test/graph_test3.v

@@ -0,0 +1,34 @@
+// Larger design for graph operations testing: more cell types, fan-in/fan-out,
+// multiple clock domains, and reconvergent paths.
+module graph_test3 (clk1, clk2, rst, d1, d2, d3, d4, q1, q2, q3);
+  input clk1, clk2, rst, d1, d2, d3, d4;
+  output q1, q2, q3;
+  wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12;
+
+  // Input stage: buffers and inverters
+  BUF_X1 buf1 (.A(d1), .Z(n1));
+  BUF_X2 buf2 (.A(d2), .Z(n2));
+  INV_X1 inv1 (.A(d3), .ZN(n3));
+  INV_X2 inv2 (.A(d4), .ZN(n4));
+
+  // Middle stage: logic gates
+  AND2_X1 and1 (.A1(n1), .A2(n2), .ZN(n5));
+  OR2_X1 or1 (.A1(n3), .A2(n4), .ZN(n6));
+  NAND2_X1 nand1 (.A1(n5), .A2(n6), .ZN(n7));
+  NOR2_X1 nor1 (.A1(n1), .A2(n3), .ZN(n8));
+
+  // Reconvergent fan-out
+  AND2_X2 and2 (.A1(n7), .A2(n8), .ZN(n9));
+  OR2_X2 or2 (.A1(n7), .A2(n8), .ZN(n10));
+
+  // Clock domain 1 registers
+  DFF_X1 reg1 (.D(n9), .CK(clk1), .Q(n11));
+  DFF_X1 reg2 (.D(n10), .CK(clk1), .Q(q1));
+
+  // Clock domain 2 register (cross-domain)
+  DFF_X1 reg3 (.D(n11), .CK(clk2), .Q(n12));
+  BUF_X1 buf3 (.A(n12), .Z(q2));
+
+  // Combinational output
+  BUF_X4 buf4 (.A(n7), .Z(q3));
+endmodule

graph/test/regression

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+../../test/regression

graph/test/save_ok

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+../../test/shared/save_ok