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rename LibertyCell::hasSequentials to isSequential 

Signed-off-by: James Cherry <cherry@CerezoBook.local>
This commit is contained in:
James Cherry 2026-06-22 19:20:39 -07:00
parent 458c277c80
commit a456c352cf
4 changed files with 18 additions and 4 deletions
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5
doc/ApiChanges.txt
View File

@ -24,6 +24,11 @@
This file summarizes STA API changes for each release.
2026/06/22
----------
Liberty::hasSequentials has been renamed isSequential.
Release 3.1.0 2026/03/25
------------------------

4
include/sta/Liberty.hh
View File

@ -536,7 +536,9 @@ public:
bool leakagePowerExists() const { return leakage_power_exists_; }
// Register, Latch or Statetable.
bool hasSequentials() const;
bool isSequential() const;
// deprecated 2026-06-22 (use isSequential)
bool hasSequentials() const __attribute__ ((deprecated));
const SequentialSeq &sequentials() const { return sequentials_; }
// Find the sequential with the output connected to an (internal) port.
Sequential *outputPortSequential(LibertyPort *port);

8
liberty/Liberty.cc
View File

@ -1438,6 +1438,12 @@ LibertyCell::outputPortSequential(LibertyPort *port)
return nullptr;
}
bool
LibertyCell::isSequential() const
{
return !sequentials_.empty() || statetable_ != nullptr;
}
bool
LibertyCell::hasSequentials() const
{
@ -1618,7 +1624,7 @@ void
LibertyCell::makeLatchEnables(Report *report,
Debug *debug)
{
if (hasSequentials()
if (isSequential()
|| hasInferedRegTimingArcs()) {
for (TimingArcSet *d_to_q : timing_arc_sets_) {
if (d_to_q->role() == TimingRole::latchDtoQ()) {

5
power/Power.cc
View File

@ -443,7 +443,7 @@ Power::power(const Scene *scene,
pad.incr(inst_power);
else if (inClockNetwork(inst, clk_network))
clock.incr(inst_power);
else if (cell->hasSequentials())
else if (cell->isSequential())
sequential.incr(inst_power);
else
combinational.incr(inst_power);
@ -695,7 +695,8 @@ PropActivityVisitor::visit(Vertex *vertex)
if (cell) {
LibertyCell *test_cell = cell->libertyCell()->testCell();
if (network_->isLoad(pin)) {
if (cell->hasSequentials() || (test_cell && test_cell->hasSequentials())) {
if (cell->isSequential()
|| (test_cell && test_cell->isSequential())) {
debugPrint(debug_, "power_activity", 3, "pending seq {}",
network_->pathName(inst));
visited_regs_.insert(inst);