Allow SDC `get_*` with 0 args and on object references

This commit is contained in:
Akash Levy 2024-09-21 18:51:11 -07:00
parent 7de907223b
commit a31a67b7df
3 changed files with 115 additions and 20 deletions

View File

@ -452,7 +452,11 @@ proc get_cells { args } {
set hierarchical [info exists flags(-hierarchical)]
set quiet [info exists flags(-quiet)]
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} [lindex $args 0]]
if { $args == {} } {
set patterns "*"
} else {
set patterns [string map {\\ \\\\} [lindex $args 0]]
}
set divider $hierarchy_separator
if [info exists keys(-hsc)] {
set divider $keys(-hsc)
@ -483,8 +487,12 @@ proc get_cells { args } {
$pin_iter finish
}
} else {
check_argc_eq1 "get_cells" $args
check_argc_eq0or1 "get_cells" $args
foreach pattern $patterns {
if { [is_object $pattern] } {
set insts [concat $insts $pattern]
continue
}
if { $divider != $hierarchy_separator } {
regsub $divider $pattern $hierarchy_separator pattern
}
@ -507,21 +515,29 @@ proc get_cells { args } {
################################################################
define_cmd_args "get_clocks" {[-regexp] [-nocase] [-quiet] [-filter expr] patterns}
define_cmd_args "get_clocks" {[-regexp] [-nocase] [-quiet] [-filter expr] [patterns]}
define_cmd_alias "get_clock" "get_clocks"
proc get_clocks { args } {
parse_key_args "get_clocks" args keys {-filter} flags {-regexp -nocase -quiet}
check_argc_eq1 "get_clocks" $args
check_argc_eq0or1 "get_clocks" $args
check_nocase_flag flags
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} [lindex $args 0]]
if { $args == {} } {
set patterns "*"
} else {
set patterns [string map {\\ \\\\} [lindex $args 0]]
}
set regexp [info exists flags(-regexp)]
set nocase [info exists flags(-nocase)]
set clocks {}
foreach pattern $patterns {
if { [is_object $pattern] } {
set clocks [concat $clocks $pattern]
continue
}
set matches [find_clocks_matching $pattern $regexp $nocase]
if { $matches != {} } {
set clocks [concat $clocks $matches]
@ -563,9 +579,13 @@ proc get_lib_cells { args } {
lappend cells [$inst liberty_cell]
}
} else {
check_argc_eq1 "get_lib_cells" $args
check_argc_eq0or1 "get_lib_cells" $args
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} [lindex $args 0]]
if { $args == {} } {
set patterns "*"
} else {
set patterns [string map {\\ \\\\} [lindex $args 0]]
}
# Parse library_name/pattern.
set divider $hierarchy_separator
if [info exists keys(-hsc)] {
@ -575,6 +595,10 @@ proc get_lib_cells { args } {
set cell_regexp [cell_regexp_hsc $divider]
set quiet [info exists flags(-quiet)]
foreach pattern $patterns {
if { [is_object $pattern] } {
set cells [concat $cells $pattern]
continue
}
if { ![regexp $cell_regexp $pattern ignore lib_name cell_pattern]} {
set lib_name "*"
set cell_pattern $pattern
@ -610,7 +634,7 @@ proc get_lib_cells { args } {
################################################################
define_cmd_args "get_lib_pins" \
{[-hsc separator] [-regexp] [-nocase] [-quiet] [-filter expr] patterns}
{[-hsc separator] [-regexp] [-nocase] [-quiet] [-filter expr] [patterns]}
define_cmd_alias "get_lib_pin" "get_lib_pins"
@ -618,14 +642,18 @@ define_cmd_alias "get_lib_pin" "get_lib_pins"
proc get_lib_pins { args } {
global hierarchy_separator
parse_key_args "get_lib_pins" args keys {-hsc -filter} flags {-regexp -nocase -quiet}
check_argc_eq1 "get_lib_pins" $args
check_argc_eq0or1 "get_lib_pins" $args
check_nocase_flag flags
set regexp [info exists flags(-regexp)]
set nocase [info exists flags(-nocase)]
set quiet [info exists flags(-quiet)]
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} [lindex $args 0]]
if { $args == {} } {
set patterns "*/*"
} else {
set patterns [string map {\\ \\\\} [lindex $args 0]]
}
# Parse library_name/cell_name/pattern.
set divider $hierarchy_separator
if [info exists keys(-hsc)] {
@ -636,6 +664,10 @@ proc get_lib_pins { args } {
set port_regexp2 [cell_regexp_hsc $divider]
set ports {}
foreach pattern $patterns {
if { [is_object $pattern] } {
set ports [concat $ports $pattern]
continue
}
# match library/cell/port
set libs {}
if { [regexp $port_regexp1 $pattern ignore lib_name cell_name port_pattern] } {
@ -689,21 +721,29 @@ proc check_nocase_flag { flags_var } {
################################################################
define_cmd_args "get_libs" {[-regexp] [-nocase] [-quiet] [-filter expr] patterns}
define_cmd_args "get_libs" {[-regexp] [-nocase] [-quiet] [-filter expr] [patterns]}
define_cmd_alias "get_lib" "get_libs"
proc get_libs { args } {
parse_key_args "get_libs" args keys {-filter} flags {-regexp -nocase -quiet}
check_argc_eq1 "get_libs" $args
check_argc_eq0or1 "get_libs" $args
check_nocase_flag flags
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} [lindex $args 0]]
if { $args == {} } {
set patterns "*"
} else {
set patterns [string map {\\ \\\\} [lindex $args 0]]
}
set regexp [info exists flags(-regexp)]
set nocase [info exists flags(-nocase)]
set libs {}
foreach pattern $patterns {
if { [is_object $pattern] } {
set libs [concat $libs $pattern]
continue
}
set matches [find_liberty_libraries_matching $pattern $regexp $nocase]
if {$matches != {}} {
set libs [concat $libs $matches]
@ -766,7 +806,11 @@ proc get_nets { args } {
set hierarchical [info exists flags(-hierarchical)]
set quiet [info exists flags(-quiet)]
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} [lindex $args 0]]
if { $args == {} } {
set patterns "*"
} else {
set patterns [string map {\\ \\\\} [lindex $args 0]]
}
if [info exists keys(-hsc)] {
set divider $keys(-hsc)
check_path_divider $divider
@ -790,8 +834,12 @@ proc get_nets { args } {
lappend nets [$pin net]
}
} else {
check_argc_eq1 "get_nets" $args
check_argc_eq0or1 "get_nets" $args
foreach pattern $patterns {
if { [is_object $pattern] } {
set nets [concat $nets $pattern]
continue
}
if { $hierarchical } {
set matches [find_nets_hier_matching $pattern $regexp $nocase]
} else {
@ -851,8 +899,12 @@ proc get_pins { args } {
$pin_iter finish
}
} else {
check_argc_eq1 "get_pins" $args
set patterns [lindex $args 0]
check_argc_eq0or1 "get_pins" $args
if { $args == {} } {
set patterns "*"
} else {
set patterns [lindex $args 0]
}
if [info exists keys(-hsc)] {
set divider $keys(-hsc)
check_path_divider $divider
@ -861,6 +913,10 @@ proc get_pins { args } {
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} $patterns]
foreach pattern $patterns {
if { [is_object $pattern] } {
set pins [concat $pins $pattern]
continue
}
if { $hierarchical } {
set matches [find_pins_hier_matching $pattern $regexp $nocase]
} else {
@ -894,7 +950,11 @@ proc get_ports { args } {
set regexp [info exists flags(-regexp)]
set nocase [info exists flags(-nocase)]
# Copy backslashes that will be removed by foreach.
set patterns [string map {\\ \\\\} [lindex $args 0]]
if { $args == {} } {
set patterns "*"
} else {
set patterns [string map {\\ \\\\} [lindex $args 0]]
}
set ports {}
if [info exists keys(-of_objects)] {
if { $args != {} } {
@ -905,8 +965,12 @@ proc get_ports { args } {
set ports [concat $ports [$net ports]]
}
} else {
check_argc_eq1 "get_ports" $args
check_argc_eq0or1 "get_ports" $args
foreach pattern $patterns {
if { [is_object $pattern] } {
set ports [concat $ports $pattern]
continue
}
set matches [find_ports_matching $pattern $regexp $nocase]
if { $matches != {} } {
set ports [concat $ports $matches]
@ -2755,7 +2819,11 @@ proc set_driving_cell { args } {
}
} else {
set library "NULL"
set cell [find_liberty_cell $cell_name]
if { [string match *_p_LibertyCell $cell_name] } {
set cell $cell_name
} else {
set cell [find_liberty_cell $cell_name]
}
if { $cell == "NULL" } {
sta_error 453 "'$cell_name' not found."
}

View File

@ -0,0 +1,26 @@
# Test get_* with no arguments and on object references
# Read in design and libraries
read_liberty asap7_small.lib.gz
read_verilog reg1_asap7.v
link_design top
create_clock -name clk -period 500 {clk1 clk2 clk3}
create_clock -name vclk -period 1000
# Test each SDC get_* command with no arguments and on object references
puts {[get_cells [get_cells]]}
report_object_full_names [get_cells [get_cells]]
puts {[get_clocks [get_clocks]]}
report_object_full_names [get_clocks [get_clocks]]
puts {[get_lib_cells [get_lib_cells]]}
report_object_full_names [get_lib_cells [get_lib_cells]]
puts {[get_lib_pins [get_lib_pins]]}
report_object_full_names [get_lib_pins [get_lib_pins]]
puts {[get_libs [get_libs]]}
report_object_full_names [get_libs [get_libs]]
puts {[get_nets [get_nets]]}
report_object_full_names [get_nets [get_nets]]
puts {[get_pins [get_pins]]}
report_object_full_names [get_pins [get_pins]]
puts {[get_ports [get_ports]]}
report_object_full_names [get_ports [get_ports]]

View File

@ -127,6 +127,7 @@ record_sta_tests {
liberty_arcs_one2one_1
liberty_arcs_one2one_2
get_filter
get_noargs_objrefs
}
define_test_group fast [group_tests all]