rm ccs_sim dcalc

Signed-off-by: James Cherry <[email protected]>

test/ccs_sim1.ok

@@ -1,17 +0,0 @@
-Startpoint: in1 (input port)
-Endpoint: out1 (output port)
-Path Group: unconstrained
-Path Type: max
-
-    Slew    Delay     Time   Description
--------------------------------------------------------------------
-            0.000    0.000 v input external delay
-  20.000    0.000    0.000 v in1 (in)
-  20.000    0.000    0.000 v u1/A (INVx8_ASAP7_75t_R)
-  49.139   20.018   20.018 ^ u1/Y (INVx8_ASAP7_75t_R)
- 139.668   44.168   64.186 ^ out1 (out)
-                    64.186   data arrival time
--------------------------------------------------------------------
-(Path is unconstrained)
-
-

test/ccs_sim1.spef

@@ -1,37 +0,0 @@
-*SPEF "IEEE 1481-1998"
-*DESIGN "top"
-*DATE "Tue Sep 25 11:51:50 2012"
-*VENDOR "handjob"
-*PROGRAM "handjob"
-*VERSION "0.0"
-*DESIGN_FLOW "NETLIST_TYPE_VERILOG"
-*DIVIDER /
-*DELIMITER :
-*BUS_DELIMITER [ ]
-*T_UNIT 1 PS
-*C_UNIT 1 FF
-*R_UNIT 1 KOHM
-*L_UNIT 1 UH
-
-*POWER_NETS VDD
-*GROUND_NETS VSS
-
-*PORTS
-in1 I
-out1 O
-
-*D_NET out1 16.6
-*CONN
-*I u1:Y O
-*I u2:Y O
-*I out1 O
-*CAP
-1 u1:Y 10
-2 u2:Y 10
-3 out1:1 10
-4 out1 50
-*RES
-1 u1:Y out1:1 0.1
-2 u2:Y out1:1 0.1
-3 out1:1 out1 1.0
-*END

test/ccs_sim1.tcl

@@ -1,8 +0,0 @@
-# ccs_sim parallel inverters
-read_liberty asap7_invbuf.lib.gz
-read_verilog ccs_sim1.v
-link_design top
-read_spef ccs_sim1.spef
-set_input_transition 20 in1 
-sta::set_delay_calculator ccs_sim
-report_checks -fields {input_pins slew} -unconstrained -digits 3

test/ccs_sim1.v

@@ -1,7 +0,0 @@
-module top (in1, out1);
-  input in1;
-  output out1;
-
-  INVx8_ASAP7_75t_R u1 (.A(in1), .Y(out1));
-  INVx8_ASAP7_75t_R u2 (.A(in1), .Y(out1));
-endmodule // top

test/regression_vars.tcl

@@ -122,7 +122,6 @@ record_example_tests {
 }
 
 record_sta_tests {
-  ccs_sim1
   prima3
   verilog_attribute
 }