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name, asString -> to_string, const 

commit d122d05822e02dcc08c665ac6ec7513791dd7209
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Mar 27 08:58:22 2025 -0700

    rebase

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 9c7ae9a7ddd885ebdab102d48b3f39dc5dacf948
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Mar 25 16:21:52 2025 -0700

    write_spice8

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 2bd088f03bb2e414305232d9ebd76c9d1958ec81
Author: James Cherry <cherry@parallaxsw.com>
Date:   Tue Mar 25 10:08:00 2025 -0700

    liberty reader stringify

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 86974caf063433b37ed1378e7103db4b2e55a04c
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 20:25:39 2025 -0700

    ConcreteLiberary/Cell/Port use string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 334476e185149a90b35cdd859e0a760ec9aa242a
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 20:16:08 2025 -0700

    leak

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 5130e8d44804f483d9099d48bb413a7f3362b4e1
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 15:57:14 2025 -0700

    liberty parser stringify

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit d48eba88cbde9093e3eb12bcee8eb48ccd444434
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 11:16:04 2025 -0700

    stringify

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 6913fb198d642f6b05a94fb1852064706a748b81
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 11:06:17 2025 -0700

    stringify

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 371bca08ecf9bf816b7adcbb7ae1458c4073f5f8
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 10:44:31 2025 -0700

    TableTemplate use string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 326465920a1f4a33dbe6be35cff5ca2245b6677e
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 09:04:55 2025 -0700

    use string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit b93a542ddfbcb5c793c9b533cbe64ea20ec08f4a
Author: James Cherry <cherry@parallaxsw.com>
Date:   Mon Mar 24 08:59:01 2025 -0700

    timingSenseString -> to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 6c121a0ff4231b37df076a62e83832897be62ff4
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Mar 23 16:09:47 2025 -0700

    Corner use string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 07b989a5a43bf5d341aa6ba2880be663997577d5
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Mar 23 16:05:43 2025 -0700

    Tag::to_string()

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 0b9480cc5a3fa9ef0cb1c6e8ba0d4a29de2df816
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Mar 23 15:53:29 2025 -0700

    PathAnalysisPt::to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit a028659091e99270f7501615285730681ed59523
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sun Mar 23 12:19:03 2025 -0700

    TimingRole stati alloc

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 495be6a57bda23d82e511282f5db7c188b32971b
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Mar 22 21:36:52 2025 -0700

    RiseFall/RiseFallBoth/Transition const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4c4b28adb383321b1172f4b774c7c4d9a1aee69f
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Mar 22 20:38:26 2025 -0700

    TimingRole const

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 54ab58ec7200d420bf3b5e709e74b652af88d508
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Mar 22 14:15:07 2025 -0700

    const MinMax

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit f70bb38df17b2ed758c7b6ba5647b7355366c0c0
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Mar 22 13:14:31 2025 -0700

    Transition::to_string(()

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit b3f3d67328194351fb8efac2219bcfbcec331552
Author: James Cherry <cherry@parallaxsw.com>
Date:   Sat Mar 22 12:33:25 2025 -0700

    RiseFall::to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4046f8a376926dfde980860c51d2c5c70cf4a867
Author: James Cherry <cherry@parallaxsw.com>
Date:   Thu Mar 20 09:04:10 2025 -0700

    TimingRole::name -> to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit cf4dd918eccb05d459f1804ced8365c81a5c6a50
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Mar 19 20:14:42 2025 -0700

    MinMax::asString -> to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit d80118117dda25be7b2b4896f19e955645c27f73
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Mar 19 17:43:08 2025 -0700

    TimingRole::name -> to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 284fa25c28aca998e8ce92e7b7bb927697494a13
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Mar 19 17:02:27 2025 -0700

    comment

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 646f19749b997e03dc4cbdf165cd7637010276d3
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Mar 19 14:47:40 2025 -0700

    FuncExpr::asString -> to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 4f73d8e7ad21feac6f41130b7b070f3e345b6fb5
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Mar 19 14:04:13 2025 -0700

    Vertex::name -> to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 7c7ec486aaea86f6607a1ef72bb1a74dca603831
Author: James Cherry <cherry@parallaxsw.com>
Date:   Wed Mar 19 13:39:24 2025 -0700

    Vertex::name -> to_string

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2025-03-30 15:27:53 -07:00
parent a25d72c7be
commit 932525bd87
102 changed files with 1201 additions and 1365 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
CMakeLists.txt
View File

@ -32,7 +32,7 @@ if(CMAKE_VERSION VERSION_GREATER_EQUAL 3.14)
cmake_policy(SET CMP0086 NEW)
endif()
project(STA VERSION 2.6.1
project(STA VERSION 2.6.2
LANGUAGES CXX
)

2
dcalc/CcsCeffDelayCalc.cc
View File

@ -119,7 +119,7 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin,
ref_time_ = output_waveforms_->referenceTime(in_slew_);
debugPrint(debug_, "ccs_dcalc", 1, "%s %s",
drvr_cell->name(),
drvr_rf_->asString());
drvr_rf_->to_string().c_str());
ArcDelay gate_delay;
Slew drvr_slew;
gateDelaySlew(drvr_library, drvr_rf_, gate_delay, drvr_slew);

2
dcalc/DelayCalcBase.cc
View File

@ -55,7 +55,7 @@ DelayCalcBase::reduceParasitic(const Parasitic *parasitic_network,
while (pin_iter->hasNext()) {
const Pin *pin = pin_iter->next();
if (network_->isDriver(pin)) {
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
for (const MinMax *min_max : min_max->range()) {
if (corner == nullptr) {
for (const Corner *corner1 : *corners_) {

44
dcalc/GraphDelayCalc.cc
View File

@ -171,7 +171,7 @@ void
GraphDelayCalc::delayInvalid(Vertex *vertex)
{
debugPrint(debug_, "delay_calc", 2, "delay invalid %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
if (graph_ && incremental_) {
invalid_delays_->insert(vertex);
// Invalidate driver that triggers dcalc for multi-driver nets.
@ -315,7 +315,7 @@ GraphDelayCalc::seedDrvrSlew(Vertex *drvr_vertex,
{
const Pin *drvr_pin = drvr_vertex->pin();
debugPrint(debug_, "delay_calc", 2, "seed driver slew %s",
drvr_vertex->name(sdc_network_));
drvr_vertex->to_string(this).c_str());
InputDrive *drive = 0;
if (network_->isTopLevelPort(drvr_pin)) {
Port *port = network_->port(drvr_pin);
@ -426,7 +426,7 @@ GraphDelayCalc::seedLoadSlew(Vertex *vertex)
{
const Pin *pin = vertex->pin();
debugPrint(debug_, "delay_calc", 2, "seed load slew %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
ClockSet *clks = sdc_->findLeafPinClocks(pin);
initSlew(vertex);
for (const RiseFall *rf : RiseFall::range()) {
@ -501,7 +501,7 @@ GraphDelayCalc::findInputDriverDelay(const LibertyCell *drvr_cell,
{
debugPrint(debug_, "delay_calc", 2, " driver cell %s %s",
drvr_cell->name(),
rf->asString());
rf->to_string().c_str());
for (TimingArcSet *arc_set : drvr_cell->timingArcSets(from_port, to_port)) {
for (TimingArc *arc : arc_set->arcs()) {
if (arc->toEdge()->asRiseFall() == rf) {
@ -525,10 +525,10 @@ GraphDelayCalc::findInputArcDelay(const Pin *drvr_pin,
{
debugPrint(debug_, "delay_calc", 3, " %s %s -> %s %s (%s)",
arc->from()->name(),
arc->fromEdge()->asString(),
arc->fromEdge()->to_string().c_str(),
arc->to()->name(),
arc->toEdge()->asString(),
arc->role()->asString());
arc->toEdge()->to_string().c_str(),
arc->role()->to_string().c_str());
const RiseFall *drvr_rf = arc->toEdge()->asRiseFall();
if (drvr_rf) {
DcalcAPIndex ap_index = dcalc_ap->index();
@ -577,7 +577,7 @@ GraphDelayCalc::findVertexDelay(Vertex *vertex,
{
const Pin *pin = vertex->pin();
debugPrint(debug_, "delay_calc", 2, "find delays %s (%s)",
vertex->name(sdc_network_),
vertex->to_string(this).c_str(),
network_->cellName(network_->instance(pin)));
if (vertex->isRoot()) {
seedRootSlew(vertex, arc_delay_calc);
@ -1091,12 +1091,12 @@ GraphDelayCalc::annotateDelaySlew(Edge *edge,
debugPrint(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s) corner:%s/%s",
arc->from()->name(),
arc->fromEdge()->asString(),
arc->fromEdge()->to_string().c_str(),
arc->to()->name(),
arc->toEdge()->asString(),
arc->role()->asString(),
arc->toEdge()->to_string().c_str(),
arc->role()->to_string().c_str(),
dcalc_ap->corner()->name(),
dcalc_ap->delayMinMax()->asString());
dcalc_ap->delayMinMax()->to_string().c_str());
debugPrint(debug_, "delay_calc", 3,
" gate delay = %s slew = %s",
delayAsString(gate_delay, this),
@ -1149,7 +1149,7 @@ GraphDelayCalc::annotateLoadDelays(Vertex *drvr_vertex,
Slew load_slew = dcalc_result.loadSlew(load_idx);
debugPrint(debug_, "delay_calc", 3,
" %s load delay = %s slew = %s",
load_vertex->name(sdc_network_),
load_vertex->to_string(this).c_str(),
delayAsString(wire_delay, this),
delayAsString(load_slew, this));
bool load_changed = false;
@ -1465,8 +1465,8 @@ GraphDelayCalc::findCheckEdgeDelays(Edge *edge,
network_->portName(to_pin));
bool delay_changed = false;
for (TimingArc *arc : arc_set->arcs()) {
RiseFall *from_rf = arc->fromEdge()->asRiseFall();
RiseFall *to_rf = arc->toEdge()->asRiseFall();
const RiseFall *from_rf = arc->fromEdge()->asRiseFall();
const RiseFall *to_rf = arc->toEdge()->asRiseFall();
if (from_rf && to_rf) {
const LibertyPort *related_out_port = arc_set->relatedOut();
const Pin *related_out_pin = 0;
@ -1482,12 +1482,12 @@ GraphDelayCalc::findCheckEdgeDelays(Edge *edge,
debugPrint(debug_, "delay_calc", 3,
" %s %s -> %s %s (%s) corner:%s/%s",
arc_set->from()->name(),
arc->fromEdge()->asString(),
arc->fromEdge()->to_string().c_str(),
arc_set->to()->name(),
arc->toEdge()->asString(),
arc_set->role()->asString(),
arc->toEdge()->to_string().c_str(),
arc_set->role()->to_string().c_str(),
dcalc_ap->corner()->name(),
dcalc_ap->delayMinMax()->asString());
dcalc_ap->delayMinMax()->to_string().c_str());
debugPrint(debug_, "delay_calc", 3,
" from_slew = %s to_slew = %s",
delayAsString(from_slew, this),
@ -1538,13 +1538,13 @@ GraphDelayCalc::reportDelayCalc(const Edge *edge,
Vertex *from_vertex = edge->from(graph_);
Vertex *to_vertex = edge->to(graph_);
Pin *to_pin = to_vertex->pin();
TimingRole *role = arc->role();
const TimingRole *role = arc->role();
const Instance *inst = network_->instance(to_pin);
const TimingArcSet *arc_set = edge->timingArcSet();
string result;
DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max);
RiseFall *from_rf = arc->fromEdge()->asRiseFall();
RiseFall *to_rf = arc->toEdge()->asRiseFall();
const RiseFall *from_rf = arc->fromEdge()->asRiseFall();
const RiseFall *to_rf = arc->toEdge()->asRiseFall();
if (from_rf && to_rf) {
const LibertyPort *related_out_port = arc_set->relatedOut();
const Pin *related_out_pin = 0;

4
dcalc/PrimaDelayCalc.cc
View File

@ -228,7 +228,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
output_waveforms_[drvr_idx] = output_waveforms;
debugPrint(debug_, "ccs_dcalc", 1, "%s %s",
dcalc_arg.drvrCell()->name(),
drvr_rf_->asString());
drvr_rf_->to_string().c_str());
LibertyCell *drvr_cell = dcalc_arg.drvrCell();
const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary();
bool vdd_exists;
@ -741,7 +741,7 @@ PrimaDelayCalc::dcalcResults()
debugPrint(debug_, "ccs_dcalc", 2,
"load %s %s delay %s slew %s",
network_->pathName(load_pin),
drvr_rf_->asString(),
drvr_rf_->to_string().c_str(),
delayAsString(wire_delay, this),
delayAsString(load_slew, this));

26
doc/ApiChanges.txt
View File

@ -24,6 +24,32 @@
This file summarizes STA API changes for each release.
Release 2.6.2 2024/03/30
------------------------
The following functions have been renamed to to_string and return std::string
instead of "const char*"
Vertex::name
FuncExpr::asString
TimingRole::name
MinMax::asString
MinMaxAll::asString
RiseFall::asString
RiseFallBoth::asString
Transition::asString
Tag::asString
timingSenseString
The following classes now return const objects.
MinMax
MinMaxAll
RiseFall
RiseFallBoth
Transition
TimingRole
Release 2.6.1 2025/03/??
-------------------------

36
graph/Graph.cc
View File

@ -206,7 +206,7 @@ Graph::makePortInstanceEdges(const Instance *inst,
// Vertices can be missing from the graph if the pins
// are power or ground.
if (from_vertex) {
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
bool is_check = role->isTimingCheckBetween();
if (to_bidirect_drvr_vertex && !is_check)
makeEdge(from_vertex, to_bidirect_drvr_vertex, arc_set);
@ -993,19 +993,27 @@ Vertex::setObjectIdx(ObjectIdx idx)
object_idx_ = idx;
}
const char *
Vertex::name(const Network *network) const
string
Vertex::to_string(const StaState *sta) const
{
const Network *network = sta->network();
if (network->direction(pin_)->isBidirect()) {
const char *pin_name = network->pathName(pin_);
return stringPrintTmp("%s %s",
pin_name,
is_bidirect_drvr_ ? "driver" : "load");
string str = network->pathName(pin_);
str += ' ';
str += is_bidirect_drvr_ ? "driver" : "load";
return str;
}
else
return network->pathName(pin_);
}
const char *
Vertex::name(const Network *network) const
{
string name = to_string(network);
return makeTmpString(name);
}
bool
Vertex::isDriver(const Network *network) const
{
@ -1245,6 +1253,16 @@ Edge::setObjectIdx(ObjectIdx idx)
object_idx_ = idx;
}
string
Edge::to_string(const StaState *sta) const
{
const Graph *graph = sta->graph();
string str = from(graph)->to_string(sta);
str += " -> ";
str += to(graph)->to_string(sta);
return str;
}
void
Edge::setTimingArcSet(TimingArcSet *set)
{
@ -1310,7 +1328,7 @@ Edge::setDelayAnnotationIsIncremental(bool is_incr)
delay_annotation_is_incremental_ = is_incr;
}
TimingRole *
const TimingRole *
Edge::role() const
{
return arc_set_->role();
@ -1344,7 +1362,7 @@ Edge::setSimTimingSense(TimingSense sense)
bool
Edge::isDisabledConstraint() const
{
TimingRole *role = arc_set_->role();
const TimingRole *role = arc_set_->role();
bool is_wire = role->isWire();
return is_disabled_constraint_
|| arc_set_->isDisabledConstraint()

16
graph/Graph.i
View File

@ -316,8 +316,8 @@ Vertex *from() { return self->from(Sta::sta()->graph()); }
Vertex *to() { return self->to(Sta::sta()->graph()); }
Pin *from_pin() { return self->from(Sta::sta()->graph())->pin(); }
Pin *to_pin() { return self->to(Sta::sta()->graph())->pin(); }
TimingRole *role() { return self->role(); }
const char *sense() { return timingSenseString(self->sense()); }
const TimingRole *role() { return self->role(); }
const char *sense() { return to_string(self->sense()); }
TimingArcSeq &
timing_arcs() { return self->timingArcSet()->arcs(); }
bool is_disabled_loop() { return Sta::sta()->isDisabledLoop(self); }
@ -334,7 +334,7 @@ bool is_disabled_bidirect_net_path()
bool is_disabled_preset_clear()
{ return Sta::sta()->isDisabledPresetClr(self); }
const char *
sim_timing_sense(){return timingSenseString(Sta::sta()->simTimingSense(self));}
sim_timing_sense(){return to_string(Sta::sta()->simTimingSense(self));}
FloatSeq
arc_delays(TimingArc *arc)
@ -376,14 +376,14 @@ arc_delay(TimingArc *arc,
return delayAsFloat(Sta::sta()->arcDelay(self, arc, dcalc_ap));
}
const char *
string
cond()
{
FuncExpr *cond = self->timingArcSet()->cond();
if (cond)
return cond->asString();
return cond->to_string();
else
return nullptr;
return "";
}
const char *
@ -414,7 +414,9 @@ latch_d_to_q_en()
const RiseFall *enable_rf;
lib_cell->latchEnable(d_q_set, enable_port, enable_func, enable_rf);
if (enable_port)
return stringPrintTmp("%s %s", enable_port->name(), enable_rf->asString());
return stringPrintTmp("%s %s",
enable_port->name(),
enable_rf->to_string().c_str());
}
return "";
}

2
include/sta/Bfs.hh
View File

@ -75,7 +75,7 @@ public:
// Notify iterator that vertex will be deleted.
void deleteVertexBefore(Vertex *vertex);
void remove(Vertex *vertex);
void reportEntries(const Network *network);
void reportEntries();
virtual bool hasNext();
bool hasNext(Level to_level);

9
include/sta/Clock.hh
View File

@ -203,7 +203,7 @@ class ClockEdge
public:
Clock *clock() const { return clock_; }
~ClockEdge();
RiseFall *transition() const { return rf_; }
const RiseFall *transition() const { return rf_; }
float time() const { return time_; }
const char *name() const { return name_; }
int index() const { return index_; }
@ -213,11 +213,12 @@ public:
friend class Clock; // builder
private:
ClockEdge(Clock *clock, RiseFall *rf);
ClockEdge(Clock *clock,
const RiseFall *rf);
void setTime(float time);
Clock *clock_;
RiseFall *rf_;
const RiseFall *rf_;
const char *name_;
float time_;
int index_;
@ -262,7 +263,7 @@ public:
void removeUncertainty(const RiseFallBoth *src_rf,
const RiseFallBoth *tgt_rf,
const SetupHoldAll *setup_hold);
const RiseFallMinMax *uncertainties(RiseFall *src_rf) const;
const RiseFallMinMax *uncertainties(const RiseFall *src_rf) const;
bool empty() const;
private:

24
include/sta/ConcreteLibrary.hh
View File

@ -45,10 +45,10 @@ class PatternMatch;
class LibertyCell;
class LibertyPort;
typedef Map<const char*, ConcreteCell*, CharPtrLess> ConcreteCellMap;
typedef Map<string, ConcreteCell*> ConcreteCellMap;
typedef std::map<string, string> AttributeMap;
typedef Vector<ConcretePort*> ConcretePortSeq;
typedef Map<const char*, ConcretePort*, CharPtrLess> ConcretePortMap;
typedef Map<string, ConcretePort*> ConcretePortMap;
typedef ConcreteCellMap::ConstIterator ConcreteLibraryCellIterator;
typedef ConcretePortSeq::ConstIterator ConcreteCellPortIterator;
typedef ConcretePortSeq::ConstIterator ConcretePortMemberIterator;
@ -60,11 +60,11 @@ public:
const char *filename,
bool is_liberty);
virtual ~ConcreteLibrary();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
void setName(const char *name);
ObjectId id() const { return id_; }
bool isLiberty() const { return is_liberty_; }
const char *filename() const { return filename_; }
const char *filename() const { return filename_.c_str(); }
void addCell(ConcreteCell *cell);
ConcreteCell *makeCell(const char *name,
bool is_leaf,
@ -82,9 +82,9 @@ protected:
void renameCell(ConcreteCell *cell,
const char *cell_name);
const char *name_;
string name_;
ObjectId id_;
const char *filename_;
string filename_;
bool is_liberty_;
char bus_brkt_left_;
char bus_brkt_right_;
@ -99,9 +99,9 @@ class ConcreteCell
public:
// Use ConcreteLibrary::deleteCell.
virtual ~ConcreteCell();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
ObjectId id() const { return id_; }
const char *filename() const { return filename_; }
const char *filename() const { return filename_.c_str(); }
ConcreteLibrary *library() const { return library_; }
LibertyCell *libertyCell() const { return liberty_cell_; }
void setLibertyCell(LibertyCell *cell);
@ -156,10 +156,10 @@ protected:
const char *name,
int index);
const char *name_;
string name_;
ObjectId id_;
// Filename is optional.
const char *filename_;
string filename_;
ConcreteLibrary *library_;
LibertyCell *liberty_cell_;
// External application cell.
@ -181,7 +181,7 @@ class ConcretePort
{
public:
virtual ~ConcretePort();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
ObjectId id() const { return id_; }
const char *busName() const;
Cell *cell() const;
@ -236,7 +236,7 @@ protected:
ConcretePortSeq *member_ports,
ConcreteCell *cell);
const char *name_;
string name_;
ObjectId id_;
ConcreteCell *cell_;
PortDirection *direction_;

7
include/sta/Corner.hh
View File

@ -51,7 +51,7 @@ class Corners : public StaState
{
public:
explicit Corners(StaState *sta);
virtual ~Corners();
~Corners();
void clear();
int count() const;
void copy(Corners *corners);
@ -106,8 +106,7 @@ class Corner
public:
Corner(const char *name,
int index);
~Corner();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
int index() const { return index_; }
ParasiticAnalysisPt *findParasiticAnalysisPt(const MinMax *min_max) const;
int parasiticAnalysisPtcount();
@ -127,7 +126,7 @@ protected:
void addPathAP(PathAnalysisPt *path_ap);
private:
const char *name_;
string name_;
int index_;
ParasiticAnalysisPtSeq parasitic_analysis_pts_;
DcalcAnalysisPtSeq dcalc_analysis_pts_;

2
include/sta/CycleAccting.hh
View File

@ -95,7 +95,7 @@ private:
int tgt_cycle,
float delay,
float req);
void setAccting(TimingRole *role,
void setAccting(const TimingRole *role,
int src_cycle,
int tgt_cycle,
float delay,

2
include/sta/DataCheck.hh
View File

@ -56,7 +56,7 @@ public:
const RiseFallBoth *to_rf,
const SetupHoldAll *setup_hold);
bool empty() const;
void marginIsOneValue(SetupHold *setup_hold,
void marginIsOneValue(const SetupHold *setup_hold,
// Return values.
float &value,
bool &one_value) const;

12
include/sta/FuncExpr.hh
View File

@ -24,12 +24,16 @@
#pragma once
#include <string>
#include "Set.hh"
#include "NetworkClass.hh"
#include "LibertyClass.hh"
namespace sta {
using std::string;
class FuncExpr
{
public:
@ -75,7 +79,7 @@ public:
TimingSense portTimingSense(const LibertyPort *port) const;
// Return true if expression has port as an input.
bool hasPort(const LibertyPort *port) const;
const char *asString() const;
string to_string() const;
// Sub expression for a bus function (bit_offset is 0 to bus->size()-1).
FuncExpr *bitSubExpr(int bit_offset);
// Check to make sure the function and port size are compatible.
@ -84,9 +88,9 @@ public:
bool checkSize(LibertyPort *port);
private:
const char *asString(bool with_parens) const;
const char *asStringSubexpr(bool with_parens,
char op) const;
string to_string(bool with_parens) const;
string to_string(bool with_parens,
char op) const;
Operator op_;
FuncExpr *left_;

5
include/sta/Graph.hh
View File

@ -247,6 +247,8 @@ public:
~Vertex();
Pin *pin() const { return pin_; }
// Pin path with load/driver suffix for bidirects.
string to_string(const StaState *sta) const;
// compatibility
const char *name(const Network *network) const;
bool isBidirectDriver() const { return is_bidirect_drvr_; }
bool isDriver(const Network *network) const;
@ -364,11 +366,12 @@ class Edge
public:
Edge();
~Edge();
string to_string(const StaState *sta) const;
Vertex *to(const Graph *graph) const { return graph->vertex(to_); }
VertexId to() const { return to_; }
Vertex *from(const Graph *graph) const { return graph->vertex(from_); }
VertexId from() const { return from_; }
TimingRole *role() const;
const TimingRole *role() const;
bool isWire() const;
TimingSense sense() const;
TimingArcSet *timingArcSet() const { return arc_set_; }

6
include/sta/InternalPower.hh
View File

@ -40,9 +40,9 @@ public:
void deleteContents();
FuncExpr *when() const { return when_; }
FuncExpr *&whenRef() { return when_; }
void setModel(RiseFall *rf,
void setModel(const RiseFall *rf,
InternalPowerModel *model);
InternalPowerModel *model(RiseFall *rf) const;
InternalPowerModel *model(const RiseFall *rf) const;
const char *relatedPgPin() const { return related_pg_pin_; }
void setRelatedPgPin(const char *related_pg_pin);
@ -65,7 +65,7 @@ public:
LibertyPort *relatedPort() const { return related_port_; }
FuncExpr *when() const { return when_; }
const char *relatedPgPin() const { return related_pg_pin_; }
float power(RiseFall *rf,
float power(const RiseFall *rf,
const Pvt *pvt,
float in_slew,
float load_cap);

85
include/sta/Liberty.hh
View File

@ -88,9 +88,9 @@ typedef Map<const TimingArcSet*, LatchEnable*> LatchEnableMap;
typedef Vector<LatchEnable*> LatchEnableSeq;
typedef Map<const char *, OcvDerate*, CharPtrLess> OcvDerateMap;
typedef Vector<InternalPowerAttrs*> InternalPowerAttrsSeq;
typedef Map<const char *, float, CharPtrLess> SupplyVoltageMap;
typedef Map<const char *, LibertyPgPort*, CharPtrLess> LibertyPgPortMap;
typedef Map<const char *, DriverWaveform*, CharPtrLess> DriverWaveformMap;
typedef Map<string, float> SupplyVoltageMap;
typedef Map<string, LibertyPgPort*> LibertyPgPortMap;
typedef Map<string, DriverWaveform*> DriverWaveformMap;
typedef Vector<DcalcAnalysisPt*> DcalcAnalysisPtSeq;
enum class ClockGateType { none, latch_posedge, latch_negedge, other };
@ -135,7 +135,7 @@ scaleFactorTypeLowHighSuffix(ScaleFactorType type);
// Timing sense as a string.
const char *
timingSenseString(TimingSense sense);
to_string(TimingSense sense);
// Opposite timing sense.
TimingSense
@ -188,7 +188,7 @@ public:
const Pvt *pvt) const;
void setWireSlewDegradationTable(TableModel *model,
RiseFall *rf);
const RiseFall *rf);
TableModel *wireSlewDegradationTable(const RiseFall *rf) const;
float degradeWireSlew(const RiseFall *rf,
float in_slew,
@ -647,8 +647,8 @@ protected:
bool has_internal_ports_;
std::atomic<bool> have_voltage_waveforms_;
std::mutex waveform_lock_;
const char *footprint_;
const char *user_function_class_;
string footprint_;
string user_function_class_;
private:
friend class LibertyLibrary;
@ -809,11 +809,11 @@ public:
void setIsCheckClk(bool is_clk);
bool isPad() const { return is_pad_; }
void setIsPad(bool is_pad);
RiseFall *pulseClkTrigger() const { return pulse_clk_trigger_; }
const RiseFall *pulseClkTrigger() const { return pulse_clk_trigger_; }
// Rise for high, fall for low.
RiseFall *pulseClkSense() const { return pulse_clk_sense_; }
void setPulseClk(RiseFall *rfigger,
RiseFall *sense);
const RiseFall *pulseClkSense() const { return pulse_clk_sense_; }
void setPulseClk(const RiseFall *rfigger,
const RiseFall *sense);
bool isDisabledConstraint() const { return is_disabled_constraint_; }
void setIsDisabledConstraint(bool is_disabled);
LibertyPort *cornerPort(const Corner *corner,
@ -826,9 +826,9 @@ public:
const LibertyPort *cornerPort(int ap_index) const;
void setCornerPort(LibertyPort *corner_port,
int ap_index);
const char *relatedGroundPin() const { return related_ground_pin_; }
const char *relatedGroundPin() const;
void setRelatedGroundPin(const char *related_ground_pin);
const char *relatedPowerPin() const { return related_power_pin_; }
const char *relatedPowerPin() const;
void setRelatedPowerPin(const char *related_power_pin);
const ReceiverModel *receiverModel() const { return receiver_model_.get(); }
void setReceiverModel(ReceiverModelPtr receiver_model);
@ -886,10 +886,10 @@ protected:
MinMaxFloatValues fanout_limit_; // outputs
float min_period_;
float min_pulse_width_[RiseFall::index_count];
RiseFall *pulse_clk_trigger_;
RiseFall *pulse_clk_sense_;
const char *related_ground_pin_;
const char *related_power_pin_;
const RiseFall *pulse_clk_trigger_;
const RiseFall *pulse_clk_sense_;
string related_ground_pin_;
string related_power_pin_;
Vector<LibertyPort*> corner_ports_;
ReceiverModelPtr receiver_model_;
DriverWaveform *driver_waveform_[RiseFall::index_count];
@ -958,19 +958,18 @@ protected:
class OperatingConditions : public Pvt
{
public:
explicit OperatingConditions(const char *name);
OperatingConditions(const char *name);
OperatingConditions(const char *name,
float process,
float voltage,
float temperature,
WireloadTree wire_load_tree);
virtual ~OperatingConditions();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
WireloadTree wireloadTree() const { return wire_load_tree_; }
void setWireloadTree(WireloadTree tree);
protected:
const char *name_;
string name_;
WireloadTree wire_load_tree_;
};
@ -978,11 +977,10 @@ class ScaleFactors
{
public:
explicit ScaleFactors(const char *name);
~ScaleFactors();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
float scale(ScaleFactorType type,
ScaleFactorPvt pvt,
RiseFall *rf);
const RiseFall *rf);
float scale(ScaleFactorType type,
ScaleFactorPvt pvt,
int rf_index);
@ -990,7 +988,7 @@ public:
ScaleFactorPvt pvt);
void setScale(ScaleFactorType type,
ScaleFactorPvt pvt,
RiseFall *rf,
const RiseFall *rf,
float scale);
void setScale(ScaleFactorType type,
ScaleFactorPvt pvt,
@ -998,7 +996,7 @@ public:
void print();
protected:
const char *name_;
string name_;
float scales_[scale_factor_type_count][scale_factor_pvt_count][RiseFall::index_count];
};
@ -1008,13 +1006,12 @@ public:
BusDcl(const char *name,
int from,
int to);
~BusDcl();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
int from() const { return from_; }
int to() const { return to_; }
protected:
const char *name_;
string name_;
int from_;
int to_;
};
@ -1024,7 +1021,7 @@ class ModeDef
{
public:
~ModeDef();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
ModeValueDef *defineValue(const char *value,
FuncExpr *cond,
const char *sdf_cond);
@ -1033,9 +1030,9 @@ public:
protected:
// Private to LibertyCell::makeModeDef.
explicit ModeDef(const char *name);
ModeDef(const char *name);
const char *name_;
string name_;
ModeValueMap values_;
private:
@ -1047,10 +1044,10 @@ class ModeValueDef
{
public:
~ModeValueDef();
const char *value() const { return value_; }
const char *value() const { return value_.c_str(); }
FuncExpr *cond() const { return cond_; }
FuncExpr *&condRef() { return cond_; }
const char *sdfCond() const { return sdf_cond_; }
const char *sdfCond() const { return sdf_cond_.c_str(); }
void setSdfCond(const char *sdf_cond);
protected:
@ -1059,9 +1056,9 @@ protected:
FuncExpr *cond,
const char *sdf_cond);
const char *value_;
string value_;
FuncExpr *cond_;
const char *sdf_cond_;
string sdf_cond_;
private:
friend class ModeDef;
@ -1070,13 +1067,12 @@ private:
class TableTemplate
{
public:
explicit TableTemplate(const char *name);
TableTemplate(const char *name);
TableTemplate(const char *name,
TableAxisPtr axis1,
TableAxisPtr axis2,
TableAxisPtr axis3);
~TableTemplate();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
void setName(const char *name);
const TableAxis *axis1() const { return axis1_.get(); }
TableAxisPtr axis1ptr() const { return axis1_; }
@ -1089,7 +1085,7 @@ public:
void setAxis3(TableAxisPtr axis);
protected:
const char *name_;
string name_;
TableAxisPtr axis1_;
TableAxisPtr axis2_;
TableAxisPtr axis3_;
@ -1137,20 +1133,19 @@ public:
deepnwell, deeppwell};
LibertyPgPort(const char *name,
LibertyCell *cell);
~LibertyPgPort();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
LibertyCell *cell() const { return cell_; }
PgType pgType() const { return pg_type_; }
void setPgType(PgType type);
const char *voltageName() const { return voltage_name_; }
const char *voltageName() const { return voltage_name_.c_str(); }
void setVoltageName(const char *voltage_name);
static bool equiv(const LibertyPgPort *port1,
const LibertyPgPort *port2);
private:
const char *name_;
string name_;
PgType pg_type_;
const char *voltage_name_;
string voltage_name_;
LibertyCell *cell_;
};

62
include/sta/MinMax.hh
View File

@ -26,10 +26,14 @@
#include <array>
#include <vector>
#include <string>
#include "Iterator.hh"
namespace sta {
using std::string;
class MinMax;
class MinMaxAll;
@ -46,15 +50,15 @@ public:
static void init();
static void destroy();
// Singleton accessors.
static MinMax *min() { return &min_; }
static MinMax *max() { return &max_; }
static EarlyLate *early() { return &min_; }
static EarlyLate *late() { return &max_; }
static const MinMax *min() { return &min_; }
static const MinMax *max() { return &max_; }
static const EarlyLate *early() { return &min_; }
static const EarlyLate *late() { return &max_; }
static int minIndex() { return min_.index_; }
static int earlyIndex() { return min_.index_; }
static int maxIndex() { return max_.index_; }
static int lateIndex() { return max_.index_; }
const char *asString() const { return name_; }
const string &to_string() const { return name_; }
int index() const { return index_; }
float initValue() const { return init_value_; }
int initValueInt() const { return init_value_int_; }
@ -64,17 +68,17 @@ public:
// min/max(value1, value2)
float minMax(float value1,
float value2) const;
MinMaxAll *asMinMaxAll() const;
MinMax *opposite() const;
const MinMaxAll *asMinMaxAll() const;
const MinMax *opposite() const;
// for range support.
// for (auto min_max : MinMax::range()) {}
static const std::array<MinMax*, 2> &range() { return range_; }
static const std::array<const MinMax*, 2> &range() { return range_; }
// for (auto mm_index : MinMax::rangeIndex()) {}
static const std::array<int, 2> &rangeIndex() { return range_index_; }
// Find MinMax from name.
static MinMax *find(const char *min_max);
static const MinMax *find(const char *min_max);
// Find MinMax from index.
static MinMax *find(int index);
static const MinMax *find(int index);
static const int index_max = 1;
static const int index_count = 2;
static const int index_bit_count = 1;
@ -87,16 +91,16 @@ private:
bool (*compare)(float value1,
float value2));
const char *name_;
const string name_;
int index_;
float init_value_;
int init_value_int_;
bool (*compare_)(float value1,
float value2);
static MinMax min_;
static MinMax max_;
static const std::array<MinMax*, 2> range_;
static const MinMax min_;
static const MinMax max_;
static const std::array<const MinMax*, 2> range_;
static const std::array<int, 2> range_index_;
};
@ -105,36 +109,36 @@ class MinMaxAll
{
public:
// Singleton accessors.
static MinMaxAll *min() { return &min_; }
static MinMaxAll *early() { return &min_; }
static MinMaxAll *max() { return &max_; }
static MinMaxAll *late() { return &max_; }
static MinMaxAll *all() { return &all_; }
const char *asString() const { return name_; }
static const MinMaxAll *min() { return &min_; }
static const MinMaxAll *early() { return &min_; }
static const MinMaxAll *max() { return &max_; }
static const MinMaxAll *late() { return &max_; }
static const MinMaxAll *all() { return &all_; }
const string &to_string() const { return name_; }
int index() const { return index_; }
MinMax *asMinMax() const;
const MinMax *asMinMax() const;
bool matches(const MinMax *min_max) const;
bool matches(const MinMaxAll *min_max) const;
static MinMaxAll *find(const char *min_max);
static const MinMaxAll *find(const char *min_max);
// for (const auto min_max : min_max->range()) {}
const std::vector<MinMax*> &range() const { return range_; }
const std::vector<const MinMax*> &range() const { return range_; }
// for (const auto mm_index : min_max->rangeIndex()) {}
const std::vector<int> &rangeIndex() const { return range_index_; }
private:
MinMaxAll(const char *name,
int index,
std::vector<MinMax*> range,
std::vector<const MinMax*> range,
std::vector<int> range_index);
const char *name_;
const string name_;
int index_;
const std::vector<MinMax*> range_;
const std::vector<const MinMax*> range_;
const std::vector<int> range_index_;
static MinMaxAll min_;
static MinMaxAll max_;
static MinMaxAll all_;
static const MinMaxAll min_;
static const MinMaxAll max_;
static const MinMaxAll all_;
};
} // namespace

2
include/sta/Path.hh
View File

@ -61,7 +61,7 @@ public:
bool is_enum,
const StaState *sta);
~Path();
const char *name(const StaState *sta) const;
string to_string(const StaState *sta) const;
bool isNull() const;
// prev_path null
void init(Vertex *vertex,

5
include/sta/PathAnalysisPt.hh
View File

@ -24,6 +24,8 @@
#pragma once
#include <string>
#include "Iterator.hh"
#include "MinMax.hh"
#include "SdcClass.hh"
@ -35,6 +37,8 @@ class MinMax;
class DcalcAnalysisPt;
class Corner;
using std::string;
class PathAnalysisPt
{
public:
@ -42,6 +46,7 @@ public:
PathAPIndex index,
const MinMax *path_min_max,
DcalcAnalysisPt *dcalc_ap);
string to_string() const;
Corner *corner() const { return corner_; }
PathAPIndex index() const { return index_; }
const MinMax *pathMinMax() const { return path_min_max_; }

20
include/sta/PathEnd.hh
View File

@ -137,7 +137,7 @@ public:
// Target clock uncertainty + inter-clk uncertainty.
virtual float targetClkUncertainty(const StaState *sta) const;
virtual float targetClkMcpAdjustment(const StaState *sta) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual const TimingRole *checkRole(const StaState *sta) const;
const TimingRole *checkGenericRole(const StaState *sta) const;
virtual bool pathDelayMarginIsExternal() const;
virtual PathDelay *pathDelay() const;
@ -331,7 +331,7 @@ public:
virtual bool isCheck() const { return true; }
virtual ArcDelay margin(const StaState *sta) const;
virtual float macroClkTreeDelay(const StaState *sta) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual const TimingRole *checkRole(const StaState *sta) const;
virtual TimingArc *checkArc() const { return check_arc_; }
virtual int exceptPathCmp(const PathEnd *path_end,
const StaState *sta) const;
@ -374,7 +374,7 @@ public:
const Path *latchDisable() const;
virtual void reportShort(const ReportPath *report) const;
virtual void reportFull(const ReportPath *report) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual const TimingRole *checkRole(const StaState *sta) const;
virtual Required requiredTime(const StaState *sta) const;
virtual Arrival borrow(const StaState *sta) const;
Arrival targetClkWidth(const StaState *sta) const;
@ -435,7 +435,7 @@ public:
virtual void reportFull(const ReportPath *report) const;
virtual bool isOutputDelay() const { return true; }
virtual ArcDelay margin(const StaState *sta) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual const TimingRole *checkRole(const StaState *sta) const;
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
virtual Arrival targetClkArrivalNoCrpr(const StaState *sta) const;
virtual Delay targetClkDelay(const StaState *sta) const;
@ -470,7 +470,7 @@ class PathEndGatedClock : public PathEndClkConstrainedMcp
public:
PathEndGatedClock(Path *gating_ref,
Path *clk_path,
TimingRole *check_role,
const TimingRole *check_role,
MultiCyclePath *mcp,
ArcDelay margin,
const StaState *sta);
@ -481,20 +481,20 @@ public:
virtual void reportFull(const ReportPath *report) const;
virtual bool isGatedClock() const { return true; }
virtual ArcDelay margin(const StaState *) const { return margin_; }
virtual TimingRole *checkRole(const StaState *sta) const;
virtual const TimingRole *checkRole(const StaState *sta) const;
virtual int exceptPathCmp(const PathEnd *path_end,
const StaState *sta) const;
protected:
PathEndGatedClock(Path *gating_ref,
Path *clk_path,
TimingRole *check_role,
const TimingRole *check_role,
MultiCyclePath *mcp,
ArcDelay margin,
Crpr crpr,
bool crpr_valid);
TimingRole *check_role_;
const TimingRole *check_role_;
ArcDelay margin_;
};
@ -513,7 +513,7 @@ public:
virtual void reportFull(const ReportPath *report) const;
virtual bool isDataCheck() const { return true; }
virtual const ClockEdge *targetClkEdge(const StaState *sta) const;
virtual TimingRole *checkRole(const StaState *sta) const;
virtual const TimingRole *checkRole(const StaState *sta) const;
virtual ArcDelay margin(const StaState *sta) const;
virtual int exceptPathCmp(const PathEnd *path_end,
const StaState *sta) const;
@ -566,7 +566,7 @@ public:
virtual void reportShort(const ReportPath *report) const;
virtual void reportFull(const ReportPath *report) const;
virtual bool isPathDelay() const { return true; }
virtual TimingRole *checkRole(const StaState *sta) const;
virtual const TimingRole *checkRole(const StaState *sta) const;
virtual bool pathDelayMarginIsExternal() const;
virtual PathDelay *pathDelay() const { return path_delay_; }
virtual ArcDelay margin(const StaState *sta) const;

2
include/sta/PortDelay.hh
View File

@ -48,7 +48,7 @@ public:
void setNetworkLatencyIncluded(bool included);
const Pin *refPin() const { return ref_pin_; }
void setRefPin(const Pin *ref_pin);
RiseFall *refTransition() const;
const RiseFall *refTransition() const;
protected:
PortDelay(const Pin *pin,

2
include/sta/StringUtil.hh
View File

@ -190,6 +190,8 @@ stringPrintTmp(const char *fmt,
char *
makeTmpString(size_t length);
char *
makeTmpString(string &str);
bool
isTmpString(const char *str);

9
include/sta/TableModel.hh
View File

@ -483,7 +483,7 @@ public:
~ReceiverModel();
void setCapacitanceModel(TableModel *table_model,
size_t segment,
RiseFall *rf);
const RiseFall *rf);
static bool checkAxes(TablePtr table);
private:
@ -576,14 +576,13 @@ private:
class DriverWaveform
{
public:
DriverWaveform(const char *name,
DriverWaveform(const string &name,
TablePtr waveforms);
~DriverWaveform();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
Table1 waveform(float slew);
private:
const char *name_;
string name_;
TablePtr waveforms_;
};

26
include/sta/TimingArc.hh
View File

@ -83,7 +83,7 @@ enum class TimingType {
};
const char *
timingTypeString(TimingType type);
to_string(TimingType type);
TimingType
findTimingType(const char *string);
bool
@ -146,7 +146,7 @@ public:
LibertyPort *from,
LibertyPort *to,
LibertyPort *related_out,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs);
virtual ~TimingArcSet();
LibertyCell *libertyCell() const;
@ -154,7 +154,7 @@ public:
LibertyPort *to() const { return to_; }
bool isWire() const;
LibertyPort *relatedOut() const { return related_out_; }
TimingRole *role() const { return role_; };
const TimingRole *role() const { return role_; };
TimingSense sense() const;
// Rise/fall if the arc set is rising_edge or falling_edge.
const RiseFall *isRisingFallingEdge() const;
@ -170,7 +170,7 @@ public:
TimingArcIndex addTimingArc(TimingArc *arc);
void deleteTimingArc(TimingArc *arc);
TimingArc *findTimingArc(unsigned arc_index);
void setRole(TimingRole *role);
void setRole(const TimingRole *role);
FuncExpr *cond() const { return attrs_->cond(); }
// Cond default is the timing arcs with no condition when there are
// other conditional timing arcs between the same pins.
@ -205,13 +205,13 @@ public:
static int wireArcCount() { return 2; }
protected:
TimingArcSet(TimingRole *role,
TimingArcSet(const TimingRole *role,
TimingArcAttrsPtr attrs);
LibertyPort *from_;
LibertyPort *to_;
LibertyPort *related_out_;
TimingRole *role_;
const TimingRole *role_;
// TimingArcAttrs are shared by TimingArcSets in a bus with timing groups.
TimingArcAttrsPtr attrs_;
TimingArcSeq arcs_;
@ -232,15 +232,15 @@ class TimingArc
{
public:
TimingArc(TimingArcSet *set,
Transition *from_rf,
Transition *to_rf,
const Transition *from_rf,
const Transition *to_rf,
TimingModel *model);
~TimingArc();
LibertyPort *from() const { return set_->from(); }
LibertyPort *to() const { return set_->to(); }
Transition *fromEdge() const { return from_rf_; }
Transition *toEdge() const { return to_rf_; }
TimingRole *role() const { return set_->role(); }
const Transition *fromEdge() const { return from_rf_; }
const Transition *toEdge() const { return to_rf_; }
const TimingRole *role() const { return set_->role(); }
TimingArcSet *set() const { return set_; }
TimingSense sense() const;
// Index in TimingArcSet.
@ -266,8 +266,8 @@ protected:
TimingModel *scaled_model);
TimingArcSet *set_;
Transition *from_rf_;
Transition *to_rf_;
const Transition *from_rf_;
const Transition *to_rf_;
unsigned index_;
TimingModel *model_;
ScaledTimingModelMap *scaled_models_;

139
include/sta/TimingRole.hh
View File

@ -24,52 +24,51 @@
#pragma once
#include <map>
#include "MinMax.hh"
#include "Map.hh"
#include "StringUtil.hh"
namespace sta {
class TimingRole;
typedef Map<const char*, TimingRole*, CharPtrLess> TimingRoleMap;
typedef std::map<string, const TimingRole*> TimingRoleMap;
class TimingRole
{
public:
static void init();
static void destroy();
static TimingRole *find(const char *name);
static const TimingRole *find(const char *name);
// Singleton accessors.
static TimingRole *wire() { return wire_; }
static TimingRole *combinational() { return combinational_; }
static TimingRole *tristateEnable() { return tristate_enable_; }
static TimingRole *tristateDisable() { return tristate_disable_; }
static TimingRole *regClkToQ() { return reg_clk_q_; }
static TimingRole *regSetClr() { return reg_set_clr_; }
static TimingRole *latchEnToQ() { return latch_en_q_; }
static TimingRole *latchDtoQ() { return latch_d_q_; }
static TimingRole *setup() { return setup_; }
static TimingRole *hold() { return hold_; }
static TimingRole *recovery() { return recovery_; }
static TimingRole *removal() { return removal_; }
static TimingRole *width() { return width_; }
static TimingRole *period() { return period_; }
static TimingRole *skew() { return skew_; }
static TimingRole *nochange() { return nochange_; }
static TimingRole *outputSetup() { return output_setup_; }
static TimingRole *outputHold() { return output_hold_; }
static TimingRole *gatedClockSetup() { return gated_clk_setup_; }
static TimingRole *gatedClockHold() { return gated_clk_hold_; }
static TimingRole *latchSetup() { return latch_setup_; }
static TimingRole *latchHold() { return latch_hold_; }
static TimingRole *dataCheckSetup() { return data_check_setup_; }
static TimingRole *dataCheckHold() { return data_check_hold_; }
static TimingRole *nonSeqSetup() { return non_seq_setup_; }
static TimingRole *nonSeqHold() { return non_seq_hold_; }
static TimingRole *clockTreePathMin() { return clock_tree_path_min_; }
static TimingRole *clockTreePathMax() { return clock_tree_path_max_; }
const char *asString() const { return name_; }
static const TimingRole *wire() { return &wire_; }
static const TimingRole *combinational() { return &combinational_; }
static const TimingRole *tristateEnable() { return &tristate_enable_; }
static const TimingRole *tristateDisable() { return &tristate_disable_; }
static const TimingRole *regClkToQ() { return &reg_clk_q_; }
static const TimingRole *regSetClr() { return &reg_set_clr_; }
static const TimingRole *latchEnToQ() { return &latch_en_q_; }
static const TimingRole *latchDtoQ() { return &latch_d_q_; }
static const TimingRole *setup() { return &setup_; }
static const TimingRole *hold() { return &hold_; }
static const TimingRole *recovery() { return &recovery_; }
static const TimingRole *removal() { return &removal_; }
static const TimingRole *width() { return &width_; }
static const TimingRole *period() { return &period_; }
static const TimingRole *skew() { return &skew_; }
static const TimingRole *nochange() { return &nochange_; }
static const TimingRole *outputSetup() { return &output_setup_; }
static const TimingRole *outputHold() { return &output_hold_; }
static const TimingRole *gatedClockSetup() { return &gated_clk_setup_; }
static const TimingRole *gatedClockHold() { return &gated_clk_hold_; }
static const TimingRole *latchSetup() { return &latch_setup_; }
static const TimingRole *latchHold() { return &latch_hold_; }
static const TimingRole *dataCheckSetup() { return &data_check_setup_; }
static const TimingRole *dataCheckHold() { return &data_check_hold_; }
static const TimingRole *nonSeqSetup() { return &non_seq_setup_; }
static const TimingRole *nonSeqHold() { return &non_seq_hold_; }
static const TimingRole *clockTreePathMin() { return &clock_tree_path_min_; }
static const TimingRole *clockTreePathMax() { return &clock_tree_path_max_; }
const string &to_string() const { return name_; }
int index() const { return index_; }
bool isWire() const;
bool isTimingCheck() const { return is_timing_check_; }
@ -82,12 +81,12 @@ public:
const TimingRole *genericRole() const;
const TimingRole *sdfRole() const;
// Timing check data path min/max.
MinMax *pathMinMax() const { return path_min_max_; }
const MinMax *pathMinMax() const { return path_min_max_; }
// Timing check target clock path insertion delay early/late.
const EarlyLate *tgtClkEarlyLate() const;
// Pseudo role to match sdf IOPATH.
static TimingRole *sdfIopath() { return sdf_iopath_; }
static const TimingRole *sdfIopath() { return &sdf_iopath_; }
static bool less(const TimingRole *role1,
const TimingRole *role2);
static const int index_max = 26;
@ -97,48 +96,48 @@ private:
bool is_sdf_iopath,
bool is_timing_check,
bool is_non_seq_check,
MinMax *path_min_max,
const MinMax *path_min_max,
// generic_type = nullptr means type is the same as this.
TimingRole *generic_role,
const TimingRole *generic_role,
int index);
const char *name_;
const string name_;
bool is_timing_check_;
bool is_sdf_iopath_;
bool is_non_seq_check_;
TimingRole *generic_role_;
const TimingRole *generic_role_;
unsigned index_;
MinMax *path_min_max_;
const MinMax *path_min_max_;
static TimingRole *wire_;
static TimingRole *combinational_;
static TimingRole *tristate_enable_;
static TimingRole *tristate_disable_;
static TimingRole *reg_clk_q_;
static TimingRole *reg_set_clr_;
static TimingRole *latch_en_q_;
static TimingRole *latch_d_q_;
static TimingRole *setup_;
static TimingRole *hold_;
static TimingRole *recovery_;
static TimingRole *removal_;
static TimingRole *width_;
static TimingRole *period_;
static TimingRole *skew_;
static TimingRole *nochange_;
static TimingRole *sdf_iopath_;
static TimingRole *output_setup_;
static TimingRole *output_hold_;
static TimingRole *gated_clk_setup_;
static TimingRole *gated_clk_hold_;
static TimingRole *latch_setup_;
static TimingRole *latch_hold_;
static TimingRole *data_check_setup_;
static TimingRole *data_check_hold_;
static TimingRole *non_seq_setup_;
static TimingRole *non_seq_hold_;
static TimingRole *clock_tree_path_min_;
static TimingRole *clock_tree_path_max_;
static const TimingRole wire_;
static const TimingRole combinational_;
static const TimingRole tristate_enable_;
static const TimingRole tristate_disable_;
static const TimingRole reg_clk_q_;
static const TimingRole reg_set_clr_;
static const TimingRole latch_en_q_;
static const TimingRole latch_d_q_;
static const TimingRole setup_;
static const TimingRole hold_;
static const TimingRole recovery_;
static const TimingRole removal_;
static const TimingRole width_;
static const TimingRole period_;
static const TimingRole skew_;
static const TimingRole nochange_;
static const TimingRole sdf_iopath_;
static const TimingRole output_setup_;
static const TimingRole output_hold_;
static const TimingRole gated_clk_setup_;
static const TimingRole gated_clk_hold_;
static const TimingRole latch_setup_;
static const TimingRole latch_hold_;
static const TimingRole data_check_setup_;
static const TimingRole data_check_hold_;
static const TimingRole non_seq_setup_;
static const TimingRole non_seq_hold_;
static const TimingRole clock_tree_path_min_;
static const TimingRole clock_tree_path_max_;
static TimingRoleMap timing_roles_;
friend class TimingRoleLess;

156
include/sta/Transition.hh
View File

@ -37,34 +37,33 @@ class Transition;
class RiseFall;
class RiseFallBoth;
typedef Map<const char*, Transition*, CharPtrLess> TransitionMap;
typedef Map<const string, const Transition*> TransitionMap;
// Rise/fall transition.
class RiseFall
{
public:
// Singleton accessors.
static RiseFall *rise() { return &rise_; }
static RiseFall *fall() { return &fall_; }
static const RiseFall *rise() { return &rise_; }
static const RiseFall *fall() { return &fall_; }
static int riseIndex() { return rise_.sdf_triple_index_; }
static int fallIndex() { return fall_.sdf_triple_index_; }
const char *asString() const { return short_name_; }
const char *name() const { return name_; }
const char *shortName() const { return short_name_; }
void setShortName(const char *short_name);
const string &to_string() const { return short_name_; }
const char *name() const { return name_.c_str(); }
const char *shortName() const { return short_name_.c_str(); }
int index() const { return sdf_triple_index_; }
RiseFallBoth *asRiseFallBoth();
const RiseFallBoth *asRiseFallBoth();
const RiseFallBoth *asRiseFallBoth() const;
Transition *asTransition() const;
// Find transition corresponding to tr_str.
static RiseFall *find(const char *tr_str);
const Transition *asTransition() const;
// Find transition corresponding to rf_str.
static const RiseFall *find(const char *rf_str);
// Find transition from index.
static RiseFall *find(int index);
RiseFall *opposite() const;
static const RiseFall *find(int index);
const RiseFall *opposite() const;
// for range support.
// for (auto rf : RiseFall::range()) {}
static const std::array<RiseFall*, 2> &range() { return range_; }
static const std::array<const RiseFall*, 2> &range() { return range_; }
// for (auto rf_index : RiseFall::rangeIndex()) {}
static const std::array<int, 2> &rangeIndex() { return range_index_; }
static const int index_count = 2;
@ -73,17 +72,16 @@ public:
protected:
RiseFall(const char *name,
const char *short_name,
int sdf_triple_index);
~RiseFall();
const char *short_name,
int sdf_triple_index);
const char *name_;
const char *short_name_;
const string name_;
const string short_name_;
const int sdf_triple_index_;
static RiseFall rise_;
static RiseFall fall_;
static const std::array<RiseFall*, 2> range_;
static const RiseFall rise_;
static const RiseFall fall_;
static const std::array<const RiseFall*, 2> range_;
static const std::array<int, 2> range_index_;
};
@ -92,21 +90,20 @@ class RiseFallBoth
{
public:
// Singleton accessors.
static RiseFallBoth *rise() { return &rise_; }
static RiseFallBoth *fall() { return &fall_; }
static RiseFallBoth *riseFall() { return &rise_fall_; }
const char *asString() const { return short_name_; }
const char *name() const { return name_; }
const char *shortName() const { return short_name_; }
void setShortName(const char *short_name);
static const RiseFallBoth *rise() { return &rise_; }
static const RiseFallBoth *fall() { return &fall_; }
static const RiseFallBoth *riseFall() { return &rise_fall_; }
const string &to_string() const { return short_name_; }
const char *name() const { return name_.c_str(); }
const char *shortName() const { return short_name_.c_str(); }
int index() const { return sdf_triple_index_; }
bool matches(const RiseFall *rf) const;
bool matches(const Transition *tr) const;
RiseFall *asRiseFall() const { return as_rise_fall_; }
const RiseFall *asRiseFall() const { return as_rise_fall_; }
// Find transition corresponding to string.
static RiseFallBoth *find(const char *tr_str);
static const RiseFallBoth *find(const char *tr_str);
// for (const auto rf : rf->range()) {}
const std::vector<RiseFall*> &range() const { return range_; }
const std::vector<const RiseFall*> &range() const { return range_; }
// for (const auto rf_index : rf->rangeIndex()) {}
const std::vector<int> &rangeIndex() const { return range_index_; }
@ -116,23 +113,22 @@ public:
protected:
RiseFallBoth(const char *name,
const char *short_name,
int sdf_triple_index,
RiseFall *as_rise_fall,
std::vector<RiseFall*> range,
std::vector<int> range_index);
~RiseFallBoth();
const char *short_name,
int sdf_triple_index,
const RiseFall *as_rise_fall,
std::vector<const RiseFall*> range,
std::vector<int> range_index);
const char *name_;
const char *short_name_;
const string name_;
const string short_name_;
const int sdf_triple_index_;
RiseFall *as_rise_fall_;
const std::vector<RiseFall*> range_;
const RiseFall *as_rise_fall_;
const std::vector<const RiseFall*> range_;
const std::vector<int> range_index_;
static RiseFallBoth rise_;
static RiseFallBoth fall_;
static RiseFallBoth rise_fall_;
static const RiseFallBoth rise_;
static const RiseFallBoth fall_;
static const RiseFallBoth rise_fall_;
};
// General SDF transition.
@ -140,58 +136,56 @@ class Transition
{
public:
// Singleton accessors.
static Transition *rise() { return &rise_; }
static Transition *fall() { return &fall_; }
static Transition *tr0Z() { return &tr_0Z_; }
static Transition *trZ1() { return &tr_Z1_; }
static Transition *tr1Z() { return &tr_1Z_; }
static Transition *trZ0() { return &tr_Z0_; }
static Transition *tr0X() { return &tr_0X_; }
static Transition *trX1() { return &tr_X1_; }
static Transition *tr1X() { return &tr_1X_; }
static Transition *trX0() { return &tr_X0_; }
static Transition *trXZ() { return &tr_XZ_; }
static Transition *trZX() { return &tr_ZX_; }
void setName(const char *name);
static const Transition *rise() { return &rise_; }
static const Transition *fall() { return &fall_; }
static const Transition *tr0Z() { return &tr_0Z_; }
static const Transition *trZ1() { return &tr_Z1_; }
static const Transition *tr1Z() { return &tr_1Z_; }
static const Transition *trZ0() { return &tr_Z0_; }
static const Transition *tr0X() { return &tr_0X_; }
static const Transition *trX1() { return &tr_X1_; }
static const Transition *tr1X() { return &tr_1X_; }
static const Transition *trX0() { return &tr_X0_; }
static const Transition *trXZ() { return &tr_XZ_; }
static const Transition *trZX() { return &tr_ZX_; }
// Matches rise and fall.
static Transition *riseFall() { return &rise_fall_; }
const char *asString() const { return name_; }
static const Transition *riseFall() { return &rise_fall_; }
const string &to_string() const { return name_; }
// As initial/final value pair.
const char *asInitFinalString() const { return init_final_; }
const char *asInitFinalString() const { return init_final_.c_str(); }
int sdfTripleIndex() const { return sdf_triple_index_; }
int index() const { return sdf_triple_index_; }
RiseFall *asRiseFall() const { return as_rise_fall_; }
const RiseFall *asRiseFall() const { return as_rise_fall_; }
const RiseFallBoth *asRiseFallBoth() const;
bool matches(const Transition *tr) const;
// Find transition corresponding to string.
static Transition *find(const char *tr_str);
static const Transition *find(const char *tr_str);
static int maxIndex() { return max_index_; }
private:
Transition(const char *name,
const char *init_final,
RiseFall *as_rise_fall,
const RiseFall *as_rise_fall,
int sdf_triple_index);
~Transition();
const char *name_;
const char *init_final_;
RiseFall *as_rise_fall_;
const string name_;
const string init_final_;
const RiseFall *as_rise_fall_;
const int sdf_triple_index_;
static Transition rise_;
static Transition fall_;
static Transition tr_0Z_;
static Transition tr_Z1_;
static Transition tr_1Z_;
static Transition tr_Z0_;
static Transition tr_0X_;
static Transition tr_X1_;
static Transition tr_1X_;
static Transition tr_X0_;
static Transition tr_XZ_;
static Transition tr_ZX_;
static Transition rise_fall_;
static const Transition rise_;
static const Transition fall_;
static const Transition tr_0Z_;
static const Transition tr_Z1_;
static const Transition tr_1Z_;
static const Transition tr_Z0_;
static const Transition tr_0X_;
static const Transition tr_X1_;
static const Transition tr_1X_;
static const Transition tr_X0_;
static const Transition tr_XZ_;
static const Transition tr_ZX_;
static const Transition rise_fall_;
static const int index_count = 13;
static const int index_max = (index_count - 1);
static const int index_bit_count = 4;

2
include/sta/VisitPathEnds.hh
View File

@ -118,7 +118,7 @@ protected:
const PathAnalysisPt *clk_ap,
const Pin *from_pin,
Vertex *from_vertex,
RiseFall *from_rf,
const RiseFall *from_rf,
bool filtered,
PathEndVisitor *visitor,
bool &is_constrained);

51
liberty/FuncExpr.cc
View File

@ -193,34 +193,29 @@ FuncExpr::portTimingSense(const LibertyPort *port) const
return TimingSense::unknown;
}
const char *
FuncExpr::asString() const
string
FuncExpr::to_string() const
{
return asString(false);
return to_string(false);
}
const char *
FuncExpr::asString(bool with_parens) const
string
FuncExpr::to_string(bool with_parens) const
{
switch (op_) {
case op_port:
return port_->name();
case op_not: {
const char *left = left_->asString(true);
size_t left_length = strlen(left);
size_t length = left_length + 2;
char *result = makeTmpString(length);
char *ptr = result;
*ptr++ = '!';
strcpy(ptr, left);
string result = "!";
result += left_->to_string(true);
return result;
}
case op_or:
return asStringSubexpr(with_parens, '+');
return to_string(with_parens, '+');
case op_and:
return asStringSubexpr(with_parens, '*');
return to_string(with_parens, '*');
case op_xor:
return asStringSubexpr(with_parens, '^');
return to_string(with_parens, '^');
case op_one:
return "1";
case op_zero:
@ -230,25 +225,19 @@ FuncExpr::asString(bool with_parens) const
}
}
const char *
FuncExpr::asStringSubexpr(bool with_parens,
char op) const
string
FuncExpr::to_string(bool with_parens,
char op) const
{
const char *left = left_->asString(true);
const char *right = right_->asString(true);
size_t length = strlen(left) + 1 + strlen(right) + 1;
string right = right_->to_string(true);
string result;
if (with_parens)
length += 2;
char *result = makeTmpString(length);
char *r = result;
result += '(';
result += left_->to_string(true);
result += op;
result += right_->to_string(true);
if (with_parens)
*r++= '(';
stringAppend(r, left);
*r++ = op;
stringAppend(r, right);
if (with_parens)
*r++ = ')';
*r = '\0';
result += ')';
return result;
}

12
liberty/InternalPower.cc
View File

@ -56,13 +56,13 @@ InternalPowerAttrs::deleteContents()
}
InternalPowerModel *
InternalPowerAttrs::model(RiseFall *rf) const
InternalPowerAttrs::model(const RiseFall *rf) const
{
return models_[rf->index()];
}
void
InternalPowerAttrs::setModel(RiseFall *rf,
InternalPowerAttrs::setModel(const RiseFall *rf,
InternalPowerModel *model)
{
models_[rf->index()] = model;
@ -86,9 +86,9 @@ InternalPower::InternalPower(LibertyCell *cell,
when_(attrs->when()),
related_pg_pin_(attrs->relatedPgPin())
{
for (auto tr : RiseFall::range()) {
int tr_index = tr->index();
models_[tr_index] = attrs->model(tr);
for (auto rf : RiseFall::range()) {
int rf_index = rf->index();
models_[rf_index] = attrs->model(rf);
}
cell->addInternalPower(this);
}
@ -105,7 +105,7 @@ InternalPower::libertyCell() const
}
float
InternalPower::power(RiseFall *rf,
InternalPower::power(const RiseFall *rf,
const Pvt *pvt,
float in_slew,
float load_cap)

152
liberty/Liberty.cc
View File

@ -130,8 +130,6 @@ LibertyLibrary::~LibertyLibrary()
delete units_;
ocv_derate_map_.deleteContents();
for (auto [supply_name, volt] : supply_voltage_map_)
stringDelete(supply_name);
delete buffers_;
delete inverters_;
driver_waveform_map_.deleteContents();
@ -325,7 +323,7 @@ LibertyLibrary::scaleFactor(ScaleFactorType type,
void
LibertyLibrary::setWireSlewDegradationTable(TableModel *model,
RiseFall *rf)
const RiseFall *rf)
{
int rf_index = rf->index();
if (wire_slew_degradation_tbls_[rf_index])
@ -799,7 +797,7 @@ LibertyLibrary::makeCornerMap(LibertyCell *cell1,
cell1->name(),
arc_set1->from() ? arc_set1->from()->name() : "",
arc_set1->to()->name(),
arc_set1->role()->asString(),
arc_set1->role()->to_string().c_str(),
cell2->library()->name(),
cell2->name());
}
@ -817,7 +815,7 @@ LibertyLibrary::checkCorners(LibertyCell *cell,
cell->libertyLibrary()->name(),
cell->name(),
corner->name(),
min_max->asString());
min_max->to_string().c_str());
}
}
}
@ -864,7 +862,7 @@ void
LibertyLibrary::addSupplyVoltage(const char *supply_name,
float voltage)
{
supply_voltage_map_[stringCopy(supply_name)] = voltage;
supply_voltage_map_[supply_name] = voltage;
}
void
@ -948,9 +946,7 @@ LibertyCell::LibertyCell(LibertyLibrary *library,
leakage_power_(0.0),
leakage_power_exists_(false),
has_internal_ports_(false),
have_voltage_waveforms_(false),
footprint_(nullptr),
user_function_class_(nullptr)
have_voltage_waveforms_(false)
{
liberty_cell_ = this;
}
@ -978,9 +974,6 @@ LibertyCell::~LibertyCell()
ocv_derate_map_.deleteContents();
pg_port_map_.deleteContents();
stringDelete(footprint_);
stringDelete(user_function_class_);
}
LibertyPort *
@ -1248,7 +1241,7 @@ LibertyCell::addTimingArcSet(TimingArcSet *arc_set)
timing_arc_sets_.push_back(arc_set);
LibertyPort *from = arc_set->from();
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (role == TimingRole::regClkToQ()
|| role == TimingRole::latchEnToQ())
from->setIsRegClk(true);
@ -1772,7 +1765,7 @@ LibertyCell::makeLatchEnables(Report *report,
&& en_rf != RiseFall::rise())
report->warn(1114, "cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function positive sense.",
library_->name(),
name_,
name(),
en->name(),
q->name(),
en_rf == RiseFall::rise()?"rising":"falling");
@ -1780,7 +1773,7 @@ LibertyCell::makeLatchEnables(Report *report,
&& en_rf != RiseFall::fall())
report->warn(1115, "cell %s/%s %s -> %s latch enable %s_edge is inconsistent with latch group enable function negative sense.",
library_->name(),
name_,
name(),
en->name(),
q->name(),
en_rf == RiseFall::rise()?"rising":"falling");
@ -1831,7 +1824,7 @@ LibertyCell::findLatchSetup(const LibertyPort *d,
if (from_rf == en_rf) {
report->warn(1113, "cell %s/%s %s -> %s latch enable %s_edge is inconsistent with %s -> %s setup_%s check.",
library_->name(),
name_,
name(),
en->name(),
q->name(),
en_rf == RiseFall::rise() ? "rising" : "falling",
@ -1913,7 +1906,7 @@ LibertyCell::inferLatchRoles(Report *report,
LibertyPort *q = en_to_q->to();
for (TimingArcSet *d_to_q : timingArcSets(nullptr, q)) {
// Look for combinational d->q arcs.
TimingRole *d_to_q_role = d_to_q->role();
const TimingRole *d_to_q_role = d_to_q->role();
if (((d_to_q_role == TimingRole::combinational()
&& d_to_q->arcCount() == 2
&& (d_to_q->sense() == TimingSense::positive_unate
@ -2002,28 +1995,35 @@ LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps)
}
}
const char *
LibertyCell::footprint() const
{
if (footprint_.empty())
return nullptr;
else
return footprint_.c_str();
}
void
LibertyCell::setFootprint(const char *footprint)
{
footprint_ = stringCopy(footprint);
footprint_ = footprint;
}
const char*
LibertyCell::footprint() const
const char *
LibertyCell::userFunctionClass() const
{
return footprint_;
if (user_function_class_.empty())
return nullptr;
else
return user_function_class_.c_str();
}
void
LibertyCell::setUserFunctionClass(const char *user_function_class)
{
user_function_class_ = stringCopy(user_function_class);
}
const char*
LibertyCell::userFunctionClass() const
{
return user_function_class_;
user_function_class_ = user_function_class;
}
////////////////////////////////////////////////////////////////
@ -2091,8 +2091,6 @@ LibertyPort::LibertyPort(LibertyCell *cell,
min_period_(0.0),
pulse_clk_trigger_(nullptr),
pulse_clk_sense_(nullptr),
related_ground_pin_(nullptr),
related_power_pin_(nullptr),
receiver_model_(nullptr),
driver_waveform_{nullptr, nullptr},
min_pulse_width_exists_(false),
@ -2129,8 +2127,6 @@ LibertyPort::~LibertyPort()
if (tristate_enable_)
tristate_enable_->deleteSubexprs();
delete scaled_ports_;
stringDelete(related_ground_pin_);
stringDelete(related_power_pin_);
}
void
@ -2597,8 +2593,8 @@ LibertyPort::setIsSwitch(bool is_switch)
}
void
LibertyPort::setPulseClk(RiseFall *trigger,
RiseFall *sense)
LibertyPort::setPulseClk(const RiseFall *trigger,
const RiseFall *sense)
{
pulse_clk_trigger_ = trigger;
pulse_clk_sense_ = sense;
@ -2673,16 +2669,34 @@ LibertyPort::setCornerPort(LibertyPort *corner_port,
corner_ports_[ap_index] = corner_port;
}
const char *
LibertyPort::relatedGroundPin() const
{
if (related_ground_pin_.empty())
return nullptr;
else
return related_ground_pin_.c_str();
}
void
LibertyPort::setRelatedGroundPin(const char *related_ground_pin)
{
related_ground_pin_ = stringCopy(related_ground_pin);
related_ground_pin_ = related_ground_pin;
}
const char *
LibertyPort::relatedPowerPin() const
{
if (related_power_pin_.empty())
return nullptr;
else
return related_power_pin_.c_str();
}
void
LibertyPort::setRelatedPowerPin(const char *related_power_pin)
{
related_power_pin_ = stringCopy(related_power_pin);
related_power_pin_ = related_power_pin;
}
void
@ -2846,28 +2860,22 @@ LibertyPortMemberIterator::next()
BusDcl::BusDcl(const char *name,
int from,
int to) :
name_(stringCopy(name)),
name_(name),
from_(from),
to_(to)
{
}
BusDcl::~BusDcl()
{
stringDelete(name_);
}
////////////////////////////////////////////////////////////////
ModeDef::ModeDef(const char *name) :
name_(stringCopy(name))
name_(name)
{
}
ModeDef::~ModeDef()
{
values_.deleteContents();
stringDelete(name_);
}
ModeValueDef *
@ -2891,31 +2899,28 @@ ModeDef::findValueDef(const char *value)
ModeValueDef::ModeValueDef(const char *value,
FuncExpr *cond,
const char *sdf_cond) :
value_(stringCopy(value)),
value_(value),
cond_(cond),
sdf_cond_(stringCopy(sdf_cond))
sdf_cond_(sdf_cond ? sdf_cond : "")
{
}
ModeValueDef::~ModeValueDef()
{
stringDelete(value_);
if (cond_)
cond_->deleteSubexprs();
if (sdf_cond_)
stringDelete(sdf_cond_);
}
void
ModeValueDef::setSdfCond(const char *sdf_cond)
{
sdf_cond_ = stringCopy(sdf_cond);
sdf_cond_ = sdf_cond;
}
////////////////////////////////////////////////////////////////
TableTemplate::TableTemplate(const char *name) :
name_(stringCopy(name)),
name_(name),
axis1_(nullptr),
axis2_(nullptr),
axis3_(nullptr)
@ -2926,23 +2931,17 @@ TableTemplate::TableTemplate(const char *name,
TableAxisPtr axis1,
TableAxisPtr axis2,
TableAxisPtr axis3) :
name_(stringCopy(name)),
name_(name),
axis1_(axis1),
axis2_(axis2),
axis3_(axis3)
{
}
TableTemplate::~TableTemplate()
{
stringDelete(name_);
}
void
TableTemplate::setName(const char *name)
{
stringDelete(name_);
name_ = stringCopy(name);
name_ = name;
}
void
@ -2994,7 +2993,7 @@ Pvt::setTemperature(float temp)
OperatingConditions::OperatingConditions(const char *name) :
Pvt(0.0, 0.0, 0.0),
name_(stringCopy(name)),
name_(name),
// Default wireload tree.
wire_load_tree_(WireloadTree::balanced)
{
@ -3006,16 +3005,11 @@ OperatingConditions::OperatingConditions(const char *name,
float temperature,
WireloadTree wire_load_tree) :
Pvt(process, voltage, temperature),
name_(stringCopy(name)),
name_(name),
wire_load_tree_(wire_load_tree)
{
}
OperatingConditions::~OperatingConditions()
{
stringDelete(name_);
}
void
OperatingConditions::setWireloadTree(WireloadTree tree)
{
@ -3101,7 +3095,7 @@ scaleFactorPvtName(ScaleFactorPvt pvt)
////////////////////////////////////////////////////////////////
ScaleFactors::ScaleFactors(const char *name) :
name_(stringCopy(name))
name_(name)
{
for (int type = 0; type < scale_factor_type_count; type++) {
for (int pvt = 0; pvt < scale_factor_pvt_count; pvt++) {
@ -3112,15 +3106,10 @@ ScaleFactors::ScaleFactors(const char *name) :
}
}
ScaleFactors::~ScaleFactors()
{
stringDelete(name_);
}
void
ScaleFactors::setScale(ScaleFactorType type,
ScaleFactorPvt pvt,
RiseFall *rf,
const RiseFall *rf,
float scale)
{
scales_[int(type)][int(pvt)][rf->index()] = scale;
@ -3137,7 +3126,7 @@ ScaleFactors::setScale(ScaleFactorType type,
float
ScaleFactors::scale(ScaleFactorType type,
ScaleFactorPvt pvt,
RiseFall *rf)
const RiseFall *rf)
{
return scales_[int(type)][int(pvt)][rf->index()];
}
@ -3232,19 +3221,12 @@ OcvDerate::setDerateTable(const RiseFall *rf,
LibertyPgPort::LibertyPgPort(const char *name,
LibertyCell *cell) :
name_(stringCopy(name)),
name_(name),
pg_type_(unknown),
voltage_name_(nullptr),
cell_(cell)
{
}
LibertyPgPort::~LibertyPgPort()
{
stringDelete(name_);
stringDelete(voltage_name_);
}
void
LibertyPgPort::setPgType(PgType type)
{
@ -3254,14 +3236,14 @@ LibertyPgPort::setPgType(PgType type)
void
LibertyPgPort::setVoltageName(const char *voltage_name)
{
voltage_name_ = stringCopy(voltage_name);
voltage_name_ = voltage_name;
}
bool
LibertyPgPort::equiv(const LibertyPgPort *port1,
const LibertyPgPort *port2)
{
return stringEq(port1->name_, port2->name_)
return port1->name_ == port2->name_
&& port1->pg_type_ == port2->pg_type_;
}
@ -3281,7 +3263,7 @@ LibertyCellPgPortIterator::hasNext()
LibertyPgPort *
LibertyCellPgPortIterator::next()
{
const char *name;
string name;
LibertyPgPort *port;
iter_.next(name, port);
return port;

22
liberty/Liberty.i
View File

@ -206,7 +206,7 @@ find_liberty_cell(const char *name)
}
bool
timing_role_is_check(TimingRole *role)
timing_role_is_check(const TimingRole *role)
{
return role->isTimingCheck();
}
@ -313,24 +313,24 @@ bool is_bus() { return self->isBus(); }
LibertyPortMemberIterator *
member_iterator() { return new LibertyPortMemberIterator(self); }
const char *
string
function()
{
FuncExpr *func = self->function();
if (func)
return func->asString();
return func->to_string();
else
return nullptr;
return "";
}
const char *
string
tristate_enable()
{
FuncExpr *enable = self->tristateEnable();
if (enable)
return enable->asString();
return enable->to_string();
else
return nullptr;
return "";
}
float
@ -358,7 +358,7 @@ scan_signal_type()
%extend TimingArcSet {
LibertyPort *from() { return self->from(); }
LibertyPort *to() { return self->to(); }
TimingRole *role() { return self->role(); }
const TimingRole *role() { return self->role(); }
const char *sdf_cond() { return self->sdfCond(); }
const char *
@ -381,11 +381,11 @@ timing_arcs() { return self->arcs(); }
%extend TimingArc {
LibertyPort *from() { return self->from(); }
LibertyPort *to() { return self->to(); }
Transition *from_edge() { return self->fromEdge(); }
const Transition *from_edge() { return self->fromEdge(); }
const char *from_edge_name() { return self->fromEdge()->asRiseFall()->name(); }
Transition *to_edge() { return self->toEdge(); }
const Transition *to_edge() { return self->toEdge(); }
const char *to_edge_name() { return self->toEdge()->asRiseFall()->name(); }
TimingRole *role() { return self->role(); }
const TimingRole *role() { return self->role(); }
float
time_voltage(float in_slew,

48
liberty/LibertyBuilder.cc
View File

@ -327,7 +327,7 @@ LibertyBuilder::makeCombinationalArcs(LibertyCell *cell,
}
TimingModel *model;
RiseFall *to_rf;
const RiseFall *to_rf;
switch (sense) {
case TimingSense::positive_unate:
if (to_rise) {
@ -391,18 +391,20 @@ LibertyBuilder::makeLatchDtoQArcs(LibertyCell *cell,
TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port,
TimingRole::latchDtoQ(), attrs);
TimingModel *model;
RiseFall *to_rf = RiseFall::rise();
const RiseFall *to_rf = RiseFall::rise();
model = attrs->model(to_rf);
if (model) {
RiseFall *from_rf = (sense == TimingSense::negative_unate) ?
to_rf->opposite() : to_rf;
const RiseFall *from_rf = (sense == TimingSense::negative_unate)
? to_rf->opposite()
: to_rf;
makeTimingArc(arc_set, from_rf, to_rf, model);
}
to_rf = RiseFall::fall();
model = attrs->model(to_rf);
if (model) {
RiseFall *from_rf = (sense == TimingSense::negative_unate) ?
to_rf->opposite() : to_rf;
const RiseFall *from_rf = (sense == TimingSense::negative_unate)
? to_rf->opposite()
: to_rf;
makeTimingArc(arc_set, from_rf, to_rf, model);
}
return arc_set;
@ -412,7 +414,7 @@ TimingArcSet *
LibertyBuilder::makeRegLatchArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
RiseFall *from_rf,
const RiseFall *from_rf,
TimingArcAttrsPtr attrs)
{
FuncExpr *to_func = to_port->function();
@ -422,7 +424,7 @@ LibertyBuilder::makeRegLatchArcs(LibertyCell *cell,
Sequential *seq = cell->outputPortSequential(func_port);
if (seq) {
if (seq->clock() && seq->clock()->hasPort(from_port)) {
TimingRole *role = seq->isRegister() ?
const TimingRole *role = seq->isRegister() ?
TimingRole::regClkToQ() : TimingRole::latchEnToQ();
return makeFromTransitionArcs(cell, from_port, to_port, nullptr,
from_rf, role, attrs);
@ -449,8 +451,8 @@ LibertyBuilder::makeFromTransitionArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
RiseFall *from_rf,
TimingRole *role,
const RiseFall *from_rf,
const TimingRole *role,
TimingArcAttrsPtr attrs)
{
TimingArcSet *arc_set = makeTimingArcSet(cell, from_port, to_port,
@ -467,7 +469,7 @@ TimingArcSet *
LibertyBuilder::makePresetClrArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
RiseFall *to_rf,
const RiseFall *to_rf,
TimingArcAttrsPtr attrs)
{
TimingArcSet *arc_set = nullptr;
@ -475,7 +477,7 @@ LibertyBuilder::makePresetClrArcs(LibertyCell *cell,
if (model) {
arc_set = makeTimingArcSet(cell, from_port, to_port,
TimingRole::regSetClr(), attrs);
RiseFall *opp_rf = to_rf->opposite();
const RiseFall *opp_rf = to_rf->opposite();
switch (attrs->timingSense()) {
case TimingSense::positive_unate:
makeTimingArc(arc_set, to_rf, to_rf, model);
@ -513,7 +515,7 @@ LibertyBuilder::makeTristateEnableArcs(LibertyCell *cell,
if (sense == TimingSense::unknown && tristate_enable)
sense = tristate_enable->portTimingSense(from_port);
TimingModel *model;
RiseFall *to_rf;
const RiseFall *to_rf;
switch (sense) {
case TimingSense::positive_unate:
if (to_rise) {
@ -584,7 +586,7 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell,
if (sense == TimingSense::unknown && tristate_enable)
sense = timingSenseOpposite(tristate_enable->portTimingSense(from_port));
TimingModel *model;
RiseFall *to_rf;
const RiseFall *to_rf;
switch (sense) {
case TimingSense::positive_unate:
if (to_rise) {
@ -642,7 +644,7 @@ LibertyBuilder::makeTristateDisableArcs(LibertyCell *cell,
TimingArcSet *
LibertyBuilder::makeClockTreePathArcs(LibertyCell *cell,
LibertyPort *to_port,
TimingRole *role,
const TimingRole *role,
const MinMax *min_max,
TimingArcAttrsPtr attrs)
{
@ -651,7 +653,7 @@ LibertyBuilder::makeClockTreePathArcs(LibertyCell *cell,
TimingModel *model = attrs->model(to_rf);
if (model) {
const GateTableModel *gate_model = dynamic_cast<GateTableModel *>(model);
RiseFall *opp_rf = to_rf->opposite();
const RiseFall *opp_rf = to_rf->opposite();
switch (attrs->timingSense()) {
case TimingSense::positive_unate:
makeTimingArc(arc_set, to_rf, to_rf, model);
@ -681,7 +683,7 @@ LibertyBuilder::makeMinPulseWidthArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs)
{
if (from_port == nullptr)
@ -702,7 +704,7 @@ TimingArcSet *
LibertyBuilder::makeTimingArcSet(LibertyCell *cell,
LibertyPort *from,
LibertyPort *to,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs)
{
return new TimingArcSet(cell, from, to, nullptr, role, attrs);
@ -713,7 +715,7 @@ LibertyBuilder::makeTimingArcSet(LibertyCell *cell,
LibertyPort *from,
LibertyPort *to,
LibertyPort *related_out,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs)
{
return new TimingArcSet(cell, from, to, related_out, role, attrs);
@ -721,8 +723,8 @@ LibertyBuilder::makeTimingArcSet(LibertyCell *cell,
TimingArc *
LibertyBuilder::makeTimingArc(TimingArcSet *set,
RiseFall *from_rf,
RiseFall *to_rf,
const RiseFall *from_rf,
const RiseFall *to_rf,
TimingModel *model)
{
return new TimingArc(set, from_rf->asTransition(),
@ -731,8 +733,8 @@ LibertyBuilder::makeTimingArc(TimingArcSet *set,
TimingArc *
LibertyBuilder::makeTimingArc(TimingArcSet *set,
Transition *from_rf,
Transition *to_rf,
const Transition *from_rf,
const Transition *to_rf,
TimingModel *model)
{
return new TimingArc(set, from_rf, to_rf, model);

24
liberty/LibertyBuilder.hh
View File

@ -78,8 +78,8 @@ public:
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
RiseFall *from_rf,
TimingRole *role,
const RiseFall *from_rf,
const TimingRole *role,
TimingArcAttrsPtr attrs);
TimingArcSet *makeCombinationalArcs(LibertyCell *cell,
LibertyPort *from_port,
@ -89,14 +89,14 @@ public:
TimingArcAttrsPtr attrs);
TimingArcSet *makeClockTreePathArcs(LibertyCell *cell,
LibertyPort *to_port,
TimingRole *role,
const TimingRole *role,
const MinMax *min_max,
TimingArcAttrsPtr attrs);
TimingArcSet *makeMinPulseWidthArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
LibertyPort *related_out,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs);
protected:
@ -122,21 +122,21 @@ protected:
virtual TimingArcSet *makeTimingArcSet(LibertyCell *cell,
LibertyPort *from,
LibertyPort *to,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs);
virtual TimingArcSet *makeTimingArcSet(LibertyCell *cell,
LibertyPort *from,
LibertyPort *to,
LibertyPort *related_out,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs);
virtual TimingArc *makeTimingArc(TimingArcSet *set,
Transition *from_rf,
Transition *to_rf,
const Transition *from_rf,
const Transition *to_rf,
TimingModel *model);
TimingArc *makeTimingArc(TimingArcSet *set,
RiseFall *from_rf,
RiseFall *to_rf,
const RiseFall *from_rf,
const RiseFall *to_rf,
TimingModel *model);
TimingArcSet *makeLatchDtoQArcs(LibertyCell *cell,
LibertyPort *from_port,
@ -146,12 +146,12 @@ protected:
TimingArcSet *makeRegLatchArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
RiseFall *from_rf,
const RiseFall *from_rf,
TimingArcAttrsPtr attrs);
TimingArcSet *makePresetClrArcs(LibertyCell *cell,
LibertyPort *from_port,
LibertyPort *to_port,
RiseFall *to_rf,
const RiseFall *to_rf,
TimingArcAttrsPtr attrs);
TimingArcSet *makeTristateEnableArcs(LibertyCell *cell,
LibertyPort *from_port,

35
liberty/LibertyParser.cc
View File

@ -78,7 +78,7 @@ LibertyParser::makeDefine(LibertyAttrValueSeq *values,
const char *value_type_name = (*values)[2]->stringValue();
LibertyAttrType value_type = attrValueType(value_type_name);
LibertyGroupType group_type = groupType(group_type_name);
define = new LibertyDefine(stringCopy(define_name), group_type,
define = new LibertyDefine(define_name, group_type,
value_type, line);
LibertyGroup *group = this->group();
group->addDefine(define);
@ -128,6 +128,7 @@ LibertyParser::groupBegin(const char *type,
int line)
{
LibertyGroup *group = new LibertyGroup(type, params, line);
stringDelete(type);
group_visitor_->begin(group);
group_stack_.push_back(group);
}
@ -168,6 +169,7 @@ LibertyParser::makeSimpleAttr(const char *name,
int line)
{
LibertyAttr *attr = new LibertySimpleAttr(name, value, line);
stringDelete(name);
group_visitor_->visitAttr(attr);
LibertyGroup *group = this->group();
if (group && group_visitor_->save(attr)) {
@ -198,6 +200,7 @@ LibertyParser::makeComplexAttr(const char *name,
}
else {
LibertyAttr *attr = new LibertyComplexAttr(name, values, line);
stringDelete(name);
group_visitor_->visitAttr(attr);
if (group_visitor_->save(attr)) {
LibertyGroup *group = this->group();
@ -210,11 +213,12 @@ LibertyParser::makeComplexAttr(const char *name,
}
LibertyStmt *
LibertyParser::makeVariable(char *var,
LibertyParser::makeVariable(const char *var,
float value,
int line)
{
LibertyVariable *variable = new LibertyVariable(var, value, line);
stringDelete(var);
group_visitor_->visitVariable(variable);
if (group_visitor_->save(variable))
return variable;
@ -227,7 +231,9 @@ LibertyParser::makeVariable(char *var,
LibertyAttrValue *
LibertyParser::makeStringAttrValue(char *value)
{
return new LibertyStringAttrValue(value);
LibertyAttrValue *attr = new LibertyStringAttrValue(value);
stringDelete(value);
return attr;
}
LibertyAttrValue *
@ -290,7 +296,6 @@ LibertyGroup::addAttribute(LibertyAttr *attr)
LibertyGroup::~LibertyGroup()
{
stringDelete(type_);
if (params_) {
params_->deleteContents();
delete params_;
@ -370,11 +375,6 @@ LibertyAttr::LibertyAttr(const char *name,
{
}
LibertyAttr::~LibertyAttr()
{
stringDelete(name_);
}
LibertySimpleAttr::LibertySimpleAttr(const char *name,
LibertyAttrValue *value,
int line) :
@ -426,11 +426,6 @@ LibertyStringAttrValue::LibertyStringAttrValue(const char *value) :
{
}
LibertyStringAttrValue::~LibertyStringAttrValue()
{
stringDelete(value_);
}
float
LibertyStringAttrValue::floatValue()
{
@ -441,7 +436,7 @@ LibertyStringAttrValue::floatValue()
const char *
LibertyStringAttrValue::stringValue()
{
return value_;
return value_.c_str();
}
LibertyFloatAttrValue::LibertyFloatAttrValue(float value) :
@ -475,11 +470,6 @@ LibertyDefine::LibertyDefine(const char *name,
{
}
LibertyDefine::~LibertyDefine()
{
stringDelete(name_);
}
////////////////////////////////////////////////////////////////
LibertyVariable::LibertyVariable(const char *var,
@ -491,11 +481,6 @@ LibertyVariable::LibertyVariable(const char *var,
{
}
LibertyVariable::~LibertyVariable()
{
stringDelete(var_);
}
////////////////////////////////////////////////////////////////
LibertyScanner::LibertyScanner(std::istream *stream,

46
liberty/LibertyParser.hh
View File

@ -48,11 +48,11 @@ class LibertyScanner;
typedef Vector<LibertyStmt*> LibertyStmtSeq;
typedef Vector<LibertyGroup*> LibertyGroupSeq;
typedef Vector<LibertyAttr*> LibertyAttrSeq;
typedef Map<const char *, LibertyAttr*, CharPtrLess> LibertyAttrMap;
typedef Map<const char *, LibertyDefine*, CharPtrLess> LibertyDefineMap;
typedef Map<string, LibertyAttr*> LibertyAttrMap;
typedef Map<string, LibertyDefine*> LibertyDefineMap;
typedef Vector<LibertyAttrValue*> LibertyAttrValueSeq;
typedef Map<const char *, float, CharPtrLess> LibertyVariableMap;
typedef Map<const char*,LibertyGroupVisitor*,CharPtrLess>LibertyGroupVisitorMap;
typedef Map<string, float> LibertyVariableMap;
typedef Map<string, LibertyGroupVisitor*>LibertyGroupVisitorMap;
typedef LibertyAttrValueSeq::Iterator LibertyAttrValueIterator;
typedef Vector<LibertyGroup*> LibertyGroupSeq;
@ -88,7 +88,7 @@ public:
int line);
LibertyAttrValue *makeStringAttrValue(char *value);
LibertyAttrValue *makeFloatAttrValue(float value);
LibertyStmt *makeVariable(char *var,
LibertyStmt *makeVariable(const char *var,
float value,
int line);
@ -103,7 +103,7 @@ private:
class LibertyStmt
{
public:
explicit LibertyStmt(int line);
LibertyStmt(int line);
virtual ~LibertyStmt() {}
int line() const { return line_; }
virtual bool isGroup() const { return false; }
@ -126,7 +126,7 @@ public:
int line);
virtual ~LibertyGroup();
virtual bool isGroup() const { return true; }
const char *type() const { return type_; }
const char *type() const { return type_.c_str(); }
// First param as a string.
const char *firstName();
// Second param as a string.
@ -143,7 +143,7 @@ public:
protected:
void parseNames(LibertyAttrValueSeq *values);
const char *type_;
string type_;
LibertyAttrValueSeq *params_;
LibertyAttrSeq *attrs_;
LibertyAttrMap *attr_map_;
@ -154,13 +154,13 @@ protected:
class LibertySubgroupIterator : public LibertyGroupSeq::Iterator
{
public:
explicit LibertySubgroupIterator(LibertyGroup *group);
LibertySubgroupIterator(LibertyGroup *group);
};
class LibertyAttrIterator : public LibertyAttrSeq::Iterator
{
public:
explicit LibertyAttrIterator(LibertyGroup *group);
LibertyAttrIterator(LibertyGroup *group);
};
// Abstract base class for attributes.
@ -169,8 +169,7 @@ class LibertyAttr : public LibertyStmt
public:
LibertyAttr(const char *name,
int line);
virtual ~LibertyAttr();
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
virtual bool isAttribute() const { return true; }
virtual bool isSimple() const = 0;
virtual bool isComplex() const = 0;
@ -178,7 +177,7 @@ public:
virtual LibertyAttrValue *firstValue() = 0;
protected:
const char *name_;
string name_;
};
// Abstract base class for simple attributes.
@ -232,21 +231,22 @@ public:
class LibertyStringAttrValue : public LibertyAttrValue
{
public:
explicit LibertyStringAttrValue(const char *value);
virtual ~LibertyStringAttrValue();
LibertyStringAttrValue(const char *value);
virtual ~LibertyStringAttrValue() {}
virtual bool isFloat() { return false; }
virtual bool isString() { return true; }
virtual float floatValue();
virtual const char *stringValue();
private:
const char *value_;
string value_;
};
class LibertyFloatAttrValue : public LibertyAttrValue
{
public:
explicit LibertyFloatAttrValue(float value);
LibertyFloatAttrValue(float value);
virtual ~LibertyFloatAttrValue() {}
virtual bool isString() { return false; }
virtual bool isFloat() { return true; }
virtual float floatValue();
@ -266,14 +266,13 @@ public:
LibertyGroupType group_type,
LibertyAttrType value_type,
int line);
virtual ~LibertyDefine();
virtual bool isDefine() const { return true; }
const char *name() const { return name_; }
const char *name() const { return name_.c_str(); }
LibertyGroupType groupType() const { return group_type_; }
LibertyAttrType valueType() const { return value_type_; }
private:
const char *name_;
string name_;
LibertyGroupType group_type_;
LibertyAttrType value_type_;
};
@ -288,15 +287,12 @@ public:
LibertyVariable(const char *var,
float value,
int line);
// var_ is NOT deleted by ~LibertyVariable because the group
// variable map ref's it.
virtual ~LibertyVariable();
virtual bool isVariable() const { return true; }
const char *variable() const { return var_; }
const char *variable() const { return var_.c_str(); }
float value() const { return value_; }
private:
const char *var_;
string var_;
float value_;
};

111
liberty/LibertyReader.cc
View File

@ -139,25 +139,7 @@ LibertyReader::init(const char *filename,
LibertyReader::~LibertyReader()
{
if (var_map_) {
LibertyVariableMap::Iterator iter(var_map_);
while (iter.hasNext()) {
const char *var;
float value;
iter.next(var, value);
stringDelete(var);
}
delete var_map_;
}
// Scaling factor attribute names are allocated, so delete them.
LibraryAttrMap::Iterator attr_iter(attr_visitor_map_);
while (attr_iter.hasNext()) {
const char *attr_name;
LibraryAttrVisitor visitor;
attr_iter.next(attr_name, visitor);
stringDelete(attr_name);
}
delete var_map_;
}
LibertyLibrary *
@ -181,7 +163,7 @@ void
LibertyReader::defineAttrVisitor(const char *attr_name,
LibraryAttrVisitor visitor)
{
attr_visitor_map_[stringCopy(attr_name)] = visitor;
attr_visitor_map_[attr_name] = visitor;
}
void
@ -1123,7 +1105,7 @@ LibertyReader::visitDefaultIntrinsicFall(LibertyAttr *attr)
void
LibertyReader::visitDefaultIntrinsic(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (library_) {
float value;
@ -1148,7 +1130,7 @@ LibertyReader::visitDefaultInoutPinFallRes(LibertyAttr *attr)
void
LibertyReader::visitDefaultInoutPinRes(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (library_) {
float value;
@ -1173,7 +1155,7 @@ LibertyReader::visitDefaultOutputPinFallRes(LibertyAttr *attr)
void
LibertyReader::visitDefaultOutputPinRes(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (library_) {
float value;
@ -1265,7 +1247,7 @@ LibertyReader::visitInputThresholdPctRise(LibertyAttr *attr)
void
LibertyReader::visitInputThresholdPct(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (library_) {
float value;
@ -1291,7 +1273,7 @@ LibertyReader::visitOutputThresholdPctRise(LibertyAttr *attr)
void
LibertyReader::visitOutputThresholdPct(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (library_) {
float value;
@ -1317,7 +1299,7 @@ LibertyReader::visitSlewLowerThresholdPctRise(LibertyAttr *attr)
void
LibertyReader::visitSlewLowerThresholdPct(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (library_) {
float value;
@ -1343,7 +1325,7 @@ LibertyReader::visitSlewUpperThresholdPctRise(LibertyAttr *attr)
void
LibertyReader::visitSlewUpperThresholdPct(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (library_) {
float value;
@ -1614,7 +1596,7 @@ LibertyReader::visitScaleFactorSuffix(LibertyAttr *attr)
if (scale_factors_) {
ScaleFactorPvt pvt = ScaleFactorPvt::unknown;
ScaleFactorType type = ScaleFactorType::unknown;
RiseFall *rf = nullptr;
const RiseFall *rf = nullptr;
// Parse the attribute name.
TokenParser parser(attr->name(), "_");
if (parser.hasNext())
@ -1652,7 +1634,7 @@ LibertyReader::visitScaleFactorPrefix(LibertyAttr *attr)
if (scale_factors_) {
ScaleFactorPvt pvt = ScaleFactorPvt::unknown;
ScaleFactorType type = ScaleFactorType::unknown;
RiseFall *rf = nullptr;
const RiseFall *rf = nullptr;
// Parse the attribute name.
TokenParser parser(attr->name(), "_");
if (parser.hasNext())
@ -1690,7 +1672,7 @@ LibertyReader::visitScaleFactorHiLow(LibertyAttr *attr)
if (scale_factors_) {
ScaleFactorPvt pvt = ScaleFactorPvt::unknown;
ScaleFactorType type = ScaleFactorType::unknown;
RiseFall *rf = nullptr;
const RiseFall *rf = nullptr;
const char *pvt_name = nullptr;
const char *type_name = nullptr;
const char *tr_name = nullptr;
@ -2628,7 +2610,7 @@ LibertyReader::beginReceiverCapacitance2Fall(LibertyGroup *group)
void
LibertyReader::beginReceiverCapacitance(LibertyGroup *group,
int index,
RiseFall *rf)
const RiseFall *rf)
{
if (timing_ || ports_) {
beginTableModel(group, TableTemplateType::delay, rf, 1.0,
@ -2674,7 +2656,7 @@ LibertyReader::beginOutputCurrentFall(LibertyGroup *group)
}
void
LibertyReader::beginOutputCurrent(RiseFall *rf,
LibertyReader::beginOutputCurrent(const RiseFall *rf,
LibertyGroup *group)
{
if (timing_) {
@ -2800,13 +2782,13 @@ void
LibertyReader::beginNormalizedDriverWaveform(LibertyGroup *group)
{
beginTable(group, TableTemplateType::delay, time_scale_);
driver_waveform_name_ = nullptr;
driver_waveform_name_.clear();
}
void
LibertyReader::visitDriverWaveformName(LibertyAttr *attr)
{
driver_waveform_name_ = stringCopy(getAttrString(attr));
driver_waveform_name_ = getAttrString(attr);
}
void
@ -3656,7 +3638,7 @@ LibertyReader::visitMinFanout(LibertyAttr *attr)
void
LibertyReader::visitFanout(LibertyAttr *attr,
MinMax *min_max)
const MinMax *min_max)
{
if (ports_) {
float fanout;
@ -3683,7 +3665,8 @@ LibertyReader::visitMinTransition(LibertyAttr *attr)
}
void
LibertyReader::visitMinMaxTransition(LibertyAttr *attr, MinMax *min_max)
LibertyReader::visitMinMaxTransition(LibertyAttr *attr,
const MinMax *min_max)
{
if (cell_) {
float value;
@ -3714,7 +3697,7 @@ LibertyReader::visitMinCapacitance(LibertyAttr *attr)
void
LibertyReader::visitMinMaxCapacitance(LibertyAttr *attr,
MinMax *min_max)
const MinMax *min_max)
{
if (cell_) {
float value;
@ -3778,8 +3761,8 @@ LibertyReader::visitPulseClock(LibertyAttr *attr)
if (cell_) {
const char *pulse_clk = getAttrString(attr);
if (pulse_clk) {
RiseFall *trigger = nullptr;
RiseFall *sense = nullptr;
const RiseFall *trigger = nullptr;
const RiseFall *sense = nullptr;
if (stringEq(pulse_clk, "rise_triggered_high_pulse")) {
trigger = RiseFall::rise();
sense = RiseFall::rise();
@ -4438,7 +4421,7 @@ LibertyReader::visitIntrinsicFall(LibertyAttr *attr)
void
LibertyReader::visitIntrinsic(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (timing_) {
float value;
@ -4463,7 +4446,7 @@ LibertyReader::visitFallResistance(LibertyAttr *attr)
void
LibertyReader::visitRiseFallResistance(LibertyAttr *attr,
RiseFall *rf)
const RiseFall *rf)
{
if (timing_) {
float value;
@ -4596,7 +4579,7 @@ LibertyReader::endRiseFallTransitionDegredation(LibertyGroup *group)
void
LibertyReader::beginTimingTableModel(LibertyGroup *group,
RiseFall *rf,
const RiseFall *rf,
ScaleFactorType scale_factor_type)
{
if (timing_)
@ -4609,7 +4592,7 @@ LibertyReader::beginTimingTableModel(LibertyGroup *group,
void
LibertyReader::beginTableModel(LibertyGroup *group,
TableTemplateType type,
RiseFall *rf,
const RiseFall *rf,
float scale,
ScaleFactorType scale_factor_type)
{
@ -5189,7 +5172,7 @@ LibertyReader::parseFunc(const char *func,
return parseFuncExpr(func, cell_, error_msg.c_str(), report_);
}
EarlyLateAll *
const EarlyLateAll *
LibertyReader::getAttrEarlyLate(LibertyAttr *attr)
{
const char *value = getAttrString(attr);
@ -5213,7 +5196,7 @@ LibertyReader::visitVariable(LibertyVariable *var)
if (var_map_ == nullptr)
var_map_ = new LibertyVariableMap;
const char *var_name = var->variable();
const char *key;
string key;
float value;
bool exists;
var_map_->findKey(var_name, key, value, exists);
@ -5222,7 +5205,7 @@ LibertyReader::visitVariable(LibertyVariable *var)
(*var_map_)[key] = var->value();
}
else
(*var_map_)[stringCopy(var_name)] = var->value();
(*var_map_)[var_name] = var->value();
}
void
@ -5921,7 +5904,7 @@ TimingGroup::setRelatedOutputPortName(const char *name)
}
void
TimingGroup::setIntrinsic(RiseFall *rf,
TimingGroup::setIntrinsic(const RiseFall *rf,
float value)
{
int rf_index = rf->index();
@ -5930,7 +5913,7 @@ TimingGroup::setIntrinsic(RiseFall *rf,
}
void
TimingGroup::intrinsic(RiseFall *rf,
TimingGroup::intrinsic(const RiseFall *rf,
// Return values.
float &value,
bool &exists)
@ -5941,7 +5924,7 @@ TimingGroup::intrinsic(RiseFall *rf,
}
void
TimingGroup::setResistance(RiseFall *rf,
TimingGroup::setResistance(const RiseFall *rf,
float value)
{
int rf_index = rf->index();
@ -5950,7 +5933,7 @@ TimingGroup::setResistance(RiseFall *rf,
}
void
TimingGroup::resistance(RiseFall *rf,
TimingGroup::resistance(const RiseFall *rf,
// Return values.
float &value,
bool &exists)
@ -5961,63 +5944,63 @@ TimingGroup::resistance(RiseFall *rf,
}
TableModel *
TimingGroup::cell(RiseFall *rf)
TimingGroup::cell(const RiseFall *rf)
{
return cell_[rf->index()];
}
void
TimingGroup::setCell(RiseFall *rf,
TimingGroup::setCell(const RiseFall *rf,
TableModel *model)
{
cell_[rf->index()] = model;
}
TableModel *
TimingGroup::constraint(RiseFall *rf)
TimingGroup::constraint(const RiseFall *rf)
{
return constraint_[rf->index()];
}
void
TimingGroup::setConstraint(RiseFall *rf,
TimingGroup::setConstraint(const RiseFall *rf,
TableModel *model)
{
constraint_[rf->index()] = model;
}
TableModel *
TimingGroup::transition(RiseFall *rf)
TimingGroup::transition(const RiseFall *rf)
{
return transition_[rf->index()];
}
void
TimingGroup::setTransition(RiseFall *rf,
TimingGroup::setTransition(const RiseFall *rf,
TableModel *model)
{
transition_[rf->index()] = model;
}
void
TimingGroup::setDelaySigma(RiseFall *rf,
EarlyLate *early_late,
TimingGroup::setDelaySigma(const RiseFall *rf,
const EarlyLate *early_late,
TableModel *model)
{
delay_sigma_[rf->index()][early_late->index()] = model;
}
void
TimingGroup::setSlewSigma(RiseFall *rf,
EarlyLate *early_late,
TimingGroup::setSlewSigma(const RiseFall *rf,
const EarlyLate *early_late,
TableModel *model)
{
slew_sigma_[rf->index()][early_late->index()] = model;
}
void
TimingGroup::setConstraintSigma(RiseFall *rf,
EarlyLate *early_late,
TimingGroup::setConstraintSigma(const RiseFall *rf,
const EarlyLate *early_late,
TableModel *model)
{
constraint_sigma_[rf->index()][early_late->index()] = model;
@ -6030,13 +6013,13 @@ TimingGroup::setReceiverModel(ReceiverModelPtr receiver_model)
}
OutputWaveforms *
TimingGroup::outputWaveforms(RiseFall *rf)
TimingGroup::outputWaveforms(const RiseFall *rf)
{
return output_waveforms_[rf->index()];
}
void
TimingGroup::setOutputWaveforms(RiseFall *rf,
TimingGroup::setOutputWaveforms(const RiseFall *rf,
OutputWaveforms *output_waveforms)
{
output_waveforms_[rf->index()] = output_waveforms;

86
liberty/LibertyReaderPvt.hh
View File

@ -64,8 +64,8 @@ using std::vector;
typedef void (LibertyReader::*LibraryAttrVisitor)(LibertyAttr *attr);
typedef void (LibertyReader::*LibraryGroupVisitor)(LibertyGroup *group);
typedef Map<const char*,LibraryAttrVisitor,CharPtrLess> LibraryAttrMap;
typedef Map<const char*,LibraryGroupVisitor,CharPtrLess> LibraryGroupMap;
typedef Map<string, LibraryAttrVisitor> LibraryAttrMap;
typedef Map<string ,LibraryGroupVisitor> LibraryGroupMap;
typedef Vector<PortGroup*> PortGroupSeq;
typedef Vector<SequentialGroup*> SequentialGroupSeq;
typedef Vector<LibertyFunc*> LibertyFuncSeq;
@ -122,15 +122,15 @@ public:
virtual void visitDefaultIntrinsicRise(LibertyAttr *attr);
virtual void visitDefaultIntrinsicFall(LibertyAttr *attr);
virtual void visitDefaultIntrinsic(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitDefaultInoutPinRiseRes(LibertyAttr *attr);
virtual void visitDefaultInoutPinFallRes(LibertyAttr *attr);
virtual void visitDefaultInoutPinRes(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitDefaultOutputPinRiseRes(LibertyAttr *attr);
virtual void visitDefaultOutputPinFallRes(LibertyAttr *attr);
virtual void visitDefaultOutputPinRes(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitDefaultFanoutLoad(LibertyAttr *attr);
virtual void visitDefaultWireLoad(LibertyAttr *attr);
virtual void visitDefaultWireLoadMode(LibertyAttr *attr);
@ -139,19 +139,19 @@ public:
virtual void visitInputThresholdPctFall(LibertyAttr *attr);
virtual void visitInputThresholdPctRise(LibertyAttr *attr);
virtual void visitInputThresholdPct(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitOutputThresholdPctFall(LibertyAttr *attr);
virtual void visitOutputThresholdPctRise(LibertyAttr *attr);
virtual void visitOutputThresholdPct(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitSlewLowerThresholdPctFall(LibertyAttr *attr);
virtual void visitSlewLowerThresholdPctRise(LibertyAttr *attr);
virtual void visitSlewLowerThresholdPct(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitSlewUpperThresholdPctFall(LibertyAttr *attr);
virtual void visitSlewUpperThresholdPctRise(LibertyAttr *attr);
virtual void visitSlewUpperThresholdPct(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitSlewDerateFromLibrary(LibertyAttr *attr);
virtual void beginTechnology(LibertyGroup *group);
@ -247,15 +247,15 @@ public:
virtual void visitMaxFanout(LibertyAttr *attr);
virtual void visitMinFanout(LibertyAttr *attr);
virtual void visitFanout(LibertyAttr *attr,
MinMax *min_max);
const MinMax *min_max);
virtual void visitMaxTransition(LibertyAttr *attr);
virtual void visitMinTransition(LibertyAttr *attr);
virtual void visitMinMaxTransition(LibertyAttr *attr,
MinMax *min_max);
const MinMax *min_max);
virtual void visitMaxCapacitance(LibertyAttr *attr);
virtual void visitMinCapacitance(LibertyAttr *attr);
virtual void visitMinMaxCapacitance(LibertyAttr *attr,
MinMax *min_max);
const MinMax *min_max);
virtual void visitMinPeriod(LibertyAttr *attr);
virtual void visitMinPulseWidthLow(LibertyAttr *attr);
virtual void visitMinPulseWidthHigh(LibertyAttr *attr);
@ -267,7 +267,7 @@ public:
virtual void visitClockGateOutPin(LibertyAttr *attr);
void visitIsPllFeedbackPin(LibertyAttr *attr);
virtual void visitSignalType(LibertyAttr *attr);
EarlyLateAll *getAttrEarlyLate(LibertyAttr *attr);
const EarlyLateAll *getAttrEarlyLate(LibertyAttr *attr);
virtual void visitClock(LibertyAttr *attr);
virtual void visitIsolationCellDataPin(LibertyAttr *attr);
virtual void visitIsolationCellEnablePin(LibertyAttr *attr);
@ -350,11 +350,11 @@ public:
virtual void visitIntrinsicRise(LibertyAttr *attr);
virtual void visitIntrinsicFall(LibertyAttr *attr);
virtual void visitIntrinsic(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitRiseResistance(LibertyAttr *attr);
virtual void visitFallResistance(LibertyAttr *attr);
virtual void visitRiseFallResistance(LibertyAttr *attr,
RiseFall *rf);
const RiseFall *rf);
virtual void visitValue(LibertyAttr *attr);
virtual void visitValues(LibertyAttr *attr);
virtual void beginCellRise(LibertyGroup *group);
@ -373,12 +373,12 @@ public:
virtual void beginTableModel(LibertyGroup *group,
TableTemplateType type,
RiseFall *rf,
const RiseFall *rf,
float scale,
ScaleFactorType scale_factor_type);
virtual void endTableModel();
virtual void beginTimingTableModel(LibertyGroup *group,
RiseFall *rf,
const RiseFall *rf,
ScaleFactorType scale_factor_type);
virtual void beginTable(LibertyGroup *group,
TableTemplateType type,
@ -469,14 +469,14 @@ public:
virtual void beginReceiverCapacitance2Fall(LibertyGroup *group);
void beginReceiverCapacitance(LibertyGroup *group,
int index,
RiseFall *rf);
const RiseFall *rf);
void endReceiverCapacitance(LibertyGroup *group,
int index,
RiseFall *rf);
const RiseFall *rf);
// ccs
void beginOutputCurrentRise(LibertyGroup *group);
void beginOutputCurrentFall(LibertyGroup *group);
void beginOutputCurrent(RiseFall *rf,
void beginOutputCurrent(const RiseFall *rf,
LibertyGroup *group);
void endOutputCurrentRiseFall(LibertyGroup *group);
void beginVector(LibertyGroup *group);
@ -645,12 +645,12 @@ protected:
InternalPowerGroup *internal_power_;
LeakagePowerGroup *leakage_power_;
LeakagePowerGroupSeq leakage_powers_;
RiseFall *rf_;
const RiseFall *rf_;
int index_;
OcvDerate *ocv_derate_;
RiseFallBoth *rf_type_;
EarlyLateAll *derate_type_;
EarlyLateAll *sigma_type_;
const RiseFallBoth *rf_type_;
const EarlyLateAll *derate_type_;
const EarlyLateAll *sigma_type_;
PathType path_type_;
LibertyPgPort *pg_port_;
ScaleFactorType scale_factor_type_;
@ -674,7 +674,7 @@ protected:
OutputWaveforms *output_waveforms_;
float reference_time_;
bool reference_time_exists_;
const char *driver_waveform_name_;
string driver_waveform_name_;
TestCell *test_cell_;
// Saved state while parsing test_cell.
@ -833,41 +833,41 @@ public:
TimingArcAttrsPtr attrs() { return attrs_; }
const char *relatedOutputPortName()const {return related_output_port_name_;}
void setRelatedOutputPortName(const char *name);
void intrinsic(RiseFall *rf,
void intrinsic(const RiseFall *rf,
// Return values.
float &value,
bool &exists);
void setIntrinsic(RiseFall *rf,
void setIntrinsic(const RiseFall *rf,
float value);
void resistance(RiseFall *rf,
void resistance(const RiseFall *rf,
// Return values.
float &value,
bool &exists);
void setResistance(RiseFall *rf,
void setResistance(const RiseFall *rf,
float value);
TableModel *cell(RiseFall *rf);
void setCell(RiseFall *rf,
TableModel *cell(const RiseFall *rf);
void setCell(const RiseFall *rf,
TableModel *model);
TableModel *constraint(RiseFall *rf);
void setConstraint(RiseFall *rf,
TableModel *constraint(const RiseFall *rf);
void setConstraint(const RiseFall *rf,
TableModel *model);
TableModel *transition(RiseFall *rf);
void setTransition(RiseFall *rf,
TableModel *transition(const RiseFall *rf);
void setTransition(const RiseFall *rf,
TableModel *model);
void makeTimingModels(LibertyCell *cell,
LibertyReader *visitor);
void setDelaySigma(RiseFall *rf,
EarlyLate *early_late,
void setDelaySigma(const RiseFall *rf,
const EarlyLate *early_late,
TableModel *model);
void setSlewSigma(RiseFall *rf,
EarlyLate *early_late,
void setSlewSigma(const RiseFall *rf,
const EarlyLate *early_late,
TableModel *model);
void setConstraintSigma(RiseFall *rf,
EarlyLate *early_late,
void setConstraintSigma(const RiseFall *rf,
const EarlyLate *early_late,
TableModel *model);
void setReceiverModel(ReceiverModelPtr receiver_model);
OutputWaveforms *outputWaveforms(RiseFall *rf);
void setOutputWaveforms(RiseFall *rf,
OutputWaveforms *outputWaveforms(const RiseFall *rf);
void setOutputWaveforms(const RiseFall *rf,
OutputWaveforms *output_current);
protected:

14
liberty/LibertyWriter.cc
View File

@ -358,16 +358,18 @@ LibertyWriter::writePortAttrs(const LibertyPort *port)
// cannot ref internal ports until sequentials are written
&& !(func->port()
&& func->port()->direction()->isInternal()))
fprintf(stream_, " function : \"%s\";\n", func->asString());
fprintf(stream_, " function : \"%s\";\n", func->to_string().c_str());
auto tristate_enable = port->tristateEnable();
if (tristate_enable) {
if (tristate_enable->op() == FuncExpr::op_not) {
FuncExpr *three_state = tristate_enable->left();
fprintf(stream_, " three_state : \"%s\";\n", three_state->asString());
fprintf(stream_, " three_state : \"%s\";\n",
three_state->to_string().c_str());
}
else {
FuncExpr three_state(FuncExpr::op_not, tristate_enable, nullptr, nullptr);
fprintf(stream_, " three_state : \"%s\";\n", three_state.asString());
fprintf(stream_, " three_state : \"%s\";\n",
three_state.to_string().c_str());
}
}
if (port->isClock())
@ -417,12 +419,12 @@ LibertyWriter::writeTimingArcSet(const TimingArcSet *arc_set)
if (sense != TimingSense::unknown
&& sense != TimingSense::non_unate)
fprintf(stream_, " timing_sense : %s;\n",
timingSenseString(sense));
to_string(sense));
const char *timing_type = timingTypeString(arc_set);
if (timing_type)
fprintf(stream_, " timing_type : %s;\n", timing_type);
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
TimingArc *arc = arc_set->arcTo(rf);
if (arc)
writeTimingModels(arc, rf);
@ -634,7 +636,7 @@ LibertyWriter::timingTypeString(const TimingArcSet *arc_set)
library_->name(),
arc_set->to()->libertyCell()->name(),
arc_set->to()->name(),
role->asString());
role->to_string().c_str());
return nullptr;
}
}

9
liberty/TableModel.cc
View File

@ -375,7 +375,7 @@ ReceiverModel::~ReceiverModel()
void
ReceiverModel::setCapacitanceModel(TableModel *table_model,
size_t segment,
RiseFall *rf)
const RiseFall *rf)
{
if ((segment + 1) * RiseFall::index_count > capacitance_models_.size())
capacitance_models_.resize((segment + 1) * RiseFall::index_count);
@ -2062,18 +2062,13 @@ OutputWaveforms::finalResistance()
////////////////////////////////////////////////////////////////
DriverWaveform::DriverWaveform(const char *name,
DriverWaveform::DriverWaveform(const string &name,
TablePtr waveforms) :
name_(name),
waveforms_(waveforms)
{
}
DriverWaveform::~DriverWaveform()
{
stringDelete(name_);
}
Table1
DriverWaveform::waveform(float slew)
{

16
liberty/TimingArc.cc
View File

@ -188,7 +188,7 @@ TimingArcSet::TimingArcSet(LibertyCell *cell,
LibertyPort *from,
LibertyPort *to,
LibertyPort *related_out,
TimingRole *role,
const TimingRole *role,
TimingArcAttrsPtr attrs) :
from_(from),
to_(to),
@ -204,7 +204,7 @@ TimingArcSet::TimingArcSet(LibertyCell *cell,
{
}
TimingArcSet::TimingArcSet(TimingRole *role,
TimingArcSet::TimingArcSet(const TimingRole *role,
TimingArcAttrsPtr attrs) :
from_(nullptr),
to_(nullptr),
@ -292,7 +292,7 @@ TimingArcSet::findTimingArc(unsigned arc_index)
}
void
TimingArcSet::setRole(TimingRole *role)
TimingArcSet::setRole(const TimingRole *role)
{
role_ = role;
}
@ -422,8 +422,8 @@ timingArcSetLess(const TimingArcSet *set1,
LibertyPort *to1 = set1->to();
LibertyPort *to2 = set2->to();
if (LibertyPort::equiv(to1, to2)) {
TimingRole *role1 = set1->role();
TimingRole *role2 = set2->role();
const TimingRole *role1 = set1->role();
const TimingRole *role2 = set2->role();
if (role1 == role2) {
const FuncExpr *cond1 = set1->cond();
const FuncExpr *cond2 = set2->cond();
@ -536,8 +536,8 @@ TimingArcSet::destroy()
////////////////////////////////////////////////////////////////
TimingArc::TimingArc(TimingArcSet *set,
Transition *from_rf,
Transition *to_rf,
const Transition *from_rf,
const Transition *to_rf,
TimingModel *model) :
set_(set),
from_rf_(from_rf),
@ -664,7 +664,7 @@ static EnumNameMap<TimingSense> timing_sense_name_map =
};
const char *
timingSenseString(TimingSense sense)
to_string(TimingSense sense)
{
return timing_sense_name_map.find(sense);
}

249
liberty/TimingRole.cc
View File

@ -26,178 +26,75 @@
namespace sta {
TimingRole *TimingRole::wire_;
TimingRole *TimingRole::combinational_;
TimingRole *TimingRole::tristate_enable_;
TimingRole *TimingRole::tristate_disable_;
TimingRole *TimingRole::reg_clk_q_;
TimingRole *TimingRole::reg_set_clr_;
TimingRole *TimingRole::latch_en_q_;
TimingRole *TimingRole::latch_d_q_;
TimingRole *TimingRole::sdf_iopath_;
TimingRole *TimingRole::setup_;
TimingRole *TimingRole::hold_;
TimingRole *TimingRole::recovery_;
TimingRole *TimingRole::removal_;
TimingRole *TimingRole::width_;
TimingRole *TimingRole::period_;
TimingRole *TimingRole::skew_;
TimingRole *TimingRole::nochange_;
TimingRole *TimingRole::output_setup_;
TimingRole *TimingRole::output_hold_;
TimingRole *TimingRole::gated_clk_setup_;
TimingRole *TimingRole::gated_clk_hold_;
TimingRole *TimingRole::latch_setup_;
TimingRole *TimingRole::latch_hold_;
TimingRole *TimingRole::data_check_setup_;
TimingRole *TimingRole::data_check_hold_;
TimingRole *TimingRole::non_seq_setup_;
TimingRole *TimingRole::non_seq_hold_;
TimingRole *TimingRole::clock_tree_path_min_;
TimingRole *TimingRole::clock_tree_path_max_;
TimingRoleMap TimingRole::timing_roles_;
void
TimingRole::init()
{
wire_ = new TimingRole("wire", false, false, false, nullptr, nullptr, 0);
combinational_ = new TimingRole("combinational", true, false, false,
nullptr, nullptr, 1);
tristate_enable_ = new TimingRole("tristate enable",
true, false, false,
nullptr, nullptr, 2);
tristate_disable_ = new TimingRole("tristate disable",
true, false, false,
nullptr, nullptr, 3);
reg_clk_q_ = new TimingRole("Reg Clk to Q", true, false, false,
nullptr, nullptr, 4);
reg_set_clr_ = new TimingRole("Reg Set/Clr", true, false, false,
nullptr, nullptr, 5);
latch_en_q_ = new TimingRole("Latch En to Q", true, false, false,
nullptr, TimingRole::regClkToQ(), 6);
latch_d_q_ = new TimingRole("Latch D to Q", true, false, false,
nullptr, nullptr, 7);
sdf_iopath_ = new TimingRole("sdf IOPATH", true, false, false,
nullptr, nullptr, 8);
setup_ = new TimingRole("setup", false, true, false,
MinMax::max(), nullptr, 9);
hold_ = new TimingRole("hold", false, true, false,
MinMax::min(), nullptr, 10);
recovery_ = new TimingRole("recovery", false, true, false,
MinMax::max(), TimingRole::setup(), 11);
removal_ = new TimingRole("removal", false, true, false,
MinMax::min(), TimingRole::hold(), 12);
width_ = new TimingRole("width", false, true, false,
nullptr, nullptr, 13);
period_ = new TimingRole("period", false, true, false,
nullptr, nullptr, 14);
skew_ = new TimingRole("skew", false, true, false,
nullptr, nullptr, 15);
nochange_ = new TimingRole("nochange", true, false, false,
nullptr, nullptr, 16);
output_setup_ = new TimingRole("output setup", false, true, false,
MinMax::max(), TimingRole::setup(), 17);
output_hold_ = new TimingRole("output hold", false, true, false,
MinMax::min(), TimingRole::hold(), 18);
gated_clk_setup_ = new TimingRole("clock gating setup",
false, true, false,
MinMax::max(), TimingRole::setup(),19);
gated_clk_hold_ = new TimingRole("clock gating hold", false, true, false,
MinMax::min(), TimingRole::hold(),20);
latch_setup_ = new TimingRole("latch setup", false, true, false,
MinMax::max(), TimingRole::setup(),21);
latch_hold_ = new TimingRole("latch hold", false, true, false,
MinMax::min(), TimingRole::hold(),22);
data_check_setup_ = new TimingRole("data check setup",
false, true, false,
MinMax::max(),TimingRole::setup(),23);
data_check_hold_ = new TimingRole("data check hold", false, true, false,
MinMax::min(), TimingRole::hold(), 24);
non_seq_setup_ = new TimingRole("non-sequential setup", false, true, true,
MinMax::max(), TimingRole::setup(), 25);
non_seq_hold_ = new TimingRole("non-sequential hold", false, true, true,
MinMax::min(), TimingRole::hold(), 26);
clock_tree_path_min_ = new TimingRole("min clock tree path", false, false, false,
MinMax::min(), nullptr, 27);
clock_tree_path_max_ = new TimingRole("max clock tree path", false, false, false,
MinMax::max(), nullptr, 28);
}
void
TimingRole::destroy()
{
delete wire_;
wire_ = nullptr;
delete combinational_;
combinational_ = nullptr;
delete tristate_enable_;
tristate_enable_ = nullptr;
delete tristate_disable_;
tristate_disable_ = nullptr;
delete reg_clk_q_;
reg_clk_q_ = nullptr;
delete reg_set_clr_;
reg_set_clr_ = nullptr;
delete latch_en_q_;
latch_en_q_ = nullptr;
delete latch_d_q_;
latch_d_q_ = nullptr;
delete sdf_iopath_;
sdf_iopath_ = nullptr;
delete setup_;
setup_ = nullptr;
delete hold_;
hold_ = nullptr;
delete recovery_;
recovery_ = nullptr;
delete removal_;
removal_ = nullptr;
delete width_;
width_ = nullptr;
delete period_;
period_ = nullptr;
delete skew_;
skew_ = nullptr;
delete nochange_;
nochange_ = nullptr;
delete output_setup_;
output_setup_ = nullptr;
delete output_hold_;
output_hold_ = nullptr;
delete gated_clk_setup_;
gated_clk_setup_ = nullptr;
delete gated_clk_hold_;
gated_clk_hold_ = nullptr;
delete latch_setup_;
latch_setup_ = nullptr;
delete latch_hold_;
latch_hold_ = nullptr;
delete data_check_setup_;
data_check_setup_ = nullptr;
delete data_check_hold_;
data_check_hold_ = nullptr;
delete non_seq_setup_;
non_seq_setup_ = nullptr;
delete non_seq_hold_;
non_seq_hold_ = nullptr;
delete clock_tree_path_min_;
clock_tree_path_min_ = nullptr;
delete clock_tree_path_max_;
clock_tree_path_max_ = nullptr;
timing_roles_.clear();
}
const TimingRole TimingRole::wire_("wire", false, false, false, nullptr, nullptr, 0);
const TimingRole TimingRole::combinational_("combinational", true, false, false,
nullptr, nullptr, 1);
const TimingRole TimingRole::tristate_enable_("tristate enable",
true, false, false,
nullptr, nullptr, 2);
const TimingRole TimingRole::tristate_disable_("tristate disable",
true, false, false,
nullptr, nullptr, 3);
const TimingRole TimingRole::reg_clk_q_("Reg Clk to Q", true, false, false,
nullptr, nullptr, 4);
const TimingRole TimingRole::reg_set_clr_("Reg Set/Clr", true, false, false,
nullptr, nullptr, 5);
const TimingRole TimingRole::latch_en_q_("Latch En to Q", true, false, false,
nullptr, TimingRole::regClkToQ(), 6);
const TimingRole TimingRole::latch_d_q_("Latch D to Q", true, false, false,
nullptr, nullptr, 7);
const TimingRole TimingRole::sdf_iopath_("sdf IOPATH", true, false, false,
nullptr, nullptr, 8);
const TimingRole TimingRole::setup_("setup", false, true, false,
MinMax::max(), nullptr, 9);
const TimingRole TimingRole::hold_("hold", false, true, false,
MinMax::min(), nullptr, 10);
const TimingRole TimingRole::recovery_("recovery", false, true, false,
MinMax::max(), TimingRole::setup(), 11);
const TimingRole TimingRole::removal_("removal", false, true, false,
MinMax::min(), TimingRole::hold(), 12);
const TimingRole TimingRole::width_("width", false, true, false,
nullptr, nullptr, 13);
const TimingRole TimingRole::period_("period", false, true, false,
nullptr, nullptr, 14);
const TimingRole TimingRole::skew_("skew", false, true, false,
nullptr, nullptr, 15);
const TimingRole TimingRole::nochange_("nochange", true, false, false,
nullptr, nullptr, 16);
const TimingRole TimingRole::output_setup_("output setup", false, true, false,
MinMax::max(), TimingRole::setup(), 17);
const TimingRole TimingRole::output_hold_("output hold", false, true, false,
MinMax::min(), TimingRole::hold(), 18);
const TimingRole TimingRole::gated_clk_setup_("clock gating setup",
false, true, false,
MinMax::max(), TimingRole::setup(),19);
const TimingRole TimingRole::gated_clk_hold_("clock gating hold", false, true, false,
MinMax::min(), TimingRole::hold(),20);
const TimingRole TimingRole::latch_setup_("latch setup", false, true, false,
MinMax::max(), TimingRole::setup(),21);
const TimingRole TimingRole::latch_hold_("latch hold", false, true, false,
MinMax::min(), TimingRole::hold(),22);
const TimingRole TimingRole::data_check_setup_("data check setup",
false, true, false,
MinMax::max(),TimingRole::setup(),23);
const TimingRole TimingRole::data_check_hold_("data check hold", false, true, false,
MinMax::min(), TimingRole::hold(), 24);
const TimingRole TimingRole::non_seq_setup_("non-sequential setup", false, true, true,
MinMax::max(), TimingRole::setup(), 25);
const TimingRole TimingRole::non_seq_hold_("non-sequential hold", false, true, true,
MinMax::min(), TimingRole::hold(), 26);
const TimingRole TimingRole::clock_tree_path_min_("min clock tree path", false, false,
false, MinMax::min(), nullptr, 27);
const TimingRole TimingRole::clock_tree_path_max_("max clock tree path", false, false,
false, MinMax::max(), nullptr, 28);
TimingRole::TimingRole(const char *name,
bool is_sdf_iopath,
bool is_timing_check,
bool is_non_seq_check,
MinMax *path_min_max,
TimingRole *generic_role,
const MinMax *path_min_max,
const TimingRole *generic_role,
int index) :
name_(name),
is_timing_check_(is_timing_check),
@ -210,7 +107,7 @@ TimingRole::TimingRole(const char *name,
timing_roles_[name] = this;
}
TimingRole *
const TimingRole *
TimingRole::find(const char *name)
{
return timing_roles_[name];
@ -220,7 +117,7 @@ const TimingRole *
TimingRole::sdfRole() const
{
if (is_sdf_iopath_)
return sdf_iopath_;
return &sdf_iopath_;
else
return this;
}
@ -243,35 +140,35 @@ TimingRole::tgtClkEarlyLate() const
bool
TimingRole::isWire() const
{
return this == wire_;
return this == &wire_;
}
bool
TimingRole::isAsyncTimingCheck() const
{
return this == recovery_
|| this == removal_;
return this == &recovery_
|| this == &removal_;
}
bool
TimingRole::isDataCheck() const
{
return this == data_check_setup_
|| this == data_check_hold_;
return this == &data_check_setup_
|| this == &data_check_hold_;
}
bool
TimingRole::isLatchDtoQ() const
{
return this == latch_d_q_;
return this == &latch_d_q_;
}
bool
TimingRole::isTimingCheckBetween() const
{
return is_timing_check_
&& this != width_
&& this != period_;
&& this != &width_
&& this != &period_;
}
bool

26
network/ConcreteLibrary.cc
View File

@ -45,9 +45,9 @@ static constexpr char escape_ = '\\';
ConcreteLibrary::ConcreteLibrary(const char *name,
const char *filename,
bool is_liberty) :
name_(stringCopy(name)),
name_(name),
id_(ConcreteNetwork::nextObjectId()),
filename_(stringCopy(filename)),
filename_(filename ? filename : ""),
is_liberty_(is_liberty),
bus_brkt_left_('['),
bus_brkt_right_(']')
@ -56,8 +56,6 @@ ConcreteLibrary::ConcreteLibrary(const char *name,
ConcreteLibrary::~ConcreteLibrary()
{
stringDelete(name_);
stringDelete(filename_);
cell_map_.deleteContents();
}
@ -131,9 +129,9 @@ ConcreteCell::ConcreteCell(const char *name,
const char *filename,
bool is_leaf,
ConcreteLibrary *library) :
name_(stringCopy(name)),
name_(name),
id_(ConcreteNetwork::nextObjectId()),
filename_(stringCopy(filename)),
filename_(filename ? filename : ""),
library_(library),
liberty_cell_(nullptr),
ext_cell_(nullptr),
@ -144,19 +142,14 @@ ConcreteCell::ConcreteCell(const char *name,
ConcreteCell::~ConcreteCell()
{
stringDelete(name_);
if (filename_)
stringDelete(filename_);
ports_.deleteContents();
}
void
ConcreteCell::setName(const char *name)
{
const char *name_cpy = stringCopy(name);
library_->renameCell(this, name_cpy);
stringDelete(name_);
name_ = name_cpy;
library_->renameCell(this, name);
name_ = name;
}
void
@ -422,7 +415,7 @@ ConcretePort::ConcretePort(const char *name,
bool is_bundle,
ConcretePortSeq *member_ports,
ConcreteCell *cell) :
name_(stringCopy(name)),
name_(name),
id_(ConcreteNetwork::nextObjectId()),
cell_(cell),
direction_(PortDirection::unknown()),
@ -444,7 +437,6 @@ ConcretePort::~ConcretePort()
if (is_bus_)
member_ports_->deleteContents();
delete member_ports_;
stringDelete(name_);
}
Cell *
@ -471,14 +463,14 @@ ConcretePort::busName() const
if (is_bus_) {
ConcreteLibrary *lib = cell_->library();
return stringPrintTmp("%s%c%d:%d%c",
name_,
name(),
lib->busBrktLeft(),
from_index_,
to_index_,
lib->busBrktRight());
}
else
return name_;
return name();
}
ConcretePort *

4
parasitics/ReduceParasitics.cc
View File

@ -312,8 +312,8 @@ reduceToPiElmore(const Parasitic *parasitic_network,
if (drvr_node) {
debugPrint(sta->debug(), "parasitic_reduce", 1, "Reduce driver %s %s %s",
sta->network()->pathName(drvr_pin),
rf->asString(),
min_max->asString());
rf->to_string().c_str(),
min_max->to_string().c_str());
ReduceToPiElmore reducer(sta);
return reducer.makePiElmore(parasitic_network, drvr_pin, drvr_node,
coupling_cap_factor, rf, corner,

20
power/Power.cc
View File

@ -364,7 +364,7 @@ ActivitySrchPred::ActivitySrchPred(const StaState *sta) :
bool
ActivitySrchPred::searchThru(Edge *edge)
{
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
return SearchPredNonLatch2::searchThru(edge)
&& role != TimingRole::regClkToQ();
}
@ -421,7 +421,7 @@ PropActivityVisitor::visit(Vertex *vertex)
Pin *pin = vertex->pin();
Instance *inst = network_->instance(pin);
debugPrint(debug_, "power_activity", 3, "visit %s",
vertex->name(network_));
vertex->to_string(this).c_str());
bool changed = false;
if (power_->hasUserActivity(pin)) {
PwrActivity &activity = power_->userActivity(pin);
@ -709,7 +709,7 @@ Power::seedActivities(BfsFwdIterator &bfs)
if (!sdc_->isLeafPinClock(pin)
&& !network_->direction(pin)->isInternal()) {
debugPrint(debug_, "power_activity", 3, "seed %s",
vertex->name(network_));
vertex->to_string(this).c_str());
if (hasUserActivity(pin))
setActivity(pin, userActivity(pin));
else
@ -743,7 +743,7 @@ Power::seedRegOutputActivities(const Instance *inst,
&& (func->port() == seq->output()
|| func->port() == seq->outputInv())) {
debugPrint(debug_, "power_reg", 1, "enqueue reg output %s",
vertex->name(network_));
vertex->to_string(this).c_str());
bfs.enqueue(vertex);
}
}
@ -870,7 +870,7 @@ Power::findInputInternalPower(const Pin *pin,
const char *related_pg_pin = pwr->relatedPgPin();
float energy = 0.0;
int rf_count = 0;
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
float slew = getSlew(vertex, rf, corner);
if (!delayInf(slew)) {
float table_energy = pwr->power(rf, pvt, slew, load_cap);
@ -900,7 +900,7 @@ Power::findInputInternalPower(const Pin *pin,
float port_internal = energy * duty * activity.density();
debugPrint(debug_, "power", 2, " %3s %6s %.2f %.2f %9.2e %9.2e %s",
port->name(),
when ? when->asString() : "",
when ? when->to_string().c_str() : "",
activity.density() * 1e-9,
duty,
energy,
@ -1031,9 +1031,9 @@ Power::findOutputInternalPower(const LibertyPort *to_port,
}
float energy = 0.0;
int rf_count = 0;
for (RiseFall *to_rf : RiseFall::range()) {
for (const RiseFall *to_rf : RiseFall::range()) {
// Use unateness to find from_rf.
RiseFall *from_rf = positive_unate ? to_rf : to_rf->opposite();
const RiseFall *from_rf = positive_unate ? to_rf : to_rf->opposite();
float slew = from_vertex
? getSlew(from_vertex, from_rf, corner)
: 0.0;
@ -1058,7 +1058,7 @@ Power::findOutputInternalPower(const LibertyPort *to_port,
debugPrint(debug_, "power", 2, "%3s -> %-3s %6s %.3f %.3f %.3f %9.2e %9.2e %s",
from_corner_port ? from_corner_port->name() : "-" ,
to_port->name(),
when ? when->asString() : "",
when ? when->to_string().c_str() : "",
to_activity.density() * 1e-9,
duty,
weight,
@ -1189,7 +1189,7 @@ Power::findLeakagePower(const Instance *inst,
float cond_duty = cond_activity.duty();
debugPrint(debug_, "power", 2, "leakage %s %s %.3e * %.2f",
cell->name(),
when->asString(),
when->to_string().c_str(),
leak->power(),
cond_duty);
cond_leakage += leak->power() * cond_duty;

6
sdc/Clock.cc
View File

@ -535,10 +535,10 @@ Clock::isDivideByOneCombinational() const
////////////////////////////////////////////////////////////////
ClockEdge::ClockEdge(Clock *clock,
RiseFall *rf) :
const RiseFall *rf) :
clock_(clock),
rf_(rf),
name_(stringPrint("%s %s", clock_->name(), rf_->asString())),
name_(stringPrint("%s %s", clock_->name(), rf_->to_string().c_str())),
time_(0.0),
index_(clock_->index() * RiseFall::index_count + rf_->index())
{
@ -671,7 +671,7 @@ InterClockUncertainty::removeUncertainty(const RiseFallBoth *src_rf,
}
const RiseFallMinMax *
InterClockUncertainty::uncertainties(RiseFall *src_rf) const
InterClockUncertainty::uncertainties(const RiseFall *src_rf) const
{
return &uncertainties_[src_rf->index()];
}

6
sdc/CycleAccting.cc
View File

@ -79,10 +79,10 @@ CycleAcctings::reportClkToClkMaxCycleWarnings(Report *report)
// duplicate warnings between different src/tgt clk edges.
ClockPairSet clk_warnings;
for (Clock *src_clk : *sdc_->clocks()) {
for (RiseFall *src_rf : RiseFall::range()) {
for (const RiseFall *src_rf : RiseFall::range()) {
ClockEdge *src = src_clk->edge(src_rf);
for (Clock *tgt_clk : *sdc_->clocks()) {
for (RiseFall *tgt_rf : RiseFall::range()) {
for (const RiseFall *tgt_rf : RiseFall::range()) {
ClockEdge *tgt = tgt_clk->edge(tgt_rf);
CycleAccting probe(src, tgt);
CycleAccting *acct = cycle_acctings_.findKey(&probe);
@ -320,7 +320,7 @@ CycleAccting::setHoldAccting(int src_cycle,
}
void
CycleAccting::setAccting(TimingRole *role,
CycleAccting::setAccting(const TimingRole *role,
int src_cycle,
int tgt_cycle,
float delay,

2
sdc/DataCheck.cc
View File

@ -80,7 +80,7 @@ DataCheck::empty() const
}
void
DataCheck::marginIsOneValue(SetupHold *setup_hold,
DataCheck::marginIsOneValue(const SetupHold *setup_hold,
// Return values.
float &value,
bool &one_value) const

2
sdc/ExceptionPath.cc
View File

@ -320,7 +320,7 @@ ExceptionPath::fromThruToString(const Network *network) const
string str;
if (min_max_ != MinMaxAll::all()) {
str += " -";
str += min_max_->asString();
str += min_max_->to_string();
}
if (from_)

2
sdc/PortDelay.cc
View File

@ -81,7 +81,7 @@ PortDelay::setNetworkLatencyIncluded(bool included)
network_latency_included_ = included;
}
RiseFall *
const RiseFall *
PortDelay::refTransition() const
{
// Reference pin transition is the clock transition.

2
sdc/Sdc.cc
View File

@ -3836,7 +3836,7 @@ Sdc::exceptionToInvalid(const Pin *pin)
if (port) {
LibertyCell *cell = port->libertyCell();
for (TimingArcSet *arc_set : cell->timingArcSets(nullptr, port)) {
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (role->genericRole() == TimingRole::regClkToQ())
return true;
}

2
sdc/Sdc.i
View File

@ -1433,6 +1433,6 @@ slew(const RiseFall *rf,
%extend ClockEdge {
Clock *clock() { return self->clock(); }
RiseFall *transition() { return self->transition(); }
const RiseFall *transition() { return self->transition(); }
float time() { return self->time(); }
}

8
sdc/WriteSdc.cc
View File

@ -1180,7 +1180,7 @@ void
WriteSdc::writeDisabledEdgeSense(Edge *edge) const
{
gzprintf(stream_, "set_disable_timing ");
const char *sense = timingSenseString(edge->sense());
const char *sense = to_string(edge->sense());
string filter;
stringPrint(filter, "sense == %s", sense);
writeGetTimingArcs(edge, filter.c_str());
@ -1451,9 +1451,9 @@ WriteSdc::writeDataCheck(DataCheck *check) const
void
WriteSdc::writeDataCheck(DataCheck *check,
RiseFallBoth *from_rf,
RiseFallBoth *to_rf,
SetupHold *setup_hold,
const RiseFallBoth *from_rf,
const RiseFallBoth *to_rf,
const SetupHold *setup_hold,
float margin) const
{
const char *from_key = "-from";

6
sdc/WriteSdcPvt.hh
View File

@ -121,9 +121,9 @@ public:
void writeDataChecks() const;
void writeDataCheck(DataCheck *check) const;
void writeDataCheck(DataCheck *check,
RiseFallBoth *from_rf,
RiseFallBoth *to_rf,
SetupHold *setup_hold,
const RiseFallBoth *from_rf,
const RiseFallBoth *to_rf,
const SetupHold *setup_hold,
float margin) const;
void writeEnvironment() const;
void writeOperatingConditions() const;

10
sdf/ReportAnnotation.cc
View File

@ -93,7 +93,7 @@ protected:
int index,
int &total,
int &annotated_total);
void reportCheckCount(TimingRole *role,
void reportCheckCount(const TimingRole *role,
int &total,
int &annotated_total);
int roleIndex(const TimingRole *role,
@ -284,14 +284,14 @@ ReportAnnotated::reportCheckCounts()
}
void
ReportAnnotated::reportCheckCount(TimingRole *role,
ReportAnnotated::reportCheckCount(const TimingRole *role,
int &total,
int &annotated_total)
{
int index = role->index();
if (edge_count_[index] > 0) {
string title;
stringPrint(title, "cell %s arcs", role->asString());
stringPrint(title, "cell %s arcs", role->to_string().c_str());
reportCount(title.c_str(), index, total, annotated_total);
}
}
@ -478,13 +478,13 @@ ReportAnnotated::reportArcs(Vertex *vertex,
while (edge_iter.hasNext()
&& (max_lines_ == 0 || i < max_lines_)) {
Edge *edge = edge_iter.next();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
const Pin *to_pin = edge->to(graph_)->pin();
if (graph_->delayAnnotated(edge) == report_annotated
&& report_role_[roleIndex(role, from_pin, to_pin)]) {
const char *role_name;
if (role->isTimingCheck())
role_name = role->asString();
role_name = role->to_string().c_str();
else if (role->isWire()) {
if (network_->isTopLevelPort(from_pin))
role_name = "primary input net";

2
sdf/SdfParse.yy
View File

@ -66,7 +66,7 @@ sta::SdfParse::error(const location_type &loc,
sta::SdfTriple *triple;
sta::SdfTripleSeq *delval_list;
sta::SdfPortSpec *port_spec;
sta::Transition *transition;
const sta::Transition *transition;
}
%token DELAYFILE SDFVERSION DESIGN DATE VENDOR PROGRAM PVERSION

16
sdf/SdfReader.cc
View File

@ -430,7 +430,7 @@ SdfReader::findPort(const Cell *cell,
}
void
SdfReader::timingCheck(TimingRole *role,
SdfReader::timingCheck(const TimingRole *role,
SdfPortSpec *data_edge,
SdfPortSpec *clk_edge,
SdfTriple *triple)
@ -450,7 +450,7 @@ SdfReader::timingCheck(TimingRole *role,
}
void
SdfReader::timingCheck1(TimingRole *role,
SdfReader::timingCheck1(const TimingRole *role,
Port *data_port,
SdfPortSpec *data_edge,
Port *clk_port,
@ -498,7 +498,7 @@ SdfReader::timingCheck1(TimingRole *role,
network_->cellName(instance_),
network_->name(data_port),
network_->name(clk_port),
role->asString());
role->to_string().c_str());
}
}
}
@ -509,7 +509,7 @@ SdfReader::annotateCheckEdges(Pin *data_pin,
SdfPortSpec *data_edge,
Pin *clk_pin,
SdfPortSpec *clk_edge,
TimingRole *sdf_role,
const TimingRole *sdf_role,
SdfTriple *triple,
bool match_generic)
{
@ -600,8 +600,8 @@ SdfReader::timingCheckSetupHold1(SdfPortSpec *data_edge,
SdfPortSpec *clk_edge,
SdfTriple *setup_triple,
SdfTriple *hold_triple,
TimingRole *setup_role,
TimingRole *hold_role)
const TimingRole *setup_role,
const TimingRole *hold_role)
{
const string *data_port_name = data_edge->port();
const string *clk_port_name = clk_edge->port();
@ -754,7 +754,7 @@ SdfReader::setEdgeArcDelaysCondUse(Edge *edge,
float **values = triple->values();
float *value_min = values[triple_min_index_];
float *value_max = values[triple_max_index_];
MinMax *min, *max;
const MinMax *min, *max;
if (cond_use_ == MinMaxAll::min()) {
min = MinMax::min();
max = MinMax::min();
@ -826,7 +826,7 @@ SdfReader::condMatch(const string *sdf_cond,
}
SdfPortSpec *
SdfReader::makePortSpec(Transition *tr,
SdfReader::makePortSpec(const Transition *tr,
const string *port,
const string *cond)
{

14
sdf/SdfReaderPvt.hh
View File

@ -92,7 +92,7 @@ public:
SdfTripleSeq *triples,
const string *cond,
bool condelse);
void timingCheck(TimingRole *role,
void timingCheck(const TimingRole *role,
SdfPortSpec *data_edge,
SdfPortSpec *clk_edge,
SdfTriple *triple);
@ -112,8 +112,8 @@ public:
SdfPortSpec *clk_edge,
SdfTriple *setup_triple,
SdfTriple *hold_triple,
TimingRole *setup_role,
TimingRole *hold_role);
const TimingRole *setup_role,
const TimingRole *hold_role);
void timingCheckNochange(SdfPortSpec *data_edge,
SdfPortSpec *clk_edge,
SdfTriple *before_triple,
@ -132,7 +132,7 @@ public:
void deleteTriple(SdfTriple *triple);
SdfTripleSeq *makeTripleSeq();
void deleteTripleSeq(SdfTripleSeq *triples);
SdfPortSpec *makePortSpec(Transition *tr,
SdfPortSpec *makePortSpec(const Transition *tr,
const string *port,
const string *cond);
SdfPortSpec *makeCondPortSpec(const string *cond_port);
@ -160,14 +160,14 @@ private:
const char *filename);
Edge *findCheckEdge(Pin *from_pin,
Pin *to_pin,
TimingRole *sdf_role,
const TimingRole *sdf_role,
const string *cond_start,
const string *cond_end);
Edge *findWireEdge(Pin *from_pin,
Pin *to_pin);
bool condMatch(const string *sdf_cond,
const char *lib_cond);
void timingCheck1(TimingRole *role,
void timingCheck1(const TimingRole *role,
Port *data_port,
SdfPortSpec *data_edge,
Port *clk_port,
@ -177,7 +177,7 @@ private:
SdfPortSpec *data_edge,
Pin *clk_pin,
SdfPortSpec *clk_edge,
TimingRole *sdf_role,
const TimingRole *sdf_role,
SdfTriple *triple,
bool match_generic);
Pin *findPin(const string *name);

18
sdf/SdfWriter.cc
View File

@ -104,7 +104,7 @@ protected:
const char *sdfEdge(const Transition *tr);
void writeArcDelays(Edge *edge);
void writeSdfTriple(RiseFallMinMax &delays,
RiseFall *rf);
const RiseFall *rf);
void writeSdfTriple(float min,
float max);
void writeSdfDelay(double delay);
@ -176,11 +176,13 @@ SdfWriter::write(const char *filename,
timescale_ = default_lib->units()->timeUnit()->scale();
corner_ = corner;
MinMax *min_max;
const MinMax *min_max;
const DcalcAnalysisPt *dcalc_ap;
min_max = MinMax::min();
dcalc_ap = corner_->findDcalcAnalysisPt(min_max);
arc_delay_min_index_ = dcalc_ap->index();
min_max = MinMax::max();
dcalc_ap = corner_->findDcalcAnalysisPt(min_max);
arc_delay_max_index_ = dcalc_ap->index();
@ -376,7 +378,7 @@ SdfWriter::writeIopaths(const Instance *inst,
VertexOutEdgeIterator edge_iter(from_vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
if (role == TimingRole::combinational()
|| role == TimingRole::tristateEnable()
|| role == TimingRole::regClkToQ()
@ -437,7 +439,7 @@ SdfWriter::writeArcDelays(Edge *edge)
RiseFallMinMax delays;
TimingArcSet *arc_set = edge->timingArcSet();
for (TimingArc *arc : arc_set->arcs()) {
RiseFall *rf = arc->toEdge()->asRiseFall();
const RiseFall *rf = arc->toEdge()->asRiseFall();
ArcDelay min_delay = graph_->arcDelay(edge, arc, arc_delay_min_index_);
delays.setValue(rf, MinMax::min(), delayAsFloat(min_delay));
@ -470,7 +472,7 @@ SdfWriter::writeArcDelays(Edge *edge)
void
SdfWriter::writeSdfTriple(RiseFallMinMax &delays,
RiseFall *rf)
const RiseFall *rf)
{
float min = delays.value(rf, MinMax::min());
float max = delays.value(rf, MinMax::max());
@ -513,7 +515,7 @@ SdfWriter::writeTimingChecks(const Instance *inst,
VertexOutEdgeIterator edge_iter(vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
const char *sdf_check = nullptr;
if (role == TimingRole::setup())
sdf_check = "SETUP";
@ -590,8 +592,8 @@ SdfWriter::writeCheck(Edge *edge,
TimingArc *arcs[RiseFall::index_count][RiseFall::index_count] =
{{nullptr, nullptr}, {nullptr, nullptr}};
for (TimingArc *arc : arc_set->arcs()) {
RiseFall *clk_rf = arc->fromEdge()->asRiseFall();
RiseFall *data_rf = arc->toEdge()->asRiseFall();;
const RiseFall *clk_rf = arc->fromEdge()->asRiseFall();
const RiseFall *data_rf = arc->toEdge()->asRiseFall();;
arcs[clk_rf->index()][data_rf->index()] = arc;
}

11
search/Bfs.cc
View File

@ -89,7 +89,7 @@ BfsIterator::clear()
}
void
BfsIterator::reportEntries(const Network *network)
BfsIterator::reportEntries()
{
Level level = first_level_;
while (levelLessOrEqual(level, last_level_)) {
@ -98,7 +98,7 @@ BfsIterator::reportEntries(const Network *network)
report_->reportLine("Level %d", level);
for (Vertex *vertex : level_vertices) {
if (vertex)
report_->reportLine(" %s", vertex->name(network));
report_->reportLine(" %s", vertex->to_string(this).c_str());
}
}
incrLevel(level);
@ -262,7 +262,8 @@ BfsIterator::findNext(Level to_level)
void
BfsIterator::enqueue(Vertex *vertex)
{
debugPrint(debug_, "bfs", 2, "enqueue %s", vertex->name(sdc_network_));
debugPrint(debug_, "bfs", 2, "enqueue %s",
vertex->to_string(this).c_str());
if (!vertex->bfsInQueue(bfs_index_)) {
Level level = vertex->level();
LockGuard lock(queue_lock_);
@ -295,12 +296,12 @@ BfsIterator::checkInQueue(Vertex *vertex)
if (vertex->bfsInQueue(bfs_index_))
return;
else
printf("extra %s\n", vertex->name(sdc_network_));
printf("extra %s\n", vertex->to_string(this).c_str());
}
}
}
if (vertex->bfsInQueue(bfs_index_))
printf("missing %s\n", vertex->name(sdc_network_));
printf("missing %s\n", vertex->to_string(this).c_str());
}
void

4
search/CheckMaxSkews.cc
View File

@ -195,8 +195,8 @@ CheckMaxSkews:: visitMaxSkewChecks(Vertex *vertex,
Vertex *ref_vertex = edge->from(graph);
TimingArcSet *arc_set = edge->timingArcSet();
for (TimingArc *arc : arc_set->arcs()) {
RiseFall *clk_rf = arc->fromEdge()->asRiseFall();
RiseFall *ref_rf = arc->toEdge()->asRiseFall();
const RiseFall *clk_rf = arc->fromEdge()->asRiseFall();
const RiseFall *ref_rf = arc->toEdge()->asRiseFall();
VertexPathIterator clk_path_iter(vertex, clk_rf, clk_min_max, search);
while (clk_path_iter.hasNext()) {
Path *clk_path = clk_path_iter.next();

10
search/CheckMinPulseWidths.cc
View File

@ -245,12 +245,12 @@ visitMinPulseWidthChecks(MinPulseWidthCheckVisitor *visitor)
{
Graph *graph = sta_->graph();
Debug *debug = sta_->debug();
Network *sdc_network = sta_->network();
VertexIterator vertex_iter(graph);
while (vertex_iter.hasNext()) {
Vertex *vertex = vertex_iter.next();
if (isClkEnd(vertex, graph)) {
debugPrint(debug, "mpw", 1, "check mpw %s", vertex->name(sdc_network));
debugPrint(debug, "mpw", 1, "check mpw %s",
vertex->to_string(sta_).c_str());
visitMinPulseWidthChecks(vertex, visitor);
}
}
@ -343,16 +343,16 @@ MinPulseWidthCheck::closePath(const StaState *sta) const
open_tag->states(),
false, sta);
debugPrint(sta->debug(), "mpw", 3, " open %s",
open_tag->asString(sta));
open_tag->to_string(sta).c_str());
debugPrint(sta->debug(), "mpw", 3, " close %s",
close_tag.asString(sta));
close_tag.to_string(sta).c_str());
VertexPathIterator close_iter(open_path_->vertex(sta), close_rf,
close_ap, sta);
while (close_iter.hasNext()) {
Path *close_path = close_iter.next();
if (tagMatchNoPathAp(close_path->tag(sta), &close_tag)) {
debugPrint(sta->debug(), "mpw", 3, " match %s",
close_path->tag(sta)->asString(sta));
close_path->tag(sta)->to_string(sta).c_str());
return close_path;
}
}

4
search/ClkInfo.cc
View File

@ -136,7 +136,7 @@ ClkInfo::asString(const StaState *sta) const
string result;
PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index_);
result += path_ap->pathMinMax()->asString();
result += path_ap->pathMinMax()->to_string();
result += "/";
result += std::to_string(path_ap_index_);
@ -174,7 +174,7 @@ ClkInfo::clock() const
return nullptr;
}
RiseFall *
const RiseFall *
ClkInfo::pulseClkSense() const
{
if (is_pulse_clk_)

2
search/ClkInfo.hh
View File

@ -56,7 +56,7 @@ public:
bool isPropagated() const { return is_propagated_; }
const Pin *genClkSrc() const { return gen_clk_src_; }
bool isPulseClk() const { return is_pulse_clk_; }
RiseFall *pulseClkSense() const;
const RiseFall *pulseClkSense() const;
int pulseClkSenseTrIndex() const { return pulse_clk_sense_; }
float latency() const { return latency_; }
Arrival &insertion() { return insertion_; }

14
search/ClkSkew.cc
View File

@ -178,7 +178,7 @@ ClkSkew::crpr(const StaState *sta)
float
ClkSkew::uncertainty(const StaState *sta)
{
TimingRole *check_role = (src_path_->minMax(sta) == SetupHold::max())
const TimingRole *check_role = (src_path_->minMax(sta) == SetupHold::max())
? TimingRole::setup()
: TimingRole::hold();
// Uncertainty decreases slack, but increases skew.
@ -255,7 +255,7 @@ ClkSkews::reportClkSkew(ClkSkew &clk_skew,
report_->reportLine("%7s source latency %s %s",
time_unit->asString(src_latency, digits),
sdc_network_->pathName(src_path->pin(this)),
src_path->transition(this)->asString());
src_path->transition(this)->to_string().c_str());
if (src_internal_clk_latency != 0.0)
report_->reportLine("%7s source internal clock delay",
time_unit->asString(src_internal_clk_latency, digits));
@ -265,7 +265,7 @@ ClkSkews::reportClkSkew(ClkSkew &clk_skew,
report_->reportLine("%7s target latency %s %s",
time_unit->asString(-tgt_latency, digits),
sdc_network_->pathName(tgt_path->pin(this)),
tgt_path->transition(this)->asString());
tgt_path->transition(this)->to_string().c_str());
if (tgt_internal_clk_latency != 0.0)
report_->reportLine("%7s target internal clock delay",
time_unit->asString(-tgt_internal_clk_latency, digits));
@ -391,7 +391,7 @@ ClkSkews::findClkSkewFrom(Vertex *src_vertex,
VertexInEdgeIterator edge_iter(end, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
if (role->isTimingCheck()
&& ((setup_hold_ == SetupHold::max()
&& role->genericRole() == TimingRole::setup())
@ -441,10 +441,10 @@ ClkSkews::findClkSkew(Vertex *src_vertex,
debugPrint(debug_, "clk_skew", 2,
"%s %s %s -> %s %s %s crpr = %s skew = %s",
network_->pathName(src_path->pin(this)),
src_path->transition(this)->asString(),
src_path->transition(this)->to_string().c_str(),
time_unit->asString(probe.srcLatency(this)),
network_->pathName(tgt_path->pin(this)),
tgt_path->transition(this)->asString(),
tgt_path->transition(this)->to_string().c_str(),
time_unit->asString(probe.tgtLatency(this)),
delayAsString(probe.crpr(this), this),
time_unit->asString(probe.skew()));
@ -499,7 +499,7 @@ FanOutSrchPred::FanOutSrchPred(const StaState *sta) :
bool
FanOutSrchPred::searchThru(Edge *edge)
{
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
return SearchPred1::searchThru(edge)
&& (role == TimingRole::wire()
|| role == TimingRole::combinational()

15
search/Corner.cc
View File

@ -144,14 +144,14 @@ Corners::makeParasiticAnalysisPts(bool per_corner)
parasitic_analysis_pts_.resize(corners_.size() * MinMax::index_count);
for (Corner *corner : corners_) {
corner->setParasiticAnalysisPtcount(MinMax::index_count);
for (MinMax *min_max : MinMax::range()) {
for (const MinMax *min_max : MinMax::range()) {
int mm_index = min_max->index();
int ap_index = corner->index() * MinMax::index_count + mm_index;
int ap_index_max = corner->index() * MinMax::index_count
+ MinMax::max()->index();
string ap_name = corner->name();
ap_name += "_";
ap_name += min_max->asString();
ap_name += min_max->to_string();
ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(ap_name.c_str(),
ap_index, ap_index_max);
parasitic_analysis_pts_[ap_index] = ap;
@ -163,10 +163,10 @@ Corners::makeParasiticAnalysisPts(bool per_corner)
// shared corner, per min/max
parasitic_analysis_pts_.resize(MinMax::index_count);
int ap_index_max = MinMax::max()->index();
for (MinMax *min_max : MinMax::range()) {
for (const MinMax *min_max : MinMax::range()) {
int mm_index = min_max->index();
int ap_index = mm_index;
ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(min_max->asString(),
ParasiticAnalysisPt *ap = new ParasiticAnalysisPt(min_max->to_string().c_str(),
ap_index,
ap_index_max);
parasitic_analysis_pts_[ap_index] = ap;
@ -360,17 +360,12 @@ Corners::findPathAnalysisPt(PathAPIndex path_index) const
Corner::Corner(const char *name,
int index) :
name_(stringCopy(name)),
name_(name),
index_(index),
path_analysis_pts_(MinMax::index_count)
{
}
Corner::~Corner()
{
stringDelete(name_);
}
ParasiticAnalysisPt *
Corner::findParasiticAnalysisPt(const MinMax *min_max) const
{

14
search/FindRegister.cc
View File

@ -76,7 +76,7 @@ FindRegClkPred::searchFrom(const Vertex *from_vertex)
bool
FindRegClkPred::searchThru(Edge *edge)
{
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
return (role->isWire()
|| role == TimingRole::combinational())
&& SearchPred1::searchThru(edge);
@ -281,13 +281,13 @@ FindRegVisitor::findInferedSequential(LibertyCell *cell,
const RiseFall *clk_rf1 = clk_rf->asRiseFall();
for (TimingArcSet *arc_set : cell->timingArcSets()) {
TimingArc *arc = *arc_set->arcs().begin();
RiseFall *arc_clk_rf = arc->fromEdge()->asRiseFall();
const RiseFall *arc_clk_rf = arc->fromEdge()->asRiseFall();
bool tr_matches = (clk_rf == RiseFallBoth::riseFall()
|| (arc_clk_rf == clk_rf1
&& clk_sense == TimingSense::positive_unate)
|| (arc_clk_rf == clk_rf1->opposite()
&& clk_sense == TimingSense::negative_unate));
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (tr_matches
&& ((role == TimingRole::regClkToQ()
&& edge_triggered)
@ -306,7 +306,7 @@ FindRegVisitor::hasTimingCheck(LibertyCell *cell,
LibertyPort *d)
{
for (TimingArcSet *arc_set : cell->timingArcSets(clk, d)) {
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (role->isTimingCheck())
return true;
}
@ -542,7 +542,7 @@ FindRegClkPins::matchPin(Pin *pin)
LibertyPort *port = network_->libertyPort(pin);
LibertyCell *cell = port->libertyCell();
for (TimingArcSet *arc_set : cell->timingArcSets(port, nullptr)) {
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (role == TimingRole::regClkToQ()
|| role == TimingRole::latchEnToQ())
return true;
@ -598,7 +598,7 @@ FindRegAsyncPins::matchPin(Pin *pin)
LibertyPort *port = network_->libertyPort(pin);
LibertyCell *cell = port->libertyCell();
for (TimingArcSet *arc_set : cell->timingArcSets(port, nullptr)) {
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (role == TimingRole::regSetClr())
return true;
}
@ -645,7 +645,7 @@ FindRegOutputPins::matchPin(Pin *pin)
LibertyPort *port = network_->libertyPort(pin);
LibertyCell *cell = port->libertyCell();
for (TimingArcSet *arc_set : cell->timingArcSets(nullptr, port)) {
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (role == TimingRole::regClkToQ()
|| role == TimingRole::latchEnToQ()
|| role == TimingRole::latchDtoQ())

4
search/GatedClk.cc
View File

@ -238,11 +238,11 @@ GatedClk::functionClkOperands(FuncExpr *root_expr,
}
}
RiseFall *
const RiseFall *
GatedClk::gatedClkActiveTrans(LogicValue active_value,
const MinMax *min_max) const
{
RiseFall *leading_rf;
const RiseFall *leading_rf;
switch (active_value) {
case LogicValue::one:
case LogicValue::unknown:

4
search/GatedClk.hh
View File

@ -46,8 +46,8 @@ public:
void gatedClkEnables(Vertex *clk_vertex,
// Return value.
PinSet &enable_pins);
RiseFall *gatedClkActiveTrans(LogicValue active_value,
const MinMax *min_max) const;
const RiseFall *gatedClkActiveTrans(LogicValue active_value,
const MinMax *min_max) const;
protected:
void isClkGatingFunc(FuncExpr *func,

19
search/Genclks.cc
View File

@ -250,7 +250,7 @@ bool
GenClkMasterSearchPred::searchThru(Edge *edge)
{
const Sdc *sdc = sta_->sdc();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
// Propagate clocks through constants.
return !(edge->role()->isTimingCheck()
|| edge->isDisabledLoop()
@ -418,7 +418,7 @@ Genclks::findFanin(Clock *gclk,
if (!fanins->hasKey(vertex)) {
fanins->insert(vertex);
debugPrint(debug_, "genclk", 2, "gen clk %s fanin %s",
gclk->name(), vertex->name(sdc_network_));
gclk->name(), vertex->to_string(this).c_str());
iter.enqueueAdjacentVertices(vertex);
}
}
@ -627,9 +627,8 @@ Genclks::findLatchFdbkEdges(Vertex *from_vertex,
Edge *edge = edge_iter.next();
Vertex *to_vertex = edge->to(graph_);
if (path_vertices.hasKey(to_vertex)) {
debugPrint(debug_, "genclk", 2, " found feedback edge %s -> %s",
from_vertex->name(sdc_network_),
to_vertex->name(sdc_network_));
debugPrint(debug_, "genclk", 2, " found feedback edge %s",
edge->to_string(this).c_str());
if (fdbk_edges == nullptr)
fdbk_edges = new EdgeSet;
fdbk_edges->insert(edge);
@ -822,7 +821,7 @@ GenclkSrcArrivalVisitor::visit(Vertex *vertex)
{
Genclks *genclks = search_->genclks();
debugPrint(debug_, "genclk", 2, "find gen clk insert arrival %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
tag_bldr_->init(vertex);
has_fanin_one_ = graph_->hasFaninOne(vertex);
genclks->copyGenClkSrcPaths(vertex, tag_bldr_);
@ -907,7 +906,7 @@ Genclks::recordSrcPaths(Clock *gclk)
if (src_clk_edge
&& matchesSrcFilter(path, gclk)) {
const EarlyLate *early_late = path->minMax(this);
RiseFall *src_clk_rf = src_clk_edge->transition();
const RiseFall *src_clk_rf = src_clk_edge->transition();
const RiseFall *rf = path->transition(this);
bool inverting_path = (rf != src_clk_rf);
const PathAnalysisPt *path_ap = path->pathAnalysisPt(this);
@ -924,8 +923,8 @@ Genclks::recordSrcPaths(Clock *gclk)
this))) {
debugPrint(debug_, "genclk", 2, " %s insertion %s %s %s",
network_->pathName(gclk_pin),
early_late->asString(),
rf->asString(),
early_late->to_string().c_str(),
rf->to_string().c_str(),
delayAsString(path->arrival(), this));
delete src_path.prevPath();
src_path = *path;
@ -1037,7 +1036,7 @@ Genclks::updateSrcPathPrevs()
p = p->prevPath();
}
debugPrint(debug_, "genclk", 3, "repaired src path prev %s",
src_path.name(this));
src_path.to_string(this).c_str());
}
}
}

4
search/Latches.cc
View File

@ -251,7 +251,7 @@ Latches::latchEnableOtherPath(const Path *path,
const ClockEdge *clk_edge = path->clkEdge(this);
const ClockEdge *other_clk_edge =
path->clkInfo(this)->isPulseClk() ? clk_edge:clk_edge->opposite();
RiseFall *other_rf = path->transition(this)->opposite();
const RiseFall *other_rf = path->transition(this)->opposite();
VertexPathIterator path_iter(vertex, other_rf, tgt_clk_path_ap, this);
while (path_iter.hasNext()) {
Path *path = path_iter.next();
@ -366,7 +366,7 @@ Latches::latchOutArrival(const Path *data_path,
en_clk_info->uncertainties(),
path_ap,
crpr_clk_path);
RiseFall *q_rf = d_q_arc->toEdge()->asRiseFall();
const RiseFall *q_rf = d_q_arc->toEdge()->asRiseFall();
ExceptionStateSet *states = nullptr;
// Latch data pin is a valid exception -from pin.
if (sdc_->exceptionFromStates(data_path->pin(this),

44
search/Levelize.cc
View File

@ -157,7 +157,8 @@ Levelize::findRoots()
Vertex *vertex = vertex_iter.next();
setLevel(vertex, 0);
if (isRoot(vertex)) {
debugPrint(debug_, "levelize", 2, "root %s", vertex->name(sdc_network_));
debugPrint(debug_, "levelize", 2, "root %s",
vertex->to_string(this).c_str());
roots_->insert(vertex);
if (hasFanout(vertex, search_pred_, graph_))
// Color roots with no fanout black so that they are
@ -219,7 +220,7 @@ Levelize::visit(Vertex *vertex,
{
Pin *from_pin = vertex->pin();
debugPrint(debug_, "levelize", 3, "level %d %s",
level, vertex->name(sdc_network_));
level, vertex->to_string(this).c_str());
vertex->setColor(LevelColor::gray);
setLevel(vertex, level);
max_level_ = max(level, max_level_);
@ -269,8 +270,8 @@ Levelize::reportPath(EdgeSeq &path) const
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
if (first_edge)
report_->reportLine(" %s", edge->from(graph_)->name(network_));
report_->reportLine(" %s", edge->to(graph_)->name(network_));
report_->reportLine(" %s", edge->from(graph_)->to_string(this).c_str());
report_->reportLine(" %s", edge->to(graph_)->to_string(this).c_str());
first_edge = false;
}
}
@ -279,10 +280,9 @@ void
Levelize::recordLoop(Edge *edge,
EdgeSeq &path)
{
debugPrint(debug_, "levelize", 2, "Loop edge %s -> %s (%s)",
edge->from(graph_)->name(sdc_network_),
edge->to(graph_)->name(sdc_network_),
edge->role()->asString());
debugPrint(debug_, "levelize", 2, "Loop edge %s (%s)",
edge->to_string(this).c_str(),
edge->role()->to_string().c_str());
// Do not record loops if they have been invalidated.
if (loops_) {
EdgeSeq *loop_edges = loopEdges(path, edge);
@ -313,16 +313,14 @@ Levelize::loopEdges(EdgeSeq &path,
if (from_pin == loop_pin)
copy = true;
if (copy) {
debugPrint(debug_, "loop", 2, " %s -> %s",
edge->from(graph_)->name(sdc_network_),
edge->to(graph_)->name(sdc_network_));
debugPrint(debug_, "loop", 2, " %s",
edge->to_string(this).c_str());
loop_edges->push_back(edge);
loop_edges_.insert(edge);
}
}
debugPrint(debug_, "loop", 2, " %s -> %s",
closing_edge->from(graph_)->name(sdc_network_),
closing_edge->to(graph_)->name(sdc_network_));
debugPrint(debug_, "loop", 2, " %s",
closing_edge->to_string(this).c_str());
loop_edges->push_back(closing_edge);
loop_edges_.insert(closing_edge);
return loop_edges;
@ -388,7 +386,7 @@ void
Levelize::invalidFrom(Vertex *vertex)
{
debugPrint(debug_, "levelize", 1, "level invalid from %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
VertexInEdgeIterator edge_iter(vertex, graph_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
@ -410,7 +408,7 @@ void
Levelize::relevelizeFrom(Vertex *vertex)
{
debugPrint(debug_, "levelize", 1, "invalid relevelize from %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
relevelize_from_->insert(vertex);
levels_valid_ = false;
}
@ -440,7 +438,7 @@ Levelize::relevelize()
{
for (Vertex *vertex : *relevelize_from_) {
debugPrint(debug_, "levelize", 1, "relevelize from %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
if (search_pred_->searchFrom(vertex)) {
if (isRoot(vertex)) {
setLevel(vertex, 0);
@ -490,7 +488,7 @@ GraphLoop::isCombinational() const
EdgeSeq::Iterator edge_iter(edges_);
while (edge_iter.hasNext()) {
Edge *edge = edge_iter.next();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
if (!(role == TimingRole::wire()
|| role == TimingRole::combinational()
|| role == TimingRole::tristateEnable()
@ -501,17 +499,17 @@ GraphLoop::isCombinational() const
}
void
GraphLoop::report(Report *report,
Network *network,
Graph *graph) const
GraphLoop::report(const StaState *sta) const
{
Graph *graph = sta->graph();
Report *report = sta->report();
bool first_edge = true;
EdgeSeq::Iterator loop_edge_iter(edges_);
while (loop_edge_iter.hasNext()) {
Edge *edge = loop_edge_iter.next();
if (first_edge)
report->reportLine(" %s", edge->from(graph)->name(network));
report->reportLine(" %s", edge->to(graph)->name(network));
report->reportLine(" %s", edge->from(graph)->to_string(sta).c_str());
report->reportLine(" %s", edge->to(graph)->to_string(graph).c_str());
first_edge = false;
}
}

4
search/Levelize.hh
View File

@ -104,9 +104,7 @@ public:
~GraphLoop();
EdgeSeq *edges() { return edges_; }
bool isCombinational() const;
void report(Report *report,
Network *network,
Graph *graph) const;
void report(const StaState *sta) const;
private:
EdgeSeq *edges_;

28
search/MakeTimingModel.cc
View File

@ -146,7 +146,7 @@ MakeTimingModel::makeLibrary()
LibertyLibrary *default_lib = network_->defaultLibertyLibrary();
*library_->units() = *default_lib->units();
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
library_->setInputThreshold(rf, default_lib->inputThreshold(rf));
library_->setOutputThreshold(rf, default_lib->outputThreshold(rf));
library_->setSlewLowerThreshold(rf, default_lib->slewLowerThreshold(rf));
@ -292,7 +292,7 @@ MakeEndTimingArcs::visit(PathEnd *path_end)
network->pathName(src_path->pin(sta_)),
tgt_clk_edge->name(),
path_end->typeName(),
min_max->asString(),
min_max->to_string().c_str(),
delayAsString(margin, sta_));
if (debug->check("make_timing_model", 3))
sta_->reportPathEnd(path_end);
@ -335,8 +335,8 @@ MakeTimingModel::findTimingFromInput(Port *input_port)
if (!sta_->isClockSrc(input_pin)) {
MakeEndTimingArcs end_visitor(sta_);
OutputPinDelays output_delays;
for (RiseFall *input_rf : RiseFall::range()) {
RiseFallBoth *input_rf1 = input_rf->asRiseFallBoth();
for (const RiseFall *input_rf : RiseFall::range()) {
const RiseFallBoth *input_rf1 = input_rf->asRiseFallBoth();
sta_->setInputDelay(input_pin, input_rf1,
sdc_->defaultArrivalClock(),
sdc_->defaultArrivalClockEdge()->transition(),
@ -398,10 +398,10 @@ MakeTimingModel::makeSetupHoldTimingArcs(const Pin *input_pin,
const ClockEdgeDelays &clk_margins)
{
for (const auto& [clk_edge, margins] : clk_margins) {
for (MinMax *min_max : MinMax::range()) {
for (const MinMax *min_max : MinMax::range()) {
bool setup = (min_max == MinMax::max());
TimingArcAttrsPtr attrs = nullptr;
for (RiseFall *input_rf : RiseFall::range()) {
for (const RiseFall *input_rf : RiseFall::range()) {
float margin;
bool exists;
margins.value(input_rf, min_max, margin, exists);
@ -426,8 +426,10 @@ MakeTimingModel::makeSetupHoldTimingArcs(const Pin *input_pin,
for (const Pin *clk_pin : clk_edge->clock()->pins()) {
LibertyPort *clk_port = modelPort(clk_pin);
if (clk_port) {
RiseFall *clk_rf = clk_edge->transition();
TimingRole *role = setup ? TimingRole::setup() : TimingRole::hold();
const RiseFall *clk_rf = clk_edge->transition();
const TimingRole *role = setup
? TimingRole::setup()
: TimingRole::hold();
lib_builder_->makeFromTransitionArcs(cell_, clk_port,
input_port, nullptr,
clk_rf, role, attrs);
@ -444,8 +446,8 @@ MakeTimingModel::makeInputOutputTimingArcs(const Pin *input_pin,
{
for (const auto& [output_pin, output_delays] : output_pin_delays) {
TimingArcAttrsPtr attrs = nullptr;
for (RiseFall *output_rf : RiseFall::range()) {
MinMax *min_max = MinMax::max();
for (const RiseFall *output_rf : RiseFall::range()) {
const MinMax *min_max = MinMax::max();
float delay;
bool exists;
output_delays.delays.value(output_rf, min_max, delay, exists);
@ -501,9 +503,9 @@ MakeTimingModel::findClkedOutputPaths()
for (const Pin *clk_pin : clk_edge->clock()->pins()) {
LibertyPort *clk_port = modelPort(clk_pin);
if (clk_port) {
RiseFall *clk_rf = clk_edge->transition();
const RiseFall *clk_rf = clk_edge->transition();
TimingArcAttrsPtr attrs = nullptr;
for (RiseFall *output_rf : RiseFall::range()) {
for (const RiseFall *output_rf : RiseFall::range()) {
float delay = delays.value(output_rf, min_max_) - clk_edge->time();
TimingModel *gate_model = makeGateModelTable(output_pin, delay, output_rf);
if (attrs == nullptr)
@ -582,7 +584,7 @@ MakeTimingModel::makeClkTreePaths(LibertyPort *lib_port,
}
if (attrs) {
attrs->setTimingSense(sense);
TimingRole *role = (min_max == MinMax::min())
const TimingRole *role = (min_max == MinMax::min())
? TimingRole::clockTreePathMin()
: TimingRole::clockTreePathMax();
lib_builder_->makeClockTreePathArcs(cell_, lib_port, role, min_max, attrs);

2
search/MakeTimingModelPvt.hh
View File

@ -108,7 +108,7 @@ private:
const Corner *corner_;
LibertyLibrary *library_;
LibertyCell *cell_;
MinMax *min_max_;
const MinMax *min_max_;
LibertyBuilder *lib_builder_;
// Output driver table model template to model template.
Map<const TableTemplate*, TableTemplate*> template_map_;

28
search/Path.cc
View File

@ -200,24 +200,16 @@ Path::init(Vertex *vertex,
is_enum_ = false;
}
const char *
Path::name(const StaState *sta) const
string
Path::to_string(const StaState *sta) const
{
const Network *network = sta->network();
Vertex *vertex = this->vertex(sta);
if (vertex) {
const char *vertex_name = vertex->name(network);
const char *tr_str = transition(sta)->asString();
const PathAnalysisPt *path_ap = pathAnalysisPt(sta);
int ap_index = path_ap->index();
const char *min_max = path_ap->pathMinMax()->asString();
TagIndex tag_index = tagIndex(sta);
return stringPrintTmp("%s %s %s/%d %d",
vertex_name, tr_str, min_max,
ap_index, tag_index);
}
else
return "NULL";
const PathAnalysisPt *path_ap = pathAnalysisPt(sta);
return stringPrintTmp("%s %s %s/%d %d",
vertex(sta)->to_string(sta).c_str(),
transition(sta)->to_string().c_str(),
path_ap->pathMinMax()->to_string().c_str(),
path_ap->index(),
tagIndex(sta));
}
bool
@ -466,7 +458,7 @@ Path::checkPrevPath(const StaState *sta) const
if (prev_vertex != prev_edge_vertex) {
Network *network = sta->network();
sta->report()->reportLine("path %s prev path corrupted %s vs %s.",
name(sta),
to_string(sta).c_str(),
prev_vertex->name(network),
prev_edge_vertex->name(network));
}

9
search/PathAnalysisPt.cc
View File

@ -42,6 +42,15 @@ PathAnalysisPt::PathAnalysisPt(Corner *corner,
{
}
string
PathAnalysisPt::to_string() const
{
string name = corner_->name();
name += '/';
name += path_min_max_->to_string();
return name;
}
void
PathAnalysisPt::setTgtClkAnalysisPt(PathAnalysisPt *path_ap)
{

26
search/PathEnd.cc
View File

@ -230,7 +230,7 @@ PathEnd::targetClkMcpAdjustment(const StaState *) const
return 0.0;
}
TimingRole *
const TimingRole *
PathEnd::checkRole(const StaState *) const
{
return nullptr;
@ -381,7 +381,7 @@ PathEnd::checkTgtClkUncertainty(const Path *tgt_clk_path,
const TimingRole *check_role,
const StaState *sta)
{
MinMax *min_max = check_role->pathMinMax();
const MinMax *min_max = check_role->pathMinMax();
ClockUncertainties *uncertainties = nullptr;
if (tgt_clk_path && tgt_clk_path->isClock(sta))
uncertainties = tgt_clk_path->clkInfo(sta)->uncertainties();
@ -985,7 +985,7 @@ PathEndCheck::reportShort(const ReportPath *report) const
report->reportShort(this);
}
TimingRole *
const TimingRole *
PathEndCheck::checkRole(const StaState *) const
{
return check_edge_->role();
@ -1181,7 +1181,7 @@ PathEndLatchCheck::sourceClkOffset(const StaState *sta) const
sta);
}
TimingRole *
const TimingRole *
PathEndLatchCheck::checkRole(const StaState *sta) const
{
if (clk_path_->clkInfo(sta)->isPulseClk())
@ -1378,7 +1378,7 @@ PathEnd::outputDelayMargin(OutputDelay *output_delay,
return -margin;
}
TimingRole *
const TimingRole *
PathEndOutputDelay::checkRole(const StaState *sta) const
{
if (path_->minMax(sta) == MinMax::max())
@ -1456,7 +1456,7 @@ PathEndOutputDelay::tgtClkDelay(const ClockEdge *tgt_clk_edge,
const PathAnalysisPt *path_ap = path_->pathAnalysisPt(sta);
const MinMax *latency_min_max = path_ap->tgtClkAnalysisPt()->pathMinMax();
Clock *tgt_clk = tgt_clk_edge->clock();
RiseFall *tgt_clk_rf = tgt_clk_edge->transition();
const RiseFall *tgt_clk_rf = tgt_clk_edge->transition();
if (!output_delay_->sourceLatencyIncluded())
insertion = sta->search()->clockInsertion(tgt_clk,
tgt_clk->defaultPin(),
@ -1510,7 +1510,7 @@ PathEndOutputDelay::exceptPathCmp(const PathEnd *path_end,
PathEndGatedClock::PathEndGatedClock(Path *gating_ref,
Path *clk_path,
TimingRole *check_role,
const TimingRole *check_role,
MultiCyclePath *mcp,
ArcDelay margin,
const StaState *) :
@ -1522,7 +1522,7 @@ PathEndGatedClock::PathEndGatedClock(Path *gating_ref,
PathEndGatedClock::PathEndGatedClock(Path *gating_ref,
Path *clk_path,
TimingRole *check_role,
const TimingRole *check_role,
MultiCyclePath *mcp,
ArcDelay margin,
Crpr crpr,
@ -1552,7 +1552,7 @@ PathEndGatedClock::typeName() const
return "gated_clk";
}
TimingRole *
const TimingRole *
PathEndGatedClock::checkRole(const StaState *) const
{
return check_role_;
@ -1578,7 +1578,7 @@ PathEndGatedClock::exceptPathCmp(const PathEnd *path_end,
if (cmp == 0) {
const PathEndGatedClock *path_end2 =
dynamic_cast<const PathEndGatedClock*>(path_end);
TimingRole *check_role2 = path_end2->check_role_;
const TimingRole *check_role2 = path_end2->check_role_;
if (check_role_ == check_role2)
return 0;
else if (check_role_ < check_role2)
@ -1618,7 +1618,7 @@ PathEndDataCheck::clkPath(Path *path,
if (p->isClock(sta))
return p;
if (prev_arc) {
TimingRole *prev_role = prev_arc->role();
const TimingRole *prev_role = prev_arc->role();
if (prev_role == TimingRole::regClkToQ()
|| prev_role == TimingRole::latchEnToQ()) {
prev_path = p->prevPath();
@ -1705,7 +1705,7 @@ PathEndDataCheck::margin(const StaState *sta) const
return margin;
}
TimingRole *
const TimingRole *
PathEndDataCheck::checkRole(const StaState *sta) const
{
if (path_->minMax(sta) == MinMax::max())
@ -1856,7 +1856,7 @@ PathEndPathDelay::pathDelayMarginIsExternal() const
return check_arc_ == nullptr;
}
TimingRole *
const TimingRole *
PathEndPathDelay::checkRole(const StaState *sta) const
{
if (check_edge_)

28
search/PathEnum.cc
View File

@ -124,9 +124,9 @@ void
PathEnum::insert(PathEnd *path_end)
{
debugPrint(debug_, "path_enum", 1, "insert %s",
path_end->path()->name(this));
path_end->path()->to_string(this).c_str());
debugPrint(debug_, "path_enum", 2, "diversion %s %s %s",
path_end->path()->name(this),
path_end->path()->to_string(this).c_str(),
cmp_slack_ ? "slack" : "delay",
delayAsString(cmp_slack_ ? path_end->slack(this) :
path_end->dataArrivalTime(this), this));
@ -181,7 +181,7 @@ PathEnum::findNext()
if (debug_->check("path_enum", 2)) {
Path *path = path_end->path();
report_->reportLine("path_enum: next path %s delay %s slack %s",
path->name(this),
path->to_string(this).c_str(),
delayAsString(path_end->dataArrivalTime(this), this),
delayAsString(path_end->slack(this), this));
reportDiversionPath(div);
@ -202,7 +202,7 @@ PathEnum::findNext()
// so we are done with it.
debugPrint(debug_, "path_enum", 1,
"endpoint_path_count reached for %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
deleteDiversionPathEnd(div);
}
}
@ -217,7 +217,7 @@ PathEnum::reportDiversionPath(Diversion *div)
Path *after_div = div->divPath();
while (p) {
report_->reportLine("path_enum: %s %s%s",
p->name(this),
p->to_string(this).c_str(),
delayAsString(p->arrival(), this),
Path::equal(p, after_div, this) ? " <-diversion" : "");
if (network_->isLatchData(p->pin(this)))
@ -339,9 +339,9 @@ PathEnumFaninVisitor::visitFromToPath(const Pin *,
const PathAnalysisPt *path_ap)
{
debugPrint(debug_, "path_enum", 3, "visit fanin %s -> %s %s %s",
from_path->name(this),
to_vertex->name(network_),
to_rf->asString(),
from_path->to_string(this).c_str(),
to_vertex->to_string(this).c_str(),
to_rf->to_string().c_str(),
delayAsString(search_->deratedDelay(from_vertex, arc, edge,
false,path_ap), this));
// These paths fanin to before_div_ so we know to_vertex matches.
@ -412,15 +412,15 @@ PathEnumFaninVisitor::reportDiversion(const Edge *div_edge,
div_arc, path_ap);
Path *div_prev = before_div_->prevPath();
report_->reportLine("path_enum: diversion %s %s %s -> %s",
path->name(this),
path->to_string(this).c_str(),
path_enum_->cmp_slack_ ? "slack" : "delay",
delayAsString(path_delay, this),
delayAsString(div_delay, this));
report_->reportLine("path_enum: from %s -> %s",
div_prev->name(this),
before_div_->name(this));
div_prev->to_string(this).c_str(),
before_div_->to_string(this).c_str());
report_->reportLine("path_enum: to %s",
after_div->name(this));
after_div->to_string(this).c_str());
}
}
@ -597,8 +597,8 @@ PathEnum::updatePathHeadDelays(PathSeq &paths,
arc, edge, false, path_ap);
Arrival arrival = prev_arrival + arc_delay;
debugPrint(debug_, "path_enum", 5, "update arrival %s %s %s -> %s",
path->vertex(this)->name(network_),
path->tag(this)->asString(this),
path->vertex(this)->to_string(this).c_str(),
path->tag(this)->to_string(this).c_str(),
delayAsString(path->arrival(), this),
delayAsString(arrival, this));
path->setArrival(arrival);

2
search/PathExpanded.cc
View File

@ -188,7 +188,7 @@ PathExpanded::clkPath() const
const Path *start = startPath();
const TimingArc *prev_arc = startPrevArc();
if (start && prev_arc) {
TimingRole *role = prev_arc->role();
const TimingRole *role = prev_arc->role();
if (role == TimingRole::latchDtoQ()) {
Edge *prev_edge = start->prevEdge(sta_);
if (prev_edge && latches->isLatchDtoQ(prev_edge)) {

9
search/PathGroup.cc
View File

@ -716,7 +716,6 @@ void
MakePathEndsAll::vertexEnd(Vertex *)
{
Debug *debug = sta_->debug();
Network *network = sta_->network();
PathGroupEndsMap::Iterator group_iter(ends_);
while (group_iter.hasNext()) {
PathGroup *group;
@ -734,9 +733,9 @@ MakePathEndsAll::vertexEnd(Vertex *)
// PathEnum will peel the others.
if (!unique_ends.hasKey(path_end)) {
debugPrint(debug, "path_enum", 5, "insert %s %s %s %d",
path_end->vertex(sta_)->name(network),
path_end->vertex(sta_)->to_string(sta_).c_str(),
path_end->typeName(),
path_end->transition(sta_)->asString(),
path_end->transition(sta_)->to_string().c_str(),
path_end->path()->tag(sta_)->index());
// Give the group a copy of the path end because
// it may delete it during pruning.
@ -749,9 +748,9 @@ MakePathEndsAll::vertexEnd(Vertex *)
}
else
debugPrint(debug, "path_enum", 5, "prune %s %s %s %d",
path_end->vertex(sta_)->name(network),
path_end->vertex(sta_)->to_string(sta_).c_str(),
path_end->typeName(),
path_end->transition(sta_)->asString(),
path_end->transition(sta_)->to_string().c_str(),
path_end->path()->tag(sta_)->index());
}
// Clear ends for next vertex.

11
search/Property.cc
View File

@ -1147,12 +1147,7 @@ getProperty(Edge *edge,
Sta *sta)
{
if (stringEqual(property, "full_name")) {
Network *network = sta->cmdNetwork();
Graph *graph = sta->ensureGraph();
const char *from = edge->from(graph)->name(network);
const char *to = edge->to(graph)->name(network);
string full_name;
stringPrint(full_name, "%s -> %s", from, to);
string full_name = edge->to_string(sta);
return PropertyValue(full_name);
}
if (stringEqual(property, "delay_min_fall"))
@ -1164,7 +1159,7 @@ getProperty(Edge *edge,
else if (stringEqual(property, "delay_max_rise"))
return edgeDelayProperty(edge, RiseFall::rise(), MinMax::max(), sta);
else if (stringEqual(property, "sense"))
return PropertyValue(timingSenseString(edge->sense()));
return PropertyValue(to_string(edge->sense()));
else if (stringEqual(property, "from_pin"))
return PropertyValue(edge->from(sta->graph())->pin());
else if (stringEqual(property, "to_pin"))
@ -1183,7 +1178,7 @@ edgeDelayProperty(Edge *edge,
bool delay_exists = false;
TimingArcSet *arc_set = edge->timingArcSet();
for (TimingArc *arc : arc_set->arcs()) {
RiseFall *to_rf = arc->toEdge()->asRiseFall();
const RiseFall *to_rf = arc->toEdge()->asRiseFall();
if (to_rf == rf) {
for (const Corner *corner : *sta->corners()) {
DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(min_max);

37
search/ReportPath.cc
View File

@ -478,8 +478,8 @@ ReportPath::reportFull(const PathEndCheck *end) const
string
ReportPath::checkRoleString(const PathEnd *end) const
{
const char *check_role = end->checkRole(this)->asString();
return stdstrPrint("library %s time", check_role);
return stdstrPrint("library %s time",
end->checkRole(this)->to_string().c_str());
}
void
@ -493,9 +493,8 @@ ReportPath::reportEndpoint(const PathEndCheck *end) const
const TimingRole *check_generic_role = check_role->genericRole();
if (check_role == TimingRole::recovery()
|| check_role == TimingRole::removal()) {
const char *check_role_name = check_role->asString();
auto reason = stdstrPrint("%s check against %s-edge clock %s",
check_role_name,
check_role->to_string().c_str(),
rise_fall,
clk_name.c_str());
reportEndpoint(inst_name, reason);
@ -723,12 +722,11 @@ ReportPath::reportFull(const PathEndPathDelay *end) const
reportBlankLine();
ArcDelay margin = end->margin(this);
MinMax *min_max = path_delay->minMax()->asMinMax();
const MinMax *min_max = path_delay->minMax()->asMinMax();
if (min_max == MinMax::max())
margin = -margin;
const char *min_max_str = min_max->asString();
auto delay_msg = stdstrPrint("%s_delay", min_max_str);
string delay_msg = min_max->to_string() + "_delay";
float delay = path_delay->delay();
reportLine(delay_msg.c_str(), delay, delay, early_late);
if (!path_delay->ignoreClkLatency()) {
@ -1091,7 +1089,7 @@ ReportPath::reportJson(const PathEnd *end,
stringAppend(result, " \"path_group\": \"%s\",\n",
search_->pathGroup(end)->name());
stringAppend(result, " \"path_type\": \"%s\",\n",
end->minMax(this)->asString());
end->minMax(this)->to_string().c_str());
PathExpanded expanded(end->path(), this);
const Pin *startpoint = expanded.startPath()->vertex(this)->pin();
@ -1586,8 +1584,8 @@ ReportPath::reportShort(const MaxSkewCheck *check) const
TimingArc *check_arc = check->checkArc();
auto what = stdstrPrint("%s (%s->%s)",
clk_pin_name,
check_arc->fromEdge()->asString(),
check_arc->toEdge()->asString());
check_arc->fromEdge()->to_string().c_str(),
check_arc->toEdge()->to_string().c_str());
reportDescription(what.c_str(), line);
const EarlyLate *early_late = EarlyLate::early();
reportSpaceFieldDelay(check->maxSkew(this), early_late, line);
@ -1734,7 +1732,7 @@ ReportPath::reportLimitVerbose(const ReportField *field,
}
report_->reportLineString(line);
line = min_max->asString();
line = min_max->to_string();
line += ' ';
line += field->name();
line += ' ';
@ -1944,7 +1942,7 @@ ReportPath::reportGroup(const PathEnd *end) const
report_->reportLineString(line);
line = "Path Type: ";
line += end->minMax(this)->asString();
line += end->minMax(this)->to_string();
report_->reportLineString(line);
if (corners_->multiCorner()) {
@ -1959,8 +1957,7 @@ ReportPath::reportGroup(const PathEnd *end) const
string
ReportPath::checkRoleReason(const PathEnd *end) const
{
const char *setup_hold = end->checkRole(this)->asString();
return stdstrPrint("%s time", setup_hold);
return stdstrPrint("%s time", end->checkRole(this)->to_string().c_str());
}
string
@ -1996,7 +1993,7 @@ ReportPath::clkRegLatchDesc(const PathEnd *end) const
while (iter.hasNext()) {
Edge *edge = iter.next();
TimingArcSet *arc_set = edge->timingArcSet();
TimingRole *role = arc_set->role();
const TimingRole *role = arc_set->role();
if (role == TimingRole::regClkToQ()
|| role == TimingRole::latchEnToQ()) {
const RiseFall *arc_rf = arc_set->isRisingFallingEdge();
@ -2051,7 +2048,7 @@ ReportPath::reportSrcClkAndPath(const Path *path,
const MinMax *min_max = path->minMax(this);
if (clk_edge) {
Clock *clk = clk_edge->clock();
RiseFall *clk_rf = clk_edge->transition();
const RiseFall *clk_rf = clk_edge->transition();
float clk_time = clk_edge->time() + time_offset;
if (clk == sdc_->defaultArrivalClock()) {
if (!is_path_delay) {
@ -2207,7 +2204,7 @@ ReportPath::reportTgtClk(const PathEnd *end,
const MinMax *min_max = path_ap->pathMinMax();
const Path *clk_path = end->targetClkPath();
reportClkLine(clk, clk_name.c_str(), clk_end_rf, prev_time, clk_time, min_max);
TimingRole *check_role = end->checkRole(this);
const TimingRole *check_role = end->checkRole(this);
if (is_prop && reportClkPath()) {
float time_offset = prev_time
+ end->targetClkOffset(this)
@ -2779,7 +2776,7 @@ ReportPath::reportPath5(const Path *path,
time = search_->clkPathArrival(path1) + time_offset;
if (src_clk_edge) {
Clock *src_clk = src_clk_edge->clock();
RiseFall *src_clk_rf = src_clk_edge->transition();
const RiseFall *src_clk_rf = src_clk_edge->transition();
slew = src_clk->slew(src_clk_rf, min_max);
}
}
@ -2793,7 +2790,7 @@ ReportPath::reportPath5(const Path *path,
time = prev_time;
const ClockEdge *src_clk_edge = path->clkEdge(this);
const Clock *src_clk = src_clk_edge->clock();
RiseFall *src_clk_rf = src_clk_edge->transition();
const RiseFall *src_clk_rf = src_clk_edge->transition();
slew = src_clk->slew(src_clk_rf, min_max);
line_case = "clk_ideal";
}
@ -3453,7 +3450,7 @@ const char *
ReportPath::edgeRegLatchDesc(const Edge *first_edge,
const TimingArc *first_arc) const
{
TimingRole *role = first_arc->role();
const TimingRole *role = first_arc->role();
if (role == TimingRole::latchDtoQ()) {
Instance *inst = network_->instance(first_edge->to(graph_)->pin());
LibertyCell *cell = network_->libertyCell(inst);

108
search/Search.cc
View File

@ -92,7 +92,7 @@ bool
EvalPred::searchThru(Edge *edge)
{
const Sdc *sdc = sta_->sdc();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
return SearchPred0::searchThru(edge)
&& (sdc->dynamicLoopBreaking()
|| !edge->isDisabledLoop())
@ -536,7 +536,7 @@ Search::deleteFilteredArrivals()
if (!filtered_arrivals_->empty()) {
report_->reportLine("Filtered verticies mismatch");
for (Vertex *vertex : *filtered_arrivals_)
report_->reportLine(" %s", vertex->name(network_));
report_->reportLine(" %s", vertex->to_string(this).c_str());
}
}
filtered_arrivals_->clear();
@ -785,7 +785,7 @@ Search::arrivalInvalid(Vertex *vertex)
{
if (arrivals_exist_) {
debugPrint(debug_, "search", 2, "arrival invalid %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
if (!arrival_iter_->inQueue(vertex)) {
// Lock for StaDelayCalcObserver called by delay calc threads.
LockGuard lock(invalid_arrivals_lock_);
@ -848,7 +848,7 @@ Search::requiredInvalid(Vertex *vertex)
{
if (requireds_exist_) {
debugPrint(debug_, "search", 2, "required invalid %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
if (!required_iter_->inQueue(vertex)) {
// Lock for StaDelayCalcObserver called by delay calc threads.
LockGuard lock(invalid_arrivals_lock_);
@ -1139,7 +1139,7 @@ void
ArrivalVisitor::visit(Vertex *vertex)
{
debugPrint(debug_, "search", 2, "find arrivals %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
Pin *pin = vertex->pin();
tag_bldr_->init(vertex);
has_fanin_one_ = graph_->hasFaninOne(vertex);
@ -1285,15 +1285,15 @@ ArrivalVisitor::visitFromToPath(const Pin * /* from_pin */,
const PathAnalysisPt *)
{
debugPrint(debug_, "search", 3, " %s",
from_vertex->name(sdc_network_));
from_vertex->to_string(this).c_str());
debugPrint(debug_, "search", 3, " %s -> %s %s",
from_rf->asString(),
to_rf->asString(),
min_max->asString());
from_rf->to_string().c_str(),
to_rf->to_string().c_str(),
min_max->to_string().c_str());
debugPrint(debug_, "search", 3, " from tag: %s",
from_tag->asString(this));
from_tag->to_string(this).c_str());
debugPrint(debug_, "search", 3, " to tag : %s",
to_tag->asString(this));
to_tag->to_string(this).c_str());
ClkInfo *to_clk_info = to_tag->clkInfo();
bool to_is_clk = to_tag->isClock();
Path *match;
@ -1346,14 +1346,14 @@ ArrivalVisitor::pruneCrprArrivals()
? max_arrival - max_crpr
: max_arrival + max_crpr;
debugPrint(debug_, "search", 4, " cmp %s %s - %s = %s",
tag->asString(this),
tag->to_string(this).c_str(),
delayAsString(max_arrival, this),
delayAsString(max_crpr, this),
delayAsString(max_arrival_max_crpr, this));
Arrival arrival = tag_bldr_->arrival(path_index);
if (delayGreater(max_arrival_max_crpr, arrival, min_max, this)) {
debugPrint(debug_, "search", 3, " pruned %s",
tag->asString(this));
tag->to_string(this).c_str());
path_itr = path_index_map.erase(path_itr);
deleted_tag = true;
}
@ -1574,7 +1574,7 @@ Search::seedClkArrival(const Pin *pin,
uncertainties = clk->uncertainties();
// Propagate liberty "pulse_clock" transition to transitive fanout.
LibertyPort *port = network_->libertyPort(pin);
RiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr);
const RiseFall *pulse_clk_sense = (port ? port->pulseClkSense() : nullptr);
ClkInfo *clk_info = findClkInfo(clk_edge, pin, is_propagated, nullptr, false,
pulse_clk_sense, insertion, latency,
uncertainties, path_ap, nullptr);
@ -1637,7 +1637,7 @@ Search::makeUnclkedPaths(Vertex *vertex,
const Pin *pin = vertex->pin();
for (PathAnalysisPt *path_ap : corners_->pathAnalysisPts()) {
const MinMax *min_max = path_ap->pathMinMax();
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
Tag *tag = fromUnclkedInputTag(pin, rf, min_max, path_ap,
is_segment_start,
require_exception);
@ -1792,7 +1792,7 @@ Search::seedInputDelayArrival(const Pin *pin,
input_delay
? "arrival seed input arrival %s"
: "arrival seed input %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
const ClockEdge *clk_edge = nullptr;
const Pin *ref_pin = nullptr;
if (input_delay) {
@ -1880,7 +1880,7 @@ Search::seedInputDelayArrival(const Pin *pin,
PathAnalysisPt *path_ap,
TagGroupBldr *tag_bldr)
{
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
if (input_delay) {
float delay;
bool exists;
@ -1932,7 +1932,7 @@ Search::inputDelayClkArrival(InputDelay *input_delay,
if (input_delay && clk_edge) {
clk_arrival = clk_edge->time();
Clock *clk = clk_edge->clock();
RiseFall *clk_rf = clk_edge->transition();
const RiseFall *clk_rf = clk_edge->transition();
if (!input_delay->sourceLatencyIncluded()) {
const EarlyLate *early_late = min_max;
clk_insertion = delayAsFloat(clockInsertion(clk, clk->defaultPin(),
@ -1961,7 +1961,7 @@ Search::inputDelayTag(const Pin *pin,
{
Clock *clk = nullptr;
const Pin *clk_pin = nullptr;
RiseFall *clk_rf = nullptr;
const RiseFall *clk_rf = nullptr;
bool is_propagated = false;
ClockUncertainties *clk_uncertainties = nullptr;
if (clk_edge) {
@ -2039,7 +2039,7 @@ PathVisitor::visitFanoutPaths(Vertex *from_vertex)
if (pred_->searchTo(to_vertex)
&& pred_->searchThru(edge)) {
debugPrint(debug_, "search", 3, " %s",
to_vertex->name(network_));
to_vertex->to_string(this).c_str());
if (!visitEdge(from_pin, from_vertex, edge, to_pin, to_vertex))
break;
}
@ -2091,7 +2091,7 @@ PathVisitor::visitArc(const Pin *from_pin,
PathAnalysisPt *path_ap)
{
if (arc) {
RiseFall *to_rf = arc->toEdge()->asRiseFall();
const RiseFall *to_rf = arc->toEdge()->asRiseFall();
if (searchThru(from_vertex, from_rf, edge, to_vertex, to_rf))
return visitFromPath(from_pin, from_vertex, from_rf, from_path,
edge, arc, to_pin, to_vertex, to_rf,
@ -2323,7 +2323,7 @@ Search::pathClkPathArrival1(const Path *path) const
if (p->isClock(this))
return p;
if (prev_edge) {
TimingRole *prev_role = prev_edge->role();
const TimingRole *prev_role = prev_edge->role();
if (prev_role == TimingRole::regClkToQ()
|| prev_role == TimingRole::latchEnToQ()) {
return p->prevPath();
@ -2444,7 +2444,7 @@ Search::thruClkTag(Path *from_path,
ClkInfo *from_clk_info = from_tag->clkInfo();
bool from_is_clk = from_tag->isClock();
bool to_is_reg_clk = to_vertex->isRegClk();
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
bool to_is_clk = (from_is_clk
&& to_propagates_clk
&& (role->isWire()
@ -2513,8 +2513,8 @@ Search::thruClkInfo(Path *from_path,
}
// Propagate liberty "pulse_clock" transition to transitive fanout.
RiseFall *from_pulse_sense = from_clk_info->pulseClkSense();
RiseFall *to_pulse_sense = from_pulse_sense;
const RiseFall *from_pulse_sense = from_clk_info->pulseClkSense();
const RiseFall *to_pulse_sense = from_pulse_sense;
LibertyPort *port = network_->libertyPort(to_pin);
if (port && port->pulseClkSense()) {
to_pulse_sense = port->pulseClkSense();
@ -2761,7 +2761,7 @@ Search::setVertexArrivals(Vertex *vertex,
void
Search::reportArrivals(Vertex *vertex) const
{
report_->reportLine("Vertex %s", vertex->name(sdc_network_));
report_->reportLine("Vertex %s", vertex->to_string(this).c_str());
TagGroup *tag_group = tagGroup(vertex);
if (tag_group) {
report_->reportLine("Group %u", tag_group->index());
@ -2775,26 +2775,26 @@ Search::reportArrivals(Vertex *vertex) const
string prev_str;
Path *prev_path = path->prevPath();
if (prev_path) {
prev_str += prev_path->name(this);
prev_str += prev_path->to_string(this);
prev_str += " ";
const Edge *prev_edge = path->prevEdge(this);
TimingArc *arc = path->prevArc(this);
prev_str += prev_edge->from(graph_)->name(network_);
prev_str += prev_edge->from(graph_)->to_string(this);
prev_str += " ";
prev_str += arc->fromEdge()->asString();
prev_str += arc->fromEdge()->to_string();
prev_str += " -> ";
prev_str += prev_edge->to(graph_)->name(network_);
prev_str += prev_edge->to(graph_)->to_string(this);
prev_str += " ";
prev_str += arc->toEdge()->asString();
prev_str += arc->toEdge()->to_string();
}
else
prev_str = "NULL";
report_->reportLine(" %s %s %s / %s %s prev %s",
rf->asString(),
path_ap->pathMinMax()->asString(),
rf->to_string().c_str(),
path_ap->pathMinMax()->to_string().c_str(),
delayAsString(path->arrival(), this),
req,
tag->asString(true, false, this),
tag->to_string(true, false, this).c_str(),
prev_str.c_str());
}
}
@ -2942,7 +2942,7 @@ Search::reportTags() const
for (TagIndex i = 0; i < tag_next_; i++) {
Tag *tag = tags_[i];
if (tag)
report_->reportLine("%s", tag->asString(this)) ;
report_->reportLine("%s", tag->to_string(this).c_str()) ;
}
size_t long_hash = 0;
for (size_t i = 0; i < tag_set_->bucket_count(); i++) {
@ -3035,7 +3035,7 @@ Search::timingDerate(const Vertex *from_vertex,
{
PathClkOrData derate_clk_data =
is_clk ? PathClkOrData::clk : PathClkOrData::data;
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
const Pin *pin = from_vertex->pin();
if (role->isWire()) {
const RiseFall *rf = arc->toEdge()->asRiseFall();
@ -3195,7 +3195,7 @@ Search::endpoints()
Vertex *vertex = vertex_iter.next();
if (isEndpoint(vertex)) {
debugPrint(debug_, "endpoint", 2, "insert %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
endpoints_->insert(vertex);
}
}
@ -3204,14 +3204,14 @@ Search::endpoints()
for (Vertex *vertex : *invalid_endpoints_) {
if (isEndpoint(vertex)) {
debugPrint(debug_, "endpoint", 2, "insert %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
endpoints_->insert(vertex);
}
else {
if (debug_->check("endpoint", 2)
&& endpoints_->hasKey(vertex))
report_->reportLine("endpoint: remove %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
endpoints_->erase(vertex);
}
}
@ -3225,7 +3225,7 @@ Search::endpointInvalid(Vertex *vertex)
{
if (invalid_endpoints_) {
debugPrint(debug_, "endpoint", 2, "invalid %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
invalid_endpoints_->insert(vertex);
}
}
@ -3345,7 +3345,7 @@ void
Search::seedRequired(Vertex *vertex)
{
debugPrint(debug_, "search", 2, "required seed %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
RequiredCmp required_cmp;
FindEndRequiredVisitor seeder(&required_cmp, this);
required_cmp.requiredsInit(vertex, this);
@ -3459,7 +3459,7 @@ void
RequiredVisitor::visit(Vertex *vertex)
{
debugPrint(debug_, "search", 2, "find required %s",
vertex->name(network_));
vertex->to_string(this).c_str());
required_cmp_->requiredsInit(vertex, this);
// Back propagate requireds from fanout.
visitFanoutPaths(vertex);
@ -3495,12 +3495,12 @@ RequiredVisitor::visitFromToPath(const Pin *,
// Don't propagate required times through latch D->Q edges.
if (edge->role() != TimingRole::latchDtoQ()) {
debugPrint(debug_, "search", 3, " %s -> %s %s",
from_rf->asString(),
to_rf->asString(),
min_max->asString());
from_rf->to_string().c_str(),
to_rf->to_string().c_str(),
min_max->to_string().c_str());
debugPrint(debug_, "search", 3, " from tag %2u: %s",
from_tag->index(),
from_tag->asString(this));
from_tag->to_string(this).c_str());
size_t path_index = from_path->pathIndex(this);
const MinMax *req_min = min_max->opposite();
TagGroup *to_tag_group = search_->tagGroup(to_vertex);
@ -3512,7 +3512,7 @@ RequiredVisitor::visitFromToPath(const Pin *,
Required from_required = to_required - arc_delay;
debugPrint(debug_, "search", 3, " to tag %2u: %s",
to_tag->index(),
to_tag->asString(this));
to_tag->to_string(this).c_str());
debugPrint(debug_, "search", 3, " %s - %s = %s %s %s",
delayAsString(to_required, this),
delayAsString(arc_delay, this),
@ -3535,7 +3535,7 @@ RequiredVisitor::visitFromToPath(const Pin *,
Required from_required = to_required - arc_delay;
debugPrint(debug_, "search", 3, " to tag %2u: %s",
to_path_tag->index(),
to_path_tag->asString(this));
to_path_tag->to_string(this).c_str());
debugPrint(debug_, "search", 3, " %s - %s = %s %s %s",
delayAsString(to_required, this),
delayAsString(arc_delay, this),
@ -3607,7 +3607,7 @@ Search::matchesFilter(Path *path,
// -from clks
const ClockEdge *path_clk_edge = path->clkEdge(this);
const Clock *path_clk = path_clk_edge ? path_clk_edge->clock() : nullptr;
RiseFall *path_clk_rf =
const RiseFall *path_clk_rf =
path_clk_edge ? path_clk_edge->transition() : nullptr;
return filter_from_->clks()->hasKey(const_cast<Clock*>(path_clk))
&& filter_from_->transition()->matches(path_clk_rf)
@ -3719,7 +3719,7 @@ Search::tnsInvalid(Vertex *vertex)
if ((tns_exists_ || worst_slacks_)
&& isEndpoint(vertex)) {
debugPrint(debug_, "tns", 2, "tns invalid %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
LockGuard lock(tns_lock_);
invalid_tns_->insert(vertex);
}
@ -3733,7 +3733,7 @@ Search::updateInvalidTns()
// Network edits can change endpointedness since tnsInvalid was called.
if (isEndpoint(vertex)) {
debugPrint(debug_, "tns", 2, "update tns %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
SlackSeq slacks(path_ap_count);
wnsSlacks(vertex, slacks);
@ -3783,7 +3783,7 @@ Search::tnsIncr(Vertex *vertex,
if (delayLess(slack, 0.0, this)) {
debugPrint(debug_, "tns", 3, "tns+ %s %s",
delayAsString(slack, this),
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
tns_[path_ap_index] += slack;
if (tns_slacks_[path_ap_index].hasKey(vertex))
report_->critical(1513, "tns incr existing vertex");
@ -3802,7 +3802,7 @@ Search::tnsDecr(Vertex *vertex,
&& delayLess(slack, 0.0, this)) {
debugPrint(debug_, "tns", 3, "tns- %s %s",
delayAsString(slack, this),
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
tns_[path_ap_index] -= slack;
tns_slacks_[path_ap_index].erase(vertex);
}
@ -3863,7 +3863,7 @@ Search::wnsTnsPreamble()
for (auto itr = invalid_requireds_->begin(); itr != invalid_requireds_->end(); ) {
Vertex *vertex = *itr;
debugPrint(debug_, "search", 2, "tns update required %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
if (isEndpoint(vertex)) {
seedRequired(vertex);
// If the endpoint has fanout it's required time

10
search/Search.i
View File

@ -313,11 +313,9 @@ void
report_loops()
{
Sta *sta = Sta::sta();
Network *network = sta->network();
Graph *graph = sta->ensureGraph();
Report *report = sta->report();
for (GraphLoop *loop : *sta->graphLoops()) {
loop->report(report, network, graph);
loop->report(sta);
report->reportLineString("");
}
}
@ -1258,7 +1256,7 @@ Slack slack() { return self->slack(Sta::sta()); }
ArcDelay margin() { return self->margin(Sta::sta()); }
Required data_required_time() { return self->requiredTimeOffset(Sta::sta()); }
Arrival data_arrival_time() { return self->dataArrivalTimeOffset(Sta::sta()); }
TimingRole *check_role() { return self->checkRole(Sta::sta()); }
const TimingRole *check_role() { return self->checkRole(Sta::sta()); }
MinMax *min_max() { return const_cast<MinMax*>(self->minMax(Sta::sta())); }
float source_clk_offset() { return self->sourceClkOffset(Sta::sta()); }
Arrival source_clk_latency() { return self->sourceClkLatency(Sta::sta()); }
@ -1315,11 +1313,11 @@ pin()
return self->pin(sta);
}
const char *
string
tag()
{
Sta *sta = Sta::sta();
return self->tag(sta)->asString(sta);
return self->tag(sta)->to_string(sta);
}
// mea_opt3

4
search/SearchPred.cc
View File

@ -184,8 +184,8 @@ searchThru(const Edge *edge,
const TimingArc *arc,
const Graph *graph)
{
RiseFall *from_rf = arc->fromEdge()->asRiseFall();
RiseFall *to_rf = arc->toEdge()->asRiseFall();
const RiseFall *from_rf = arc->fromEdge()->asRiseFall();
const RiseFall *to_rf = arc->toEdge()->asRiseFall();
// Ignore transitions other than rise/fall.
return from_rf && to_rf
&& searchThru(edge->from(graph), from_rf, edge, edge->to(graph), to_rf);

10
search/Sim.cc
View File

@ -78,7 +78,7 @@ Sim::functionSense(const FuncExpr *expr,
{
debugPrint(debug_, "sim", 4, "find sense pin %s %s",
network_->pathName(input_pin),
expr->asString());
expr->to_string().c_str());
bool increasing, decreasing;
{
LockGuard lock(bdd_lock_);
@ -103,7 +103,7 @@ Sim::functionSense(const FuncExpr *expr,
sense = TimingSense::negative_unate;
else
sense = TimingSense::non_unate;
debugPrint(debug_, "sim", 4, " %s", timingSenseString(sense));
debugPrint(debug_, "sim", 4, " %s", to_string(sense));
return sense;
}
@ -586,7 +586,7 @@ Sim::evalInstance(const Instance *inst,
value = evalExpr(expr, inst);
debugPrint(debug_, "sim", 2, " %s tri_en=1 %s = %c",
port->name(),
expr->asString(),
expr->to_string().c_str(),
logicValueString(value));
}
}
@ -601,14 +601,14 @@ Sim::evalInstance(const Instance *inst,
value = logicNot(value);
debugPrint(debug_, "sim", 2, " %s seq %s = %c",
port->name(),
expr->asString(),
expr->to_string().c_str(),
logicValueString(value));
}
else {
value = evalExpr(expr, inst);
debugPrint(debug_, "sim", 2, " %s %s = %c",
port->name(),
expr->asString(),
expr->to_string().c_str(),
logicValueString(value));
}
}

56
search/Sta.cc
View File

@ -232,7 +232,6 @@ void
initSta()
{
initElapsedTime();
TimingRole::init();
PortDirection::init();
initLiberty();
initDelayConstants();
@ -249,7 +248,6 @@ deleteAllMemory()
Sta::setSta(nullptr);
}
deleteDelayCalcs();
TimingRole::destroy();
PortDirection::destroy();
deleteLiberty();
}
@ -3021,7 +3019,7 @@ Sta::vertexSlack(Vertex *vertex,
const MinMax *min_max)
{
findRequired(vertex);
MinMax *min = MinMax::min();
const MinMax *min = MinMax::min();
Slack slack = min->initValue();
VertexPathIterator path_iter(vertex, this);
while (path_iter.hasNext()) {
@ -3077,7 +3075,7 @@ Sta::vertexSlack1(Vertex *vertex,
const ClockEdge *clk_edge,
const PathAnalysisPt *path_ap)
{
MinMax *min = MinMax::min();
const MinMax *min = MinMax::min();
Slack slack = min->initValue();
VertexPathIterator path_iter(vertex, rf, path_ap, this);
while (path_iter.hasNext()) {
@ -3221,7 +3219,7 @@ Sta::findRequired(Vertex *vertex)
int fanout = 0;
disableFanoutCrprPruning(vertex, fanout);
debugPrint(debug_, "search", 1, "resurrect pruned required %s fanout %d",
vertex->name(sdc_network_),
vertex->to_string(this).c_str(),
fanout);
// Find fanout arrivals and requireds with pruning disabled.
search_->findArrivals();
@ -3605,7 +3603,7 @@ Sta::setArcDelay(Edge *edge,
ArcDelay delay)
{
ensureGraph();
for (MinMax *mm : min_max->range()) {
for (const MinMax *mm : min_max->range()) {
const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(mm);
DcalcAPIndex ap_index = dcalc_ap->index();
graph_->setArcDelay(edge, arc, ap_index, delay);
@ -3628,10 +3626,10 @@ Sta::setAnnotatedSlew(Vertex *vertex,
float slew)
{
ensureGraph();
for (MinMax *mm : min_max->range()) {
for (const MinMax *mm : min_max->range()) {
const DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(mm);
DcalcAPIndex ap_index = dcalc_ap->index();
for (RiseFall *rf1 : rf->range()) {
for (const RiseFall *rf1 : rf->range()) {
graph_->setSlew(vertex, rf1, ap_index, slew);
// Don't let delay calculation clobber the value.
vertex->setSlewAnnotated(true, rf1, ap_index);
@ -3692,10 +3690,10 @@ Sta::setPortExtPinCap(const Port *port,
const MinMaxAll *min_max,
float cap)
{
for (RiseFall *rf1 : rf->range()) {
for (MinMax *mm : min_max->range()) {
for (const RiseFall *rf1 : rf->range()) {
for (const MinMax *mm : min_max->range()) {
if (corner == nullptr) {
for (Corner *corner : *corners_)
for (const Corner *corner : *corners_)
sdc_->setPortExtPinCap(port, rf1, corner, mm, cap);
}
else
@ -3719,7 +3717,7 @@ Sta::portExtCaps(const Port *port,
pin_cap = min_max->initValue();
wire_cap = min_max->initValue();
fanout = min_max->initValueInt();
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
float pin_cap1, wire_cap1;
int fanout1;
bool pin_exists1, wire_exists1, fanout_exists1;
@ -3756,10 +3754,10 @@ Sta::setPortExtWireCap(const Port *port,
const MinMaxAll *min_max,
float cap)
{
for (RiseFall *rf1 : rf->range()) {
for (MinMax *mm : min_max->range()) {
for (const RiseFall *rf1 : rf->range()) {
for (const MinMax *mm : min_max->range()) {
if (corner == nullptr) {
for (Corner *corner : *corners_)
for (const Corner *corner : *corners_)
sdc_->setPortExtWireCap(port, subtract_pin_cap, rf1, corner, mm, cap);
}
else
@ -3782,9 +3780,9 @@ Sta::setPortExtFanout(const Port *port,
const Corner *corner,
const MinMaxAll *min_max)
{
for (MinMax *mm : min_max->range()) {
for (const MinMax *mm : min_max->range()) {
if (corner == nullptr) {
for (Corner *corner : *corners_)
for (const Corner *corner : *corners_)
sdc_->setPortExtFanout(port, corner, mm, fanout);
}
else
@ -3800,9 +3798,9 @@ Sta::setNetWireCap(const Net *net,
const MinMaxAll *min_max,
float cap)
{
for (MinMax *mm : min_max->range()) {
for (const MinMax *mm : min_max->range()) {
if (corner == nullptr) {
for (Corner *corner : *corners_)
for (const Corner *corner : *corners_)
sdc_->setNetWireCap(net, subtract_pin_cap, corner, mm, cap);
}
else
@ -3835,7 +3833,7 @@ Sta::connectedCap(const Net *net,
pin_cap = min_max->initValue();
wire_cap = min_max->initValue();
for (const Corner *corner : makeCornerSeq(corner)) {
for (RiseFall *rf : RiseFall::range()) {
for (const RiseFall *rf : RiseFall::range()) {
float pin_cap1, wire_cap1;
connectedCap(drvr_pin, rf, corner, min_max, pin_cap1, wire_cap1);
pin_cap = min_max->minMax(pin_cap, pin_cap1);
@ -3869,7 +3867,7 @@ Sta::capacitance(const LibertyPort *port,
float cap = min_max->initValue();
for (const Corner *corner : makeCornerSeq(corner)) {
const LibertyPort *corner_port = port->cornerPort(corner, min_max);
for (RiseFall *rf : RiseFall::range())
for (const RiseFall *rf : RiseFall::range())
cap = min_max->minMax(cap, corner_port->capacitance(rf, min_max, op_cond, op_cond));
}
return cap;
@ -3983,8 +3981,8 @@ Sta::makePiElmore(Pin *drvr_pin,
float rpi,
float c1)
{
Corner *corner = cmd_corner_;
for (MinMax *mm : min_max->range()) {
const Corner *corner = cmd_corner_;
for (const MinMax *mm : min_max->range()) {
ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(mm);
parasitics_->makePiElmore(drvr_pin, rf, ap, c2, rpi, c1);
}
@ -4015,8 +4013,8 @@ Sta::setElmore(Pin *drvr_pin,
const MinMaxAll *min_max,
float elmore)
{
Corner *corner = cmd_corner_;
for (MinMax *mm : min_max->range()) {
const Corner *corner = cmd_corner_;
for (const MinMax *mm : min_max->range()) {
const ParasiticAnalysisPt *ap = corner->findParasiticAnalysisPt(mm);
Parasitic *pi_elmore = parasitics_->findPiElmore(drvr_pin, rf, ap);
if (pi_elmore)
@ -4871,7 +4869,7 @@ FanInOutSrchPred::searchThru(Edge *edge)
bool
FanInOutSrchPred::searchThruRole(Edge *edge)
{
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
return role == TimingRole::wire()
|| role == TimingRole::combinational()
|| role == TimingRole::tristateEnable()
@ -4920,7 +4918,7 @@ FaninSrchPred::FaninSrchPred(bool thru_disabled,
bool
FaninSrchPred::searchThruRole(Edge *edge)
{
TimingRole *role = edge->role();
const TimingRole *role = edge->role();
return role == TimingRole::wire()
|| role == TimingRole::combinational()
|| role == TimingRole::tristateEnable()
@ -4996,7 +4994,7 @@ Sta::findFaninPins(Vertex *to,
int pin_level)
{
debugPrint(debug_, "fanin", 1, "%s",
to->name(sdc_network_));
to->to_string(this).c_str());
if (!visited.hasKey(to)) {
visited.insert(to);
Pin *to_pin = to->pin();
@ -5106,7 +5104,7 @@ Sta::findFanoutPins(Vertex *from,
int pin_level)
{
debugPrint(debug_, "fanout", 1, "%s",
from->name(sdc_network_));
from->to_string(this).c_str());
if (!visited.hasKey(from)) {
visited.insert(from);
if (!search_->isEndpoint(from, pred)

23
search/Tag.cc
View File

@ -89,16 +89,16 @@ Tag::~Tag()
delete states_;
}
const char *
Tag::asString(const StaState *sta) const
string
Tag::to_string(const StaState *sta) const
{
return asString(true, true, sta);
return to_string(true, true, sta);
}
const char *
Tag::asString(bool report_index,
bool report_rf_min_max,
const StaState *sta) const
string
Tag::to_string(bool report_index,
bool report_rf_min_max,
const StaState *sta) const
{
const Network *network = sta->network();
const Corners *corners = sta->corners();
@ -111,9 +111,9 @@ Tag::asString(bool report_index,
const RiseFall *rf = transition();
PathAnalysisPt *path_ap = corners->findPathAnalysisPt(path_ap_index_);
result += " ";
result += rf->asString();
result += rf->to_string().c_str();
result += " ";
result += path_ap->pathMinMax()->asString();
result += path_ap->pathMinMax()->to_string();
result += "/";
result += std::to_string(path_ap_index_);
}
@ -178,10 +178,7 @@ Tag::asString(bool report_index,
}
}
}
char *tmp = makeTmpString(result.size() + 1);
strcpy(tmp, result.c_str());
return tmp;
return result;
}
const RiseFall *

8
search/Tag.hh
View File

@ -62,10 +62,10 @@ public:
bool own_states,
const StaState *sta);
~Tag();
const char *asString(const StaState *sta) const;
const char *asString(bool report_index,
bool report_rf_min_max,
const StaState *sta) const;
string to_string(const StaState *sta) const;
string to_string(bool report_index,
bool report_rf_min_max,
const StaState *sta) const;
ClkInfo *clkInfo() const { return clk_info_; }
bool isClock() const { return is_clk_; }
const ClockEdge *clkEdge() const;

2
search/TagGroup.cc
View File

@ -120,7 +120,7 @@ pathIndexMapReport(const PathIndexMap *path_index_map,
for (auto const [tag, path_index] : *path_index_map)
report->reportLine(" %2zu %s",
path_index,
tag->asString(sta));
tag->to_string(sta).c_str());
report->reportBlankLine();
}

14
search/VisitPathEnds.cc
View File

@ -65,7 +65,7 @@ VisitPathEnds::visitPathEnds(Vertex *vertex,
if (!vertex->isBidirectDriver()) {
const Pin *pin = vertex->pin();
debugPrint(debug_, "search", 2, "find end slack %s",
vertex->name(sdc_network_));
vertex->to_string(this).c_str());
visitor->vertexBegin(vertex);
bool is_constrained = false;
visitClkedPathEnds(pin, vertex, corner, min_max, filtered, visitor,
@ -155,7 +155,7 @@ VisitPathEnds::visitCheckEnd(const Pin *pin,
&& check_role->pathMinMax() == min_max) {
TimingArcSet *arc_set = edge->timingArcSet();
for (TimingArc *check_arc : arc_set->arcs()) {
RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall();
const RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall();
if (check_arc->toEdge()->asRiseFall() == end_rf
&& clk_rf) {
VertexPathIterator tgt_clk_path_iter(tgt_clk_vertex, clk_rf,
@ -255,7 +255,7 @@ VisitPathEnds::visitCheckEndUnclked(const Pin *pin,
&& check_role->pathMinMax() == min_max) {
TimingArcSet *arc_set = edge->timingArcSet();
for (TimingArc *check_arc : arc_set->arcs()) {
RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall();
const RiseFall *clk_rf = check_arc->fromEdge()->asRiseFall();
if (check_arc->toEdge()->asRiseFall() == end_rf
&& clk_rf
&& (!filtered
@ -315,7 +315,7 @@ VisitPathEnds::visitOutputDelayEnd(const Pin *pin,
if (ref_pin) {
Clock *tgt_clk = output_delay->clock();
Vertex *ref_vertex = graph_->pinLoadVertex(ref_pin);
RiseFall *ref_rf = output_delay->refTransition();
const RiseFall *ref_rf = output_delay->refTransition();
VertexPathIterator ref_path_iter(ref_vertex,ref_rf,path_ap,this);
while (ref_path_iter.hasNext()) {
Path *ref_path = ref_path_iter.next();
@ -406,7 +406,7 @@ VisitPathEnds::visitGatedClkEnd(const Pin *pin,
Vertex *clk_vertex = graph_->pinLoadVertex(clk_pin);
LogicValue active_value =
sdc_->clockGatingActiveValue(clk_pin, pin);
RiseFall *clk_rf =
const RiseFall *clk_rf =
// Clock active value specified by set_clock_gating_check
// overrides the library cell function active value.
gated_clk->gatedClkActiveTrans((active_value == LogicValue::unknown) ?
@ -425,7 +425,7 @@ VisitPathEnds::visitGatedClkEnd(const Pin *pin,
&& !path->clkInfo(this)->isGenClkSrcPath()
&& !sdc_->clkStopPropagation(pin, clk)
&& clk_vertex->hasDownstreamClkPin()) {
TimingRole *check_role = (min_max == MinMax::max())
const TimingRole *check_role = (min_max == MinMax::max())
? TimingRole::gatedClockSetup()
: TimingRole::gatedClockHold();
float margin = clockGatingMargin(clk, clk_pin,
@ -536,7 +536,7 @@ VisitPathEnds::visitDataCheckEnd1(DataCheck *check,
const PathAnalysisPt *clk_ap,
const Pin *from_pin,
Vertex *from_vertex,
RiseFall *from_rf,
const RiseFall *from_rf,
bool filtered,
PathEndVisitor *visitor,
bool &is_constrained)

18
search/VisitPathGroupVertices.cc
View File

@ -243,7 +243,7 @@ PathGroupPathVisitor::visit(Vertex *vertex)
visitFanoutPaths(vertex);
if (vertex_matches_) {
debugPrint(debug_, "visit_path_group", 1, "visit %s",
vertex->name(network_));
vertex->to_string(this).c_str());
visitor_->visit(vertex);
bkwd_iter_->enqueueAdjacentVertices(vertex);
}
@ -272,10 +272,10 @@ PathGroupPathVisitor::visitFromToPath(const Pin *,
if (!to_path.isNull()) {
if (matching_paths->hasKey(&to_path)) {
debugPrint(debug_, "visit_path_group", 2, "match %s %s -> %s %s",
from_vertex->name(network_),
from_tag->asString(this),
to_vertex->name(network_),
to_tag->asString(this));
from_vertex->to_string(this).c_str(),
from_tag->to_string(this).c_str(),
to_vertex->to_string(this).c_str(),
to_tag->to_string(this).c_str());
fromMatches(from_vertex, from_tag);
}
}
@ -287,10 +287,10 @@ PathGroupPathVisitor::visitFromToPath(const Pin *,
&& matching_paths->hasKey(to_path)) {
debugPrint(debug_, "visit_path_group", 2,
"match crpr %s %s -> %s %s",
from_vertex->name(network_),
from_tag->asString(this),
to_vertex->name(network_),
to_tag->asString(this));
from_vertex->to_string(this).c_str(),
from_tag->to_string(this).c_str(),
to_vertex->to_string(this).c_str(),
to_tag->to_string(this).c_str());
fromMatches(from_vertex, from_tag);
}
}

10
search/WorstSlack.cc
View File

@ -254,7 +254,7 @@ WorstSlack::checkQueue(PathAPIndex path_ap_index)
&& delayLessEqual(search_->wnsSlack(end, path_ap_index),
slack_threshold_, this))
report_->reportLine("WorstSlack queue missing %s %s < %s",
end->name(network_),
end->to_string(this).c_str(),
delayAsString(search_->wnsSlack(end, path_ap_index), this),
delayAsString(slack_threshold_, this));
}
@ -262,7 +262,7 @@ WorstSlack::checkQueue(PathAPIndex path_ap_index)
for (Vertex *end : *queue_) {
if (!end_set.hasKey(end))
report_->reportLine("WorstSlack queue extra %s %s > %s",
end->name(network_),
end->to_string(this).c_str(),
delayAsString(search_->wnsSlack(end, path_ap_index), this),
delayAsString(slack_threshold_, this));
}
@ -289,13 +289,13 @@ WorstSlack::updateWorstSlack(Vertex *vertex,
if (!delayEqual(slack, slack_init_)
&& delayLessEqual(slack, slack_threshold_, this)) {
debugPrint(debug_, "wns", 3, "insert %s %s",
vertex->name(network_),
vertex->to_string(this).c_str(),
delayAsString(slack, this));
queue_->insert(vertex);
}
else {
debugPrint(debug_, "wns", 3, "delete %s %s",
vertex->name(network_),
vertex->to_string(this).c_str(),
delayAsString(slack, this));
queue_->erase(vertex);
}
@ -308,7 +308,7 @@ WorstSlack::setWorstSlack(Vertex *vertex,
Slack slack)
{
debugPrint(debug_, "wns", 3, "%s %s",
vertex->name(network_),
vertex->to_string(this).c_str(),
delayAsString(slack, this));
worst_vertex_ = vertex;
worst_slack_ = slack;

6
spice/WritePathSpice.cc
View File

@ -222,9 +222,9 @@ WritePathSpice::writeHeader()
const Path *start_path = path_expanded_.startPath();
string title = stdstrPrint("Path from %s %s to %s %s",
network_->pathName(start_path->pin(this)),
start_path->transition(this)->asString(),
start_path->transition(this)->to_string().c_str(),
network_->pathName(path_->pin(this)),
path_->transition(this)->asString());
path_->transition(this)->to_string().c_str());
float max_time = maxTime();
float time_step = 1e-13;
writeHeader(title, max_time, time_step);
@ -364,7 +364,7 @@ WritePathSpice::writeClkWaveform()
const Clock *clk = clk_edge->clock();
float period = clk->period();
float time_offset = clkWaveformTimeOffset(clk);
RiseFall *rf0, *rf1;
const RiseFall *rf0, *rf1;
float volt0;
if (clk_edge->time() < period) {
rf0 = RiseFall::rise();

66
tcl/StaTclTypes.i
View File

@ -452,38 +452,40 @@ using namespace sta;
Transition *tr = $1;
const char *str = "";
if (tr)
str = tr->asString();
str = tr->to_string().c_str();
Tcl_SetResult(interp, const_cast<char*>(str), TCL_STATIC);
}
%typemap(in) RiseFall* {
int length;
const char *arg = Tcl_GetStringFromObj($input, &length);
RiseFall *rf = RiseFall::find(arg);
const RiseFall *rf = RiseFall::find(arg);
if (rf == nullptr) {
tclArgError(interp, 2151, "Unknown rise/fall edge '%s'.", arg);
return TCL_ERROR;
}
$1 = rf;
// Swig is retarded and drops const on args.
$1 = const_cast<RiseFall*>(rf);
}
%typemap(out) RiseFall* {
const RiseFall *tr = $1;
const RiseFall *rf = $1;
const char *str = "";
if (tr)
str = tr->asString();
if (rf)
str = rf->to_string().c_str();
Tcl_SetResult(interp, const_cast<char*>(str), TCL_STATIC);
}
%typemap(in) RiseFallBoth* {
int length;
const char *arg = Tcl_GetStringFromObj($input, &length);
RiseFallBoth *tr = RiseFallBoth::find(arg);
if (tr == nullptr) {
const RiseFallBoth *rf = RiseFallBoth::find(arg);
if (rf == nullptr) {
tclArgError(interp, 2152, "Unknown transition name '%s'.", arg);
return TCL_ERROR;
}
$1 = tr;
// Swig is retarded and drops const on args.
$1 = const_cast<RiseFallBoth*>(rf);
}
%typemap(out) RiseFallBoth* {
@ -509,9 +511,10 @@ using namespace sta;
%typemap(in) TimingRole* {
int length;
const char *arg = Tcl_GetStringFromObj($input, &length);
TimingRole *role = TimingRole::find(arg);
const TimingRole *role = TimingRole::find(arg);
if (role)
$1 = TimingRole::find(arg);
// Swig is retarded and drops const on args.
$1 = const_cast<TimingRole*>(TimingRole::find(arg));
else {
tclArgError(interp, 2154, "Unknown timing role '%s'.", arg);
return TCL_ERROR;
@ -519,7 +522,7 @@ using namespace sta;
}
%typemap(out) TimingRole* {
Tcl_SetResult(interp, const_cast<char*>($1->asString()), TCL_STATIC);
Tcl_SetResult(interp, const_cast<char*>($1->to_string().c_str()), TCL_STATIC);
}
%typemap(in) LogicValue {
@ -848,7 +851,8 @@ using namespace sta;
%typemap(in) MinMax* {
int length;
char *arg = Tcl_GetStringFromObj($input, &length);
MinMax *min_max = MinMax::find(arg);
// Swig is retarded and drops const on args.
MinMax *min_max = const_cast<MinMax*>(MinMax::find(arg));
if (min_max)
$1 = min_max;
else {
@ -858,17 +862,18 @@ using namespace sta;
}
%typemap(out) MinMax* {
Tcl_SetResult(interp, const_cast<char*>($1->asString()), TCL_STATIC);
Tcl_SetResult(interp, const_cast<char*>($1->to_string().c_str()), TCL_STATIC);
}
%typemap(out) MinMax* {
Tcl_SetResult(interp, const_cast<char*>($1->asString()), TCL_STATIC);
Tcl_SetResult(interp, const_cast<char*>($1->to_string().c_str()), TCL_STATIC);
}
%typemap(in) MinMaxAll* {
int length;
char *arg = Tcl_GetStringFromObj($input, &length);
MinMaxAll *min_max = MinMaxAll::find(arg);
// Swig is retarded and drops const on args.
MinMaxAll *min_max = const_cast<MinMaxAll*>(MinMaxAll::find(arg));
if (min_max)
$1 = min_max;
else {
@ -883,7 +888,8 @@ using namespace sta;
if (stringEqual(arg, "NULL"))
$1 = nullptr;
else {
MinMaxAll *min_max = MinMaxAll::find(arg);
// Swig is retarded and drops const on args.
MinMaxAll *min_max = const_cast<MinMaxAll*>(MinMaxAll::find(arg));
if (min_max)
$1 = min_max;
else {
@ -898,15 +904,16 @@ using namespace sta;
}
// SetupHold is typedef'd to MinMax.
%typemap(in) SetupHold* {
%typemap(in) const SetupHold* {
int length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
if (stringEqual(arg, "hold")
|| stringEqual(arg, "min"))
$1 = MinMax::min();
$1 = const_cast<MinMax*>(MinMax::min());
else if (stringEqual(arg, "setup")
|| stringEqual(arg, "max"))
$1 = MinMax::max();
$1 = const_cast<MinMax*>(MinMax::max());
else {
tclArgError(interp, 2162, "%s not setup, hold, min or max.", arg);
return TCL_ERROR;
@ -914,18 +921,19 @@ using namespace sta;
}
// SetupHoldAll is typedef'd to MinMaxAll.
%typemap(in) SetupHoldAll* {
%typemap(in) const SetupHoldAll* {
int length;
char *arg = Tcl_GetStringFromObj($input, &length);
// Swig is retarded and drops const on args.
if (stringEqual(arg, "hold")
|| stringEqual(arg, "min"))
$1 = SetupHoldAll::min();
$1 = const_cast<SetupHoldAll*>(SetupHoldAll::min());
else if (stringEqual(arg, "setup")
|| stringEqual(arg, "max"))
$1 = SetupHoldAll::max();
$1 = const_cast<SetupHoldAll*>(SetupHoldAll::max());
else if (stringEqual(arg, "setup_hold")
|| stringEqual(arg, "min_max"))
$1 = SetupHoldAll::all();
$1 = const_cast<SetupHoldAll*>(SetupHoldAll::all());
else {
tclArgError(interp, 2163, "%s not setup, hold, setup_hold, min, max or min_max.", arg);
return TCL_ERROR;
@ -933,10 +941,11 @@ using namespace sta;
}
// EarlyLate is typedef'd to MinMax.
%typemap(in) EarlyLate* {
%typemap(in) const EarlyLate* {
int length;
char *arg = Tcl_GetStringFromObj($input, &length);
EarlyLate *early_late = EarlyLate::find(arg);
// Swig is retarded and drops const on args.
EarlyLate *early_late = const_cast<EarlyLate*>(EarlyLate::find(arg));
if (early_late)
$1 = early_late;
else {
@ -946,10 +955,11 @@ using namespace sta;
}
// EarlyLateAll is typedef'd to MinMaxAll.
%typemap(in) EarlyLateAll* {
%typemap(in) const EarlyLateAll* {
int length;
char *arg = Tcl_GetStringFromObj($input, &length);
EarlyLateAll *early_late = EarlyLateAll::find(arg);
// Swig is retarded and drops const on args.
EarlyLateAll *early_late = const_cast<EarlyLateAll*>(EarlyLateAll::find(arg));
if (early_late)
$1 = early_late;
else {

4
tcl/TclTypeHelpers.cc
View File

@ -161,7 +161,7 @@ tclArcDcalcArg(ArcDcalcArg &gate,
obj = Tcl_NewStringObj(from_name, strlen(from_name));
Tcl_ListObjAppendElement(interp, list, obj);
const char *from_edge = arc->fromEdge()->asString();
const char *from_edge = arc->fromEdge()->to_string().c_str();
obj = Tcl_NewStringObj(from_edge, strlen(from_edge));
Tcl_ListObjAppendElement(interp, list, obj);
@ -169,7 +169,7 @@ tclArcDcalcArg(ArcDcalcArg &gate,
obj = Tcl_NewStringObj(to_name, strlen(to_name));
Tcl_ListObjAppendElement(interp, list, obj);
const char *to_edge = arc->toEdge()->asString();
const char *to_edge = arc->toEdge()->to_string().c_str();
obj = Tcl_NewStringObj(to_edge, strlen(to_edge));
Tcl_ListObjAppendElement(interp, list, obj);

26
util/MinMax.cc
View File

@ -49,9 +49,9 @@ compareMax(float value1,
////////////////////////////////////////////////////////////////
MinMax MinMax::min_("min", 0, INF, std::numeric_limits<int>::max(), compareMin);
MinMax MinMax::max_("max", 1, -INF, std::numeric_limits<int>::min(), compareMax);
const std::array<MinMax*, 2> MinMax::range_{&min_, &max_};
const MinMax MinMax::min_("min", 0, INF, std::numeric_limits<int>::max(), compareMin);
const MinMax MinMax::max_("max", 1, -INF, std::numeric_limits<int>::min(), compareMax);
const std::array<const MinMax*, 2> MinMax::range_{&min_, &max_};
const std::array<int, 2> MinMax::range_index_{min_.index(), max_.index()};
MinMax::MinMax(const char *name,
@ -67,7 +67,7 @@ MinMax::MinMax(const char *name,
{
}
MinMaxAll *
const MinMaxAll *
MinMax::asMinMaxAll() const
{
if (this == &min_)
@ -76,7 +76,7 @@ MinMax::asMinMaxAll() const
return MinMaxAll::max();
}
MinMax *
const MinMax *
MinMax::opposite() const
{
if (this == &max_)
@ -85,7 +85,7 @@ MinMax::opposite() const
return &max_;
}
MinMax *
const MinMax *
MinMax::find(const char *min_max)
{
if (stringEq(min_max, "min")
@ -98,7 +98,7 @@ MinMax::find(const char *min_max)
return nullptr;
}
MinMax *
const MinMax *
MinMax::find(int index)
{
if (index == min_.index())
@ -128,14 +128,14 @@ MinMax::minMax(float value1,
////////////////////////////////////////////////////////////////
MinMaxAll MinMaxAll::min_("min", 0, {MinMax::min()}, {MinMax::min()->index()});
MinMaxAll MinMaxAll::max_("max", 1, {MinMax::max()}, {MinMax::max()->index()});
MinMaxAll MinMaxAll::all_("all", 2, {MinMax::min(), MinMax::max()},
const MinMaxAll MinMaxAll::min_("min", 0, {MinMax::min()}, {MinMax::min()->index()});
const MinMaxAll MinMaxAll::max_("max", 1, {MinMax::max()}, {MinMax::max()->index()});
const MinMaxAll MinMaxAll::all_("all", 2, {MinMax::min(), MinMax::max()},
{MinMax::min()->index(), MinMax::max()->index()});
MinMaxAll::MinMaxAll(const char *name,
int index,
std::vector<MinMax*> range,
std::vector<const MinMax*> range,
std::vector<int> range_index) :
name_(name),
index_(index),
@ -144,7 +144,7 @@ MinMaxAll::MinMaxAll(const char *name,
{
}
MinMax *
const MinMax *
MinMaxAll::asMinMax() const
{
if (this == &min_)
@ -165,7 +165,7 @@ MinMaxAll::matches(const MinMaxAll *min_max) const
return this == &all_ || this == min_max;
}
MinMaxAll *
const MinMaxAll *
MinMaxAll::find(const char *min_max)
{
if (stringEq(min_max, "min")

2
util/RiseFallMinMax.cc
View File

@ -237,7 +237,7 @@ RiseFallMinMax::hasValue(const RiseFall *rf, const MinMax *min_max) const
void
RiseFallMinMax::mergeWith(RiseFallMinMax *rfmm)
{
for (MinMax *min_max : MinMax::range()) {
for (const MinMax *min_max : MinMax::range()) {
int mm_index = min_max->index();
for (int rf_index : RiseFall::rangeIndex()) {
bool exists1 = exists_[rf_index][mm_index];

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