rm WriteSpice.cc,hh
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry
parent
dcecf54641
commit
917f45365a
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@ -1,927 +0,0 @@
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// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2023, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <string>
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#include <iostream>
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#include <fstream>
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#include <regex>
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#include "Machine.hh"
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#include "Debug.hh"
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#include "Error.hh"
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#include "Report.hh"
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#include "StringUtil.hh"
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#include "FuncExpr.hh"
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#include "Liberty.hh"
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#include "TimingArc.hh"
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#include "Network.hh"
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#include "Graph.hh"
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#include "Sdc.hh"
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#include "DcalcAnalysisPt.hh"
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#include "Parasitics.hh"
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#include "PathAnalysisPt.hh"
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#include "Path.hh"
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#include "PathRef.hh"
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#include "PathExpanded.hh"
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#include "StaState.hh"
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#include "WriteSpice.hh"
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namespace sta {
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using std::string;
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using std::ofstream;
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using std::ifstream;
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typedef Vector<string> StringVector;
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typedef Map<string, StringVector*> CellSpicePortNames;
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typedef int Stage;
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typedef Map<ParasiticNode*, int> ParasiticNodeMap;
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void
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split(const string &text,
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const string &delims,
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// Return values.
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StringVector &tokens);
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void
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streamPrint(ofstream &stream,
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const char *fmt,
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...) __attribute__((format (printf, 2, 3)));
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////////////////////////////////////////////////////////////////
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class WriteSpice : public StaState
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{
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public:
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WriteSpice(Path *path,
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const char *spice_filename,
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const char *subckts_filename,
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const char *lib_subckts_filename,
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const char *models_filename,
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const StaState *sta);
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~WriteSpice();
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void writeSpice();;
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private:
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void writeHeader();
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void writeStageInstances();
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void writeInputSource();
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void writeStageSubckts();
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void writeInputStage(Stage stage);
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void writeMeasureStmts();
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void writeGateStage(Stage stage);
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void writeStageVoltageSources(LibertyCell *cell,
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StringVector *spice_port_names,
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const char *inst_name,
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LibertyPort *from_port,
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LibertyPort *drvr_port);
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void writeStageParasitics(Stage stage);
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void writeSubckts();
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void findPathCellnames(// Return values.
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StringSet &path_cell_names);
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void recordSpicePortNames(const char *cell_name,
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StringVector &tokens);
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float pgPortVoltage(const char *pg_port_name,
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LibertyCell *cell);
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float pgPortVoltage(LibertyPgPort *pg_port);
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float maxTime();
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const char *nodeName(ParasiticNode *node);
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void initNodeMap(const char *net_name);
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// Stage "accessors".
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// Internally a stage index from stageFirst() to stageLast()
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// is turned into an index into path_expanded_.
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Stage stageFirst();
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Stage stageLast();
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string stageName(Stage stage);
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int stageGateInputPathIndex(Stage stage);
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int stageDrvrPathIndex(Stage stage);
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int stageLoadPathIndex(Stage stage);
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PathRef *stageGateInputPath(Stage stage);
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PathRef *stageDrvrPath(Stage stage);
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PathRef *stageLoadPath(Stage stage);
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TimingArc *stageGateArc(Stage stage);
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TimingArc *stageWireArc(Stage stage);
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Edge *stageGateEdge(Stage stage);
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Edge *stageWireEdge(Stage stage);
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Pin *stageInputPin(Stage stage);
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Pin *stageDrvrPin(Stage stage);
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Pin *stageLoadPin(Stage stage);
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const char *stageInputPinName(Stage stage);
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const char *stageDrvrPinName(Stage stage);
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const char *stageLoadPinName(Stage stage);
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Path *path_;
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const char *spice_filename_;
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const char *subckts_filename_;
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const char *lib_subckts_filename_;
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const char *models_filename_;
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ofstream spice_stream_;
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PathExpanded path_expanded_;
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CellSpicePortNames cell_spice_port_names_;
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ParasiticNodeMap node_map_;
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int next_node_index_;
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const char *net_name_;
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// Resistance to use to simulate a short circuit between spice nodes.
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static const float short_ckt_resistance_;
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};
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////////////////////////////////////////////////////////////////
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class SubcktEndsMissing : public StaException
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{
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public:
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SubcktEndsMissing(const char *cell_name,
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const char *subckt_filename);;
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const char *what() const throw();
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protected:
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string what_;
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};
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SubcktEndsMissing::SubcktEndsMissing(const char *cell_name,
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const char *subckt_filename)
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{
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what_ = "Error: spice subckt for cell ";
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what_ += cell_name;
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what_ += " missing .ends in ";
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what_ += subckt_filename;
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}
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const char *
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SubcktEndsMissing::what() const throw()
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{
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return what_.c_str();
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}
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////////////////////////////////////////////////////////////////
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void
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writeSpice (Path *path,
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const char *spice_filename,
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const char *subckts_filename,
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const char *lib_subckts_filename,
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const char *models_filename,
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StaState *sta)
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{
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WriteSpice writer(path, spice_filename, subckts_filename,
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lib_subckts_filename, models_filename, sta);
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writer.writeSpice();
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}
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const float WriteSpice::short_ckt_resistance_ = .0001;
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WriteSpice::WriteSpice(Path *path,
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const char *spice_filename,
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const char *subckts_filename,
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const char *lib_subckts_filename,
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const char *models_filename,
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const StaState *sta) :
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StaState(sta),
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path_(path),
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spice_filename_(spice_filename),
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subckts_filename_(subckts_filename),
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lib_subckts_filename_(lib_subckts_filename),
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models_filename_(models_filename),
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path_expanded_(sta),
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net_name_(NULL)
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{
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}
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WriteSpice::~WriteSpice()
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{
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cell_spice_port_names_.deleteContents();
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}
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void
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WriteSpice::writeSpice()
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{
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spice_stream_.open(spice_filename_);
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if (spice_stream_.is_open()) {
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path_expanded_.expand(path_, true);
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// Find subckt port names as a side-effect of writeSubckts.
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writeSubckts();
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writeHeader();
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writeStageInstances();
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writeInputSource();
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writeStageSubckts();
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streamPrint(spice_stream_, ".end\n");
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spice_stream_.close();
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}
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else
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throw FileNotWritable(spice_filename_);
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}
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void
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WriteSpice::writeHeader()
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{
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const MinMax *min_max = path_->minMax(this);
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const Pvt *pvt = sdc_->operatingConditions(min_max);
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if (pvt == NULL)
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pvt = network_->defaultLibertyLibrary()->defaultOperatingConditions();
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float temp = pvt->temperature();
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streamPrint(spice_stream_, ".temp %.1f\n", temp);
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streamPrint(spice_stream_, ".include \"%s\"\n", models_filename_);
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streamPrint(spice_stream_, ".include \"%s\"\n", subckts_filename_);
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float max_time = maxTime();
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float time_step = max_time / 1e+3;
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streamPrint(spice_stream_, ".tran %.3g %.3g\n\n",
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time_step, max_time);
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}
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float
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WriteSpice::maxTime()
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{
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float end_slew = path_->slew(this);
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float max_time = (path_->arrival(this) + end_slew * 2) * 1.5;
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return max_time;
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}
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void
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WriteSpice::writeStageInstances()
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{
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streamPrint(spice_stream_, "*****************\n");
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streamPrint(spice_stream_, "* Stage instances\n");
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streamPrint(spice_stream_, "*****************\n\n");
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for (Stage stage = stageFirst(); stage <= stageLast(); stage++) {
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const char *stage_name = stageName(stage).c_str();
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if (stage == stageFirst())
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streamPrint(spice_stream_, "x%s %s %s %s\n",
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stage_name,
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stageDrvrPinName(stage),
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stageLoadPinName(stage),
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stage_name);
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else
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streamPrint(spice_stream_, "x%s %s %s %s %s\n",
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stage_name,
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stageInputPinName(stage),
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stageDrvrPinName(stage),
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stageLoadPinName(stage),
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stage_name);
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}
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streamPrint(spice_stream_, "\n");
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}
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float
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WriteSpice::pgPortVoltage(const char *pg_port_name,
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LibertyCell *cell)
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{
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auto pg_port = cell->findPgPort(pg_port_name);
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return pgPortVoltage(pg_port);
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}
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float
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WriteSpice::pgPortVoltage(LibertyPgPort *pg_port)
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{
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auto cell = pg_port->cell();
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auto voltage_name = pg_port->voltageName();
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auto lib = cell->libertyLibrary();
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float voltage = lib->supplyVoltage(voltage_name);
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return voltage;
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}
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void
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WriteSpice::writeInputSource()
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{
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streamPrint(spice_stream_, "**************\n");
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streamPrint(spice_stream_, "* Input source\n");
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streamPrint(spice_stream_, "**************\n\n");
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Stage input_stage = stageFirst();
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streamPrint(spice_stream_, "v1 %s 0 pwl(\n",
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stageDrvrPinName(input_stage));
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auto wire_arc = stageWireArc(input_stage);
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auto load_pin = stageLoadPin(input_stage);
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auto cell = network_->libertyCell(network_->instance(load_pin));
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auto load_port = network_->libertyPort(load_pin);
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const char *pg_gnd_port_name = load_port->relatedGroundPin();
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const char *pg_pwr_port_name = load_port->relatedPowerPin();
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auto gnd_volt = pgPortVoltage(pg_gnd_port_name, cell);
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auto pwr_volt = pgPortVoltage(pg_pwr_port_name, cell);
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float volt0, volt1;
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if (wire_arc->fromTrans()->asRiseFall() == TransRiseFall::rise()) {
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volt0 = gnd_volt;
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volt1 = pwr_volt;
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}
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else {
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volt0 = pwr_volt;
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volt1 = gnd_volt;
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}
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float time0 = .1e-9;
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float time1 = .2e-9;
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streamPrint(spice_stream_, "+%.3e %.3e\n", 0.0, volt0);
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streamPrint(spice_stream_, "+%.3e %.3e\n", time0, volt0);
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streamPrint(spice_stream_, "+%.3e %.3e\n", time1, volt1);
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streamPrint(spice_stream_, "+%.3e %.3e\n", maxTime(), volt1);
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streamPrint(spice_stream_, "+)\n\n");
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}
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void
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WriteSpice::writeMeasureStmts()
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{
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streamPrint(spice_stream_, "********************\n");
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streamPrint(spice_stream_, "* Measure statements\n");
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streamPrint(spice_stream_, "********************\n\n");
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}
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void
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WriteSpice::writeStageSubckts()
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{
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streamPrint(spice_stream_, "***************\n");
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streamPrint(spice_stream_, "* Stage subckts\n");
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streamPrint(spice_stream_, "***************\n\n");
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for (Stage stage = stageFirst(); stage <= stageLast(); stage++) {
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if (stage == stageFirst())
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writeInputStage(stage);
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else
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writeGateStage(stage);
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}
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}
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// Input port to first gate input.
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void
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WriteSpice::writeInputStage(Stage stage)
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{
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// Input arc.
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// External driver not handled.
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auto drvr_pin_name = stageDrvrPinName(stage);
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auto load_pin_name = stageLoadPinName(stage);
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streamPrint(spice_stream_, ".subckt %s %s %s\n",
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stageName(stage).c_str(),
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drvr_pin_name,
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load_pin_name);
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writeStageParasitics(stage);
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streamPrint(spice_stream_, ".ends\n\n");
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}
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// Gate and load parasitics.
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void
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WriteSpice::writeGateStage(Stage stage)
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{
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auto input_pin = stageInputPin(stage);
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auto input_pin_name = stageInputPinName(stage);
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auto drvr_pin = stageDrvrPin(stage);
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auto drvr_pin_name = stageDrvrPinName(stage);
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auto load_pin_name = stageLoadPinName(stage);
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streamPrint(spice_stream_, ".subckt stage%d %s %s %s\n",
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stage,
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input_pin_name,
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drvr_pin_name,
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load_pin_name);
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Instance *inst = network_->instance(input_pin);
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const char *inst_name = network_->pathName(inst);
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LibertyCell *cell = network_->libertyCell(inst);
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const char *cell_name = cell->name();
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auto spice_port_names = cell_spice_port_names_[cell_name];
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// Instance subckt call.
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streamPrint(spice_stream_, "x%s", inst_name);
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StringVector::Iterator port_iter(spice_port_names);
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while (port_iter.hasNext()) {
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const char *subckt_port_name = port_iter.next().c_str();
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auto pin = network_->findPin(inst, subckt_port_name);
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auto pg_port = cell->findPgPort(subckt_port_name);
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const char *pin_name;
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if (pin) {
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pin_name = network_->pathName(pin);
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streamPrint(spice_stream_, " %s", pin_name);
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}
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else if (pg_port)
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streamPrint(spice_stream_, " %s/%s", inst_name, subckt_port_name);
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}
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streamPrint(spice_stream_, " %s\n", cell_name);
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writeStageVoltageSources(cell, spice_port_names,
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inst_name,
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network_->libertyPort(input_pin),
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network_->libertyPort(drvr_pin));
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writeStageParasitics(stage);
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streamPrint(spice_stream_, ".ends\n\n");
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}
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typedef Map<LibertyPort*, LogicValue> LibertyPortLogicValues;
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// Find the logic values for expression inputs to enable paths from_port.
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void
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sensitizationValues(FuncExpr *expr,
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LibertyPort *from_port,
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// Return values.
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LibertyPortLogicValues &port_values)
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{
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switch (expr->op()) {
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case FuncExpr::op_port: {
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break;
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}
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case FuncExpr::op_not: {
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sensitizationValues(expr->left(), from_port, port_values);
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break;
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}
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case FuncExpr::op_or: {
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FuncExpr *left = expr->left();
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FuncExpr *right = expr->right();
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if (left->port() == from_port
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&& right->op() == FuncExpr::op_port)
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port_values[right->port()] = logic_zero;
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else if (right->port() == from_port
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&& left->op() == FuncExpr::op_port)
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port_values[left->port()] = logic_zero;
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break;
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}
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case FuncExpr::op_and: {
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FuncExpr *left = expr->left();
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FuncExpr *right = expr->right();
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if (left->port() == from_port
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&& right->op() == FuncExpr::op_port)
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port_values[right->port()] = logic_one;
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else if (right->port() == from_port
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&& left->op() == FuncExpr::op_port)
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port_values[left->port()] = logic_one;
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break;
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}
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case FuncExpr::op_xor: {
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// Need to know timing arc sense to get this right.
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FuncExpr *left = expr->left();
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FuncExpr *right = expr->right();
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if (left->port() == from_port
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&& right->op() == FuncExpr::op_port)
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port_values[right->port()] = logic_zero;
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else if (right->port() == from_port
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&& left->op() == FuncExpr::op_port)
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port_values[left->port()] = logic_zero;
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break;
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}
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case FuncExpr::op_one:
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case FuncExpr::op_zero:
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break;
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}
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}
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// Power/ground and input voltage sources.
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void
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WriteSpice::writeStageVoltageSources(LibertyCell *cell,
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StringVector *spice_port_names,
|
||||
const char *inst_name,
|
||||
LibertyPort *from_port,
|
||||
LibertyPort *drvr_port)
|
||||
{
|
||||
auto from_port_name = from_port->name();
|
||||
auto drvr_port_name = drvr_port->name();
|
||||
LibertyLibrary *lib = cell->libertyLibrary();
|
||||
LibertyPortLogicValues port_values;
|
||||
sensitizationValues(drvr_port->function(), from_port, port_values);
|
||||
int volt_source = 1;
|
||||
debugPrint1(debug_, "write_spice", 2, "subckt %s\n", cell->name());
|
||||
StringVector::Iterator port_iter(spice_port_names);
|
||||
while (port_iter.hasNext()) {
|
||||
auto subckt_port_name = port_iter.next().c_str();
|
||||
auto pg_port = cell->findPgPort(subckt_port_name);
|
||||
debugPrint2(debug_, "write_spice", 2, " port %s%s\n",
|
||||
subckt_port_name,
|
||||
pg_port ? " pwr/gnd" : "");
|
||||
if (pg_port) {
|
||||
auto voltage = pgPortVoltage(pg_port);
|
||||
streamPrint(spice_stream_, "v%d %s/%s 0 %.3f\n",
|
||||
volt_source,
|
||||
inst_name, subckt_port_name,
|
||||
voltage);
|
||||
volt_source++;
|
||||
} else if (!(stringEq(subckt_port_name, from_port_name)
|
||||
|| stringEq(subckt_port_name, drvr_port_name))) {
|
||||
// Input voltage to sensitize path from gate input to output.
|
||||
LibertyPort *port = cell->findLibertyPort(subckt_port_name);
|
||||
if (port) {
|
||||
const char *pg_port_name = NULL;
|
||||
bool port_has_value;
|
||||
LogicValue port_value;
|
||||
port_values.findKey(port, port_value, port_has_value);
|
||||
if (port_has_value) {
|
||||
switch (port_value) {
|
||||
case logic_zero:
|
||||
pg_port_name = port->relatedGroundPin();
|
||||
break;
|
||||
case logic_one:
|
||||
pg_port_name = port->relatedPowerPin();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if (pg_port_name) {
|
||||
auto pg_port = cell->findPgPort(pg_port_name);
|
||||
if (pg_port) {
|
||||
auto voltage_name = pg_port->voltageName();
|
||||
if (voltage_name) {
|
||||
float voltage = lib->supplyVoltage(voltage_name);
|
||||
streamPrint(spice_stream_, "v%d %s/%s 0 %.3f\n",
|
||||
volt_source,
|
||||
inst_name, subckt_port_name,
|
||||
voltage);
|
||||
volt_source++;
|
||||
}
|
||||
else
|
||||
report_->error("port %s %s voltage %s not found,\n",
|
||||
subckt_port_name,
|
||||
pg_port_name,
|
||||
voltage_name);
|
||||
}
|
||||
else
|
||||
report_->error("port %s %s not found,\n",
|
||||
subckt_port_name,
|
||||
pg_port_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
typedef Set<ParasiticDevice*> ParasiticDeviceSet;
|
||||
typedef Set<ParasiticNode*> ParasiticNodeSet;
|
||||
|
||||
void
|
||||
findParasiticDevicesNodes(ParasiticNode *node,
|
||||
Parasitics *parasitics,
|
||||
// Return values.
|
||||
ParasiticNodeSet &nodes,
|
||||
ParasiticDeviceSet &devices)
|
||||
{
|
||||
nodes.insert(node);
|
||||
auto device_iter = parasitics->deviceIterator(node);
|
||||
while (device_iter->hasNext()) {
|
||||
auto device = device_iter->next();
|
||||
if (!devices.hasKey(device)) {
|
||||
devices.insert(device);
|
||||
auto other_node = parasitics->otherNode(device, node);
|
||||
findParasiticDevicesNodes(other_node, parasitics, nodes, devices);
|
||||
}
|
||||
}
|
||||
delete device_iter;
|
||||
}
|
||||
|
||||
void
|
||||
WriteSpice::writeStageParasitics(Stage stage)
|
||||
{
|
||||
auto drvr_path = stageDrvrPath(stage);
|
||||
auto drvr_pin = stageDrvrPin(stage);
|
||||
auto load_pin = stageLoadPin(stage);
|
||||
auto dcalc_ap = drvr_path->dcalcAnalysisPt(this);
|
||||
auto parasitic_ap = dcalc_ap->parasiticAnalysisPt();
|
||||
auto parasitic = parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap);
|
||||
int resistor_index = 1;
|
||||
int cap_index = 1;
|
||||
if (parasitic) {
|
||||
Net *net = network_->net(drvr_pin);
|
||||
auto net_name =
|
||||
net ? network_->pathName(net) : network_->pathName(drvr_pin);
|
||||
initNodeMap(net_name);
|
||||
streamPrint(spice_stream_, "* Net %s\n", net_name);
|
||||
auto node = parasitics_->findNode(parasitic, drvr_pin);
|
||||
ParasiticNodeSet nodes;
|
||||
ParasiticDeviceSet devices;
|
||||
findParasiticDevicesNodes(node, parasitics_, nodes, devices);
|
||||
ParasiticDeviceSet::Iterator device_iter(devices);
|
||||
while (device_iter.hasNext()) {
|
||||
auto device = device_iter.next();
|
||||
auto resistance = parasitics_->value(device, parasitic_ap);
|
||||
if (parasitics_->isResistor(device)) {
|
||||
ParasiticNode *node1, *node2;
|
||||
parasitics_->resistorNodes(device, node1, node2);
|
||||
streamPrint(spice_stream_, "R%d %s %s %.3e\n",
|
||||
resistor_index,
|
||||
nodeName(node1),
|
||||
nodeName(node2),
|
||||
resistance);
|
||||
resistor_index++;
|
||||
}
|
||||
else if (parasitics_->isCouplingCap(device)) {
|
||||
}
|
||||
}
|
||||
ParasiticNodeSet::Iterator node_iter(nodes);
|
||||
while (node_iter.hasNext()) {
|
||||
auto node = node_iter.next();
|
||||
auto cap = parasitics_->nodeGndCap(node, parasitic_ap);
|
||||
streamPrint(spice_stream_, "C%d %s 0 %.3e\n",
|
||||
cap_index,
|
||||
nodeName(node),
|
||||
cap);
|
||||
cap_index++;
|
||||
}
|
||||
}
|
||||
else
|
||||
streamPrint(spice_stream_, "R1 %s %s %.3e\n",
|
||||
network_->pathName(drvr_pin),
|
||||
network_->pathName(load_pin),
|
||||
short_ckt_resistance_);
|
||||
}
|
||||
|
||||
void
|
||||
WriteSpice::initNodeMap(const char *net_name)
|
||||
{
|
||||
stringDelete(net_name_);
|
||||
node_map_.clear();
|
||||
next_node_index_ = 1;
|
||||
net_name_ = stringCopy(net_name);
|
||||
}
|
||||
|
||||
const char *
|
||||
WriteSpice::nodeName(ParasiticNode *node)
|
||||
{
|
||||
auto pin = parasitics_->connectionPin(node);
|
||||
if (pin)
|
||||
return parasitics_->name(node);
|
||||
else {
|
||||
int node_index;
|
||||
bool node_index_exists;
|
||||
node_map_.findKey(node, node_index, node_index_exists);
|
||||
if (!node_index_exists) {
|
||||
node_index = next_node_index_++;
|
||||
node_map_[node] = node_index;
|
||||
}
|
||||
return stringPrintTmp(strlen(net_name_) + 10, "%s/%d",
|
||||
net_name_, node_index);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Copy the subckt definition from lib_subckts_filename for
|
||||
// each cell in path to path_subckts_filename.
|
||||
void
|
||||
WriteSpice::writeSubckts()
|
||||
{
|
||||
StringSet path_cell_names;
|
||||
findPathCellnames(path_cell_names);
|
||||
|
||||
ifstream lib_subckts_stream(lib_subckts_filename_);
|
||||
if (lib_subckts_stream.is_open()) {
|
||||
ofstream subckts_stream(subckts_filename_);
|
||||
if (subckts_stream.is_open()) {
|
||||
string line;
|
||||
while (getline(lib_subckts_stream, line)) {
|
||||
// .subckt <cell_name> [args..]
|
||||
StringVector tokens;
|
||||
split(line, " \t", tokens);
|
||||
if (tokens.size() >= 2
|
||||
&& stringEqual(tokens[0].c_str(), ".subckt")) {
|
||||
const char *cell_name = tokens[1].c_str();
|
||||
if (path_cell_names.hasKey(cell_name)) {
|
||||
subckts_stream << line << "\n";
|
||||
bool found_ends = false;
|
||||
while (getline(lib_subckts_stream, line)) {
|
||||
subckts_stream << line << "\n";
|
||||
if (stringEqual(line.c_str(), ".ends")) {
|
||||
subckts_stream << "\n";
|
||||
found_ends = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!found_ends)
|
||||
throw SubcktEndsMissing(cell_name, lib_subckts_filename_);
|
||||
path_cell_names.eraseKey(cell_name);
|
||||
}
|
||||
recordSpicePortNames(cell_name, tokens);
|
||||
}
|
||||
}
|
||||
subckts_stream.close();
|
||||
lib_subckts_stream.close();
|
||||
|
||||
if (!path_cell_names.empty()) {
|
||||
StringSet::Iterator cell_iter(path_cell_names);
|
||||
report_->error("The following subkcts are missing from %s\n",
|
||||
lib_subckts_filename_);
|
||||
while (cell_iter.hasNext()) {
|
||||
const char *cell_name = cell_iter.next();
|
||||
report_->printError(" %s\n", cell_name);
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
lib_subckts_stream.close();
|
||||
throw FileNotWritable(subckts_filename_);
|
||||
}
|
||||
}
|
||||
else
|
||||
throw FileNotReadable(lib_subckts_filename_);
|
||||
}
|
||||
|
||||
void
|
||||
WriteSpice::findPathCellnames(// Return values.
|
||||
StringSet &path_cell_names)
|
||||
{
|
||||
for (Stage stage = stageFirst(); stage <= stageLast(); stage++) {
|
||||
auto arc = stageGateArc(stage);
|
||||
if (arc) {
|
||||
LibertyCell *cell = arc->set()->libertyCell();
|
||||
if (cell) {
|
||||
debugPrint1(debug_, "write_spice", 2, "cell %s\n", cell->name());
|
||||
path_cell_names.insert(cell->name());
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
WriteSpice::recordSpicePortNames(const char *cell_name,
|
||||
StringVector &tokens)
|
||||
{
|
||||
auto cell = network_->findLibertyCell(cell_name);
|
||||
auto spice_port_names = new StringVector;
|
||||
for (int i = 2; i < tokens.size(); i++) {
|
||||
const char *port_name = tokens[i].c_str();
|
||||
auto port = cell->findLibertyPort(port_name);
|
||||
auto pg_port = cell->findPgPort(port_name);
|
||||
if (port == NULL && pg_port == NULL)
|
||||
report_->error("subckt %s port %s has no corresponding liberty port or pg_port.\n",
|
||||
cell_name, port_name);
|
||||
spice_port_names->push_back(port_name);
|
||||
}
|
||||
cell_spice_port_names_[cell_name] = spice_port_names;
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
Stage
|
||||
WriteSpice::stageFirst()
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
Stage
|
||||
WriteSpice::stageLast()
|
||||
{
|
||||
return (path_expanded_.size() + 1) / 2;
|
||||
}
|
||||
|
||||
string
|
||||
WriteSpice::stageName(Stage stage)
|
||||
{
|
||||
string name;
|
||||
stringPrint(name, "stage%d", stage);
|
||||
return name;
|
||||
}
|
||||
|
||||
int
|
||||
WriteSpice::stageGateInputPathIndex(Stage stage)
|
||||
{
|
||||
return stage * 2 - 3;
|
||||
}
|
||||
|
||||
int
|
||||
WriteSpice::stageDrvrPathIndex(Stage stage)
|
||||
{
|
||||
return stage * 2 - 2;
|
||||
}
|
||||
|
||||
int
|
||||
WriteSpice::stageLoadPathIndex(Stage stage)
|
||||
{
|
||||
return stage * 2 - 1;
|
||||
}
|
||||
|
||||
PathRef *
|
||||
WriteSpice::stageGateInputPath(Stage stage)
|
||||
{
|
||||
int path_index = stageGateInputPathIndex(stage);
|
||||
return path_expanded_.path(path_index);
|
||||
}
|
||||
|
||||
PathRef *
|
||||
WriteSpice::stageDrvrPath(Stage stage)
|
||||
{
|
||||
int path_index = stageDrvrPathIndex(stage);
|
||||
return path_expanded_.path(path_index);
|
||||
}
|
||||
|
||||
PathRef *
|
||||
WriteSpice::stageLoadPath(Stage stage)
|
||||
{
|
||||
int path_index = stageLoadPathIndex(stage);
|
||||
return path_expanded_.path(path_index);
|
||||
}
|
||||
|
||||
TimingArc *
|
||||
WriteSpice::stageGateArc(Stage stage)
|
||||
{
|
||||
int path_index = stageDrvrPathIndex(stage);
|
||||
if (path_index >= 0)
|
||||
return path_expanded_.prevArc(path_index);
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
TimingArc *
|
||||
WriteSpice::stageWireArc(Stage stage)
|
||||
{
|
||||
int path_index = stageLoadPathIndex(stage);
|
||||
return path_expanded_.prevArc(path_index);
|
||||
}
|
||||
|
||||
Edge *
|
||||
WriteSpice::stageGateEdge(Stage stage)
|
||||
{
|
||||
PathRef *path = stageGateInputPath(stage);
|
||||
TimingArc *arc = stageGateArc(stage);
|
||||
return path->prevEdge(arc, this);
|
||||
}
|
||||
|
||||
Edge *
|
||||
WriteSpice::stageWireEdge(Stage stage)
|
||||
{
|
||||
PathRef *path = stageLoadPath(stage);
|
||||
TimingArc *arc = stageWireArc(stage);
|
||||
return path->prevEdge(arc, this);
|
||||
}
|
||||
|
||||
Pin *
|
||||
WriteSpice::stageInputPin(Stage stage)
|
||||
{
|
||||
PathRef *path = stageGateInputPath(stage);
|
||||
return path->pin(this);
|
||||
}
|
||||
|
||||
Pin *
|
||||
WriteSpice::stageDrvrPin(Stage stage)
|
||||
{
|
||||
PathRef *path = stageDrvrPath(stage);
|
||||
return path->pin(this);
|
||||
}
|
||||
|
||||
Pin *
|
||||
WriteSpice::stageLoadPin(Stage stage)
|
||||
{
|
||||
PathRef *path = stageLoadPath(stage);
|
||||
return path->pin(this);
|
||||
}
|
||||
|
||||
const char *
|
||||
WriteSpice::stageInputPinName(Stage stage)
|
||||
{
|
||||
const Pin *pin = stageInputPin(stage);
|
||||
return network_->pathName(pin);
|
||||
}
|
||||
|
||||
const char *
|
||||
WriteSpice::stageDrvrPinName(Stage stage)
|
||||
{
|
||||
Pin *pin = stageDrvrPin(stage);
|
||||
return network_->pathName(pin);
|
||||
}
|
||||
|
||||
const char *
|
||||
WriteSpice::stageLoadPinName(Stage stage)
|
||||
{
|
||||
const Pin *pin = stageLoadPin(stage);
|
||||
return network_->pathName(pin);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
void
|
||||
split(const string &text,
|
||||
const string &delims,
|
||||
// Return values.
|
||||
StringVector &tokens)
|
||||
{
|
||||
auto start = text.find_first_not_of(delims);
|
||||
auto end = text.find_first_of(delims, start);
|
||||
while (end != string::npos) {
|
||||
tokens.push_back(text.substr(start, end - start));
|
||||
start = text.find_first_not_of(delims, end);
|
||||
end = text.find_first_of(delims, start);
|
||||
}
|
||||
if (start != string::npos)
|
||||
tokens.push_back(text.substr(start));
|
||||
}
|
||||
|
||||
// fprintf for c++ streams.
|
||||
// Yes, I hate formatted output to ostream THAT much.
|
||||
void
|
||||
streamPrint(ofstream &stream,
|
||||
const char *fmt,
|
||||
...)
|
||||
{
|
||||
va_list args;
|
||||
va_start(args, fmt);
|
||||
char *result;
|
||||
vasprintf(&result, fmt, args);
|
||||
stream << result;
|
||||
free(result);
|
||||
va_end(args);
|
||||
}
|
||||
|
||||
} // namespace
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
// OpenSTA, Static Timing Analyzer
|
||||
// Copyright (c) 2023, Parallax Software, Inc.
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <https://www.gnu.org/licenses/>.
|
||||
|
||||
#pragma once
|
||||
|
||||
namespace sta {
|
||||
|
||||
// Write a spice deck for path.
|
||||
// Throws FileNotReadable, FileNotWritable, SubcktEndsMissing
|
||||
void
|
||||
writeSpice(Path *path,
|
||||
// Spice file written for path.
|
||||
const char *spice_filename,
|
||||
// Subckts used by path included in spice file.
|
||||
const char *subckts_filename,
|
||||
// File of all cell spice subckt definitions.
|
||||
const char *lib_subckts_filename,
|
||||
// Device model file included in spice file.
|
||||
const char *models_filename,
|
||||
StaState *sta);
|
||||
|
||||
} // namespace
|
||||
#endif
|
||||
Loading…
Reference in New Issue