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Merge pull request #330 from The-OpenROAD-Project-staging/fix-exception-override-priority 

Fix exception_override_priority test for OpenROAD regression
This commit is contained in:
Matt Liberty 2026-04-03 04:45:06 +00:00 committed by GitHub
parent 4c8efd7474 1d38466776
commit 8b4c581a90
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38 changed files with 0 additions and 2124 deletions
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106
sdc/test/sdc_capacitance_propagated.ok
View File

@ -1,106 +0,0 @@
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (propagated)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

36
sdc/test/sdc_capacitance_propagated.tcl
View File

@ -29,9 +29,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Test 1: set_load - basic pin and wire loads
############################################################
set_load 0.05 [get_ports out1]
set_load -pin_load 0.04 [get_ports out1]
@ -40,39 +38,29 @@ set_load -wire_load 0.02 [get_ports out1]
set_load -pin_load 0.03 [get_ports out2]
############################################################
# Test 2: set_load with rise/fall
############################################################
set_load -pin_load -rise 0.045 [get_ports out1]
set_load -pin_load -fall 0.055 [get_ports out1]
set_load -wire_load -rise 0.015 [get_ports out2]
set_load -wire_load -fall 0.025 [get_ports out2]
############################################################
# Test 3: set_load with min/max
############################################################
set_load -min 0.01 [get_ports out1]
set_load -max 0.06 [get_ports out1]
set_load -pin_load -min 0.02 [get_ports out2]
set_load -pin_load -max 0.05 [get_ports out2]
############################################################
# Test 4: Port fanout number
############################################################
set_port_fanout_number 4 [get_ports out1]
set_port_fanout_number 8 [get_ports out2]
############################################################
# Test 5: Net wire cap (set_load on nets)
############################################################
set_load 0.01 [get_nets n1]
set_load 0.02 [get_nets n2]
############################################################
# Test 6: Capacitance limits
############################################################
# Design-level
set_max_capacitance 0.25 [current_design]
@ -102,9 +90,7 @@ set_max_area 200.0
set sdc1 [make_result_file sdc_cap_prop1.sdc]
write_sdc -no_timestamp $sdc1
############################################################
# Test 7: Propagated clocks - set and unset
############################################################
# Set propagated on clock object
set_propagated_clock [get_clocks clk1]
@ -126,9 +112,7 @@ unset_propagated_clock [get_ports clk2]
set sdc3 [make_result_file sdc_cap_prop3.sdc]
write_sdc -no_timestamp $sdc3
############################################################
# Test 8: Case analysis - all 4 values and unset
############################################################
# Value 0
set_case_analysis 0 [get_ports in1]
@ -160,30 +144,10 @@ write_sdc -no_timestamp $sdc5
# Unset
unset_case_analysis [get_ports in1]
############################################################
# Test 9: Logic values
############################################################
set_logic_zero [get_ports in1]
set_logic_one [get_ports in2]
set_logic_dc [get_ports in3]
set sdc6 [make_result_file sdc_cap_prop6.sdc]
write_sdc -no_timestamp $sdc6
############################################################
# Test 10: Read back and verify roundtrip
############################################################
read_sdc $sdc1
report_checks
set sdc7 [make_result_file sdc_cap_prop7.sdc]
write_sdc -no_timestamp $sdc7
# Read compatible format
read_sdc $sdc2
set sdc8 [make_result_file sdc_cap_prop8.sdc]
write_sdc -no_timestamp -compatible $sdc8
report_checks

404
sdc/test/sdc_clock_operations.ok
View File

@ -1112,407 +1112,3 @@ clk1 10.00 0.00 5.00
Clock Period Waveform
----------------------------------------------------
clk2 20.00 5.00 15.00
--- read_sdc ---
Warning 1061: generated clock gclk_div2 pin clk1 is in the fanout of multiple clocks.
Warning 1061: generated clock gclk_edge pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.10 10.10 clock network delay (propagated)
-0.20 9.90 clock uncertainty
0.00 9.90 clock reconvergence pessimism
-3.00 6.90 output external delay
6.90 data required time
---------------------------------------------------------
6.90 data required time
-5.00 data arrival time
---------------------------------------------------------
1.90 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset_clock_latency ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
-0.20 9.80 clock uncertainty
0.00 9.80 clock reconvergence pessimism
-3.00 6.80 output external delay
6.80 data required time
---------------------------------------------------------
6.80 data required time
-5.00 data arrival time
---------------------------------------------------------
1.80 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset_clock_uncertainty ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-5.00 data arrival time
---------------------------------------------------------
2.00 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset inter-clock uncertainty ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (propagated)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-5.00 data arrival time
---------------------------------------------------------
2.00 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)
--- unset_propagated_clock ---
Startpoint: reg2/Q (clock source 'gclk_edge')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gclk_edge (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-5.00 data arrival time
---------------------------------------------------------
2.00 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_alt)
Path Group: clk1_alt
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk2 (rise edge)
0.40 5.40 clock network delay (ideal)
2.00 7.40 v input external delay
0.00 7.40 v in3 (in)
0.05 7.45 v or1/ZN (OR2_X1)
0.03 7.47 ^ nor1/ZN (NOR2_X1)
0.00 7.47 ^ reg2/D (DFF_X1)
7.47 data arrival time
10.00 10.00 clock clk1_alt (rise edge)
0.00 10.00 clock network delay (propagated)
-0.25 9.75 clock uncertainty
0.00 9.75 clock reconvergence pessimism
9.75 ^ reg2/CK (DFF_X1)
-0.03 9.72 library setup time
9.72 data required time
---------------------------------------------------------
9.72 data required time
-7.47 data arrival time
---------------------------------------------------------
2.24 slack (MET)
Startpoint: reg3/Q (clock source 'gclk_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
1.67 1.67 clock gclk_mul3 (rise edge)
0.00 1.67 clock network delay
1.67 ^ out2 (out)
1.67 data arrival time
5.00 5.00 clock clk2 (rise edge)
0.20 5.20 clock network delay (ideal)
-0.15 5.05 clock uncertainty
0.00 5.05 clock reconvergence pessimism
-3.00 2.05 output external delay
2.05 data required time
---------------------------------------------------------
2.05 data required time
-1.67 data arrival time
---------------------------------------------------------
0.38 slack (MET)

68
sdc/test/sdc_clock_operations.tcl
View File

@ -23,9 +23,7 @@ set_input_delay -clock [create_clock -name clk1 -period 10 [get_ports clk1]] 2.0
set_input_delay -clock clk1 2.0 [get_ports in2]
set_output_delay -clock clk1 3.0 [get_ports out1]
############################################################
# Create clocks with different waveforms
############################################################
puts "--- clock with custom waveform ---"
create_clock -name clk2 -period 20 -waveform {5 15} [get_ports clk2]
set_input_delay -clock clk2 2.0 [get_ports in3]
@ -39,9 +37,7 @@ puts "--- clock with -add ---"
create_clock -name clk1_alt -period 5 -add [get_ports clk1]
report_checks
############################################################
# Generated clocks with various options
############################################################
puts "--- generated clock divide_by ---"
create_generated_clock -name gclk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
report_checks
@ -54,9 +50,7 @@ puts "--- generated clock edges ---"
create_generated_clock -name gclk_edge -source [get_ports clk1] -edges {1 3 5} [get_pins reg2/Q]
report_checks
############################################################
# Propagated clock
############################################################
puts "--- set_propagated_clock ---"
set_propagated_clock [get_clocks clk1]
set_propagated_clock [get_clocks clk2]
@ -65,9 +59,7 @@ report_checks
puts "--- set_propagated_clock on pin ---"
set_propagated_clock [get_ports clk1]
############################################################
# Clock slew/transition
############################################################
puts "--- clock transition ---"
set_clock_transition -rise -max 0.15 [get_clocks clk1]
set_clock_transition -fall -min 0.08 [get_clocks clk1]
@ -76,9 +68,7 @@ set_clock_transition -rise 0.12 [get_clocks clk1]
set_clock_transition -fall 0.09 [get_clocks clk1]
report_checks
############################################################
# Clock latency - source and non-source
############################################################
puts "--- clock latency source ---"
set_clock_latency -source 0.5 [get_clocks clk1]
set_clock_latency -source -early 0.3 [get_clocks clk1]
@ -93,9 +83,7 @@ set_clock_latency -rise -max 0.4 [get_clocks clk2]
set_clock_latency -fall -min 0.1 [get_clocks clk2]
report_checks
############################################################
# Clock insertion
############################################################
puts "--- clock insertion ---"
set_clock_latency -source -rise -early 0.1 [get_clocks clk1]
set_clock_latency -source -rise -late 0.3 [get_clocks clk1]
@ -103,18 +91,14 @@ set_clock_latency -source -fall -early 0.15 [get_clocks clk1]
set_clock_latency -source -fall -late 0.35 [get_clocks clk1]
report_checks
############################################################
# Clock uncertainty - simple
############################################################
puts "--- clock uncertainty ---"
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
set_clock_uncertainty 0.15 [get_clocks clk2]
report_checks
############################################################
# Inter-clock uncertainty
############################################################
puts "--- inter-clock uncertainty ---"
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
@ -122,17 +106,13 @@ set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
report_checks
############################################################
# Clock uncertainty on pin
############################################################
puts "--- clock uncertainty on pin ---"
set_clock_uncertainty -setup 0.25 [get_ports clk1]
set_clock_uncertainty -hold 0.08 [get_ports clk1]
report_checks
############################################################
# Write SDC
############################################################
puts "--- write_sdc ---"
set sdc1 [make_result_file sdc_clock_ops1.sdc]
write_sdc -no_timestamp $sdc1
@ -141,61 +121,13 @@ puts "--- write_sdc compatible ---"
set sdc2 [make_result_file sdc_clock_ops2.sdc]
write_sdc -no_timestamp -compatible $sdc2
############################################################
# Remove clock and re-create
############################################################
puts "--- delete_clock ---"
delete_clock [get_clocks vclk1]
report_checks
############################################################
# Clock properties reporting
############################################################
puts "--- report_clock_properties ---"
report_clock_properties
report_clock_properties clk1
report_clock_properties clk2
############################################################
# Read SDC back
############################################################
puts "--- read_sdc ---"
read_sdc $sdc1
report_checks
############################################################
# Remove clock latency
############################################################
puts "--- unset_clock_latency ---"
unset_clock_latency -source [get_clocks clk1]
report_checks
############################################################
# Remove clock uncertainty
############################################################
puts "--- unset_clock_uncertainty ---"
unset_clock_uncertainty -setup [get_clocks clk1]
unset_clock_uncertainty -hold [get_clocks clk1]
report_checks
############################################################
# Remove inter-clock uncertainty
############################################################
puts "--- unset inter-clock uncertainty ---"
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup
unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
report_checks
############################################################
# Remove propagated clock
############################################################
puts "--- unset_propagated_clock ---"
unset_propagated_clock [get_clocks clk1]
unset_propagated_clock [get_clocks clk2]
report_checks
############################################################
# Final write
############################################################
set sdc3 [make_result_file sdc_clock_ops3.sdc]
write_sdc -no_timestamp $sdc3

57
sdc/test/sdc_clock_removal_cascade.ok
View File

@ -156,60 +156,3 @@ Path Type: max
1.92 slack (MET)
Startpoint: in1 (input port clocked by clk_master)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
Path Group: clk_master
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk_master (fall edge)
0.60 5.60 clock network delay (propagated)
2.50 8.10 v input external delay
0.00 8.10 v in1 (in)
0.02 8.12 v buf1/Z (BUF_X1)
0.05 8.17 v or1/ZN (OR2_X1)
0.03 8.19 ^ nor1/ZN (NOR2_X1)
0.00 8.19 ^ reg2/D (DFF_X1)
8.19 data arrival time
10.00 10.00 clock clk_master (rise edge)
0.30 10.30 clock network delay (propagated)
-0.15 10.15 clock uncertainty
0.00 10.15 clock reconvergence pessimism
10.15 ^ reg2/CK (DFF_X1)
-0.03 10.12 library setup time
10.12 data required time
---------------------------------------------------------
10.12 data required time
-8.19 data arrival time
---------------------------------------------------------
1.92 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_new)
Endpoint: out2 (output port clocked by clk_new)
Path Group: clk_new
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk_new (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
15.00 15.00 clock clk_new (rise edge)
0.00 15.00 clock network delay (ideal)
0.00 15.00 clock reconvergence pessimism
-3.00 12.00 output external delay
12.00 data required time
---------------------------------------------------------
12.00 data required time
-0.08 data arrival time
---------------------------------------------------------
11.92 slack (MET)

15
sdc/test/sdc_clock_removal_cascade.tcl
View File

@ -24,9 +24,7 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdc_test2.v
link_design sdc_test2
############################################################
# Phase 1: Create complex clock hierarchy
############################################################
create_clock -name clk_master -period 10 [get_ports clk1]
create_clock -name clk_aux -period 20 -waveform {0 10} [get_ports clk2]
create_clock -name vclk1 -period 5
@ -101,9 +99,7 @@ write_sdc -no_timestamp $sdc1
report_checks
############################################################
# Phase 2: Delete virtual clocks (simpler cascade)
############################################################
delete_clock [get_clocks vclk1]
delete_clock [get_clocks vclk2]
@ -113,9 +109,7 @@ report_clock_properties
set sdc2 [make_result_file sdc_clkremoval2.sdc]
write_sdc -no_timestamp $sdc2
############################################################
# Phase 3: Delete generated clocks
############################################################
delete_generated_clock [get_clocks gclk_div2]
delete_generated_clock [get_clocks gclk_div4]
@ -124,17 +118,13 @@ delete_generated_clock [get_clocks gclk_mul2]
report_clock_properties
############################################################
# Phase 4: Delete the -add clock on clk1 port
############################################################
delete_clock [get_clocks clk_master_alt]
set sdc3 [make_result_file sdc_clkremoval3.sdc]
write_sdc -no_timestamp $sdc3
############################################################
# Phase 5: Delete master clock (cascades to remove all refs)
############################################################
delete_clock [get_clocks clk_aux]
report_clock_properties
@ -144,9 +134,7 @@ write_sdc -no_timestamp $sdc4
report_checks
############################################################
# Phase 6: Re-create everything fresh
############################################################
create_clock -name clk_new -period 15 [get_ports clk2]
create_generated_clock -name gclk_new -source [get_ports clk1] -divide_by 3 [get_pins reg1/Q]
@ -164,6 +152,3 @@ set_false_path -from [get_clocks clk_master] -to [get_clocks clk_new]
set sdc5 [make_result_file sdc_clkremoval5.sdc]
write_sdc -no_timestamp $sdc5
read_sdc $sdc5
report_checks

52
sdc/test/sdc_delay_borrow_group.ok
View File

@ -1,52 +0,0 @@
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.30 0.30 clock network delay (ideal)
0.00 0.30 ^ reg2/CK (DFF_X1)
0.08 0.38 ^ reg2/Q (DFF_X1)
0.00 0.38 ^ out1 (out)
0.38 data arrival time
5.00 5.00 clock clk1 (fall edge)
0.30 5.30 clock network delay (ideal)
0.00 5.30 clock reconvergence pessimism
-3.20 2.10 output external delay
2.10 data required time
---------------------------------------------------------
2.10 data required time
-0.38 data arrival time
---------------------------------------------------------
1.72 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.20 0.20 clock network delay (ideal)
0.00 0.20 ^ reg3/CK (DFF_X1)
0.08 0.28 ^ reg3/Q (DFF_X1)
0.00 0.28 ^ out2 (out)
0.28 data arrival time
10.00 10.00 clock clk2 (fall edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-2.80 7.20 output external delay
7.20 data required time
---------------------------------------------------------
7.20 data required time
-0.28 data arrival time
---------------------------------------------------------
6.92 slack (MET)

38
sdc/test/sdc_delay_borrow_group.tcl
View File

@ -25,16 +25,12 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdc_test2.v
link_design sdc_test2
############################################################
# Setup clocks
############################################################
create_clock -name clk1 -period 10 [get_ports clk1]
create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
create_clock -name vclk -period 8
############################################################
# Input delays with -source_latency_included
############################################################
set_input_delay -clock clk1 -source_latency_included 2.0 [get_ports in1]
set_input_delay -clock clk1 -network_latency_included 1.8 [get_ports in2]
@ -48,9 +44,7 @@ set_input_delay -clock clk1 -clock_fall -source_latency_included -add_delay 2.2
set_input_delay -clock clk1 -rise -max -source_latency_included 3.0 [get_ports in2] -add_delay
set_input_delay -clock clk1 -fall -min -network_latency_included 0.5 [get_ports in2] -add_delay
############################################################
# Output delays with -source_latency_included
############################################################
set_output_delay -clock clk1 -source_latency_included 3.0 [get_ports out1]
set_output_delay -clock clk2 -network_latency_included 2.5 [get_ports out2]
@ -65,9 +59,7 @@ set_output_delay -clock clk1 -rise -min 1.5 [get_ports out1] -add_delay
set_output_delay -clock clk1 -fall -max 3.2 [get_ports out1] -add_delay
set_output_delay -clock clk1 -fall -min 1.2 [get_ports out1] -add_delay
############################################################
# Propagated clock + remove propagated clock
############################################################
set_propagated_clock [get_clocks clk1]
# Setting clock latency removes propagated clock
@ -78,9 +70,7 @@ set_propagated_clock [get_ports clk2]
set_clock_latency 0.2 [get_ports clk2]
############################################################
# Latch borrow limits on all three target types
############################################################
set_max_time_borrow 2.0 [get_clocks clk1]
set_max_time_borrow 1.5 [get_clocks clk2]
@ -91,9 +81,7 @@ set_max_time_borrow 1.2 [get_cells reg1]
set_max_time_borrow 0.9 [get_cells reg3]
############################################################
# Min pulse width on all targets
############################################################
# Global
set_min_pulse_width 0.5
@ -113,14 +101,10 @@ set_min_pulse_width -low 0.25 [get_pins reg2/CK]
# Instance
set_min_pulse_width 0.45 [get_cells reg3]
############################################################
# set_max_area
############################################################
set_max_area 250.0
############################################################
# Group paths - default and named with through
############################################################
group_path -default -from [get_ports in1] -to [get_ports out1]
group_path -name grp_thru -from [get_ports in2] \
@ -131,14 +115,10 @@ group_path -name grp_clk -from [get_clocks clk1] -to [get_clocks clk2]
# Duplicate group path (same name, same from/to - exercises hasKey path)
group_path -name grp_clk -from [get_clocks clk1] -to [get_clocks clk2]
############################################################
# Clock groups - logically_exclusive (exercises clockGroupsAreSame)
############################################################
set_clock_groups -logically_exclusive -group {clk1} -group {clk2}
############################################################
# False paths and multicycle with -setup/-hold for exceptions
############################################################
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
@ -149,16 +129,12 @@ set_multicycle_path -setup -start 3 -from [get_ports in2] -to [get_ports out1]
# Multicycle with -end for hold
set_multicycle_path -hold -end 1 -from [get_ports in2] -to [get_ports out1]
############################################################
# Max/min delay with -ignore_clock_latency
############################################################
set_max_delay -from [get_ports in3] -to [get_ports out2] -ignore_clock_latency 7.0
set_min_delay -from [get_ports in3] -to [get_ports out2] 0.5
############################################################
# Write SDC
############################################################
set sdc1 [make_result_file sdc_delay_borrow_group1.sdc]
write_sdc -no_timestamp $sdc1
@ -168,9 +144,7 @@ write_sdc -no_timestamp -compatible $sdc2
set sdc3 [make_result_file sdc_delay_borrow_group3.sdc]
write_sdc -no_timestamp -digits 8 $sdc3
############################################################
# Remove some constraints and re-write
############################################################
unset_input_delay -clock clk1 [get_ports in1]
unset_output_delay -clock clk1 [get_ports out1]
@ -178,15 +152,3 @@ unset_output_delay -clock clk1 [get_ports out1]
# Unset path exceptions
unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk2]
unset_path_exceptions -hold -from [get_clocks clk2] -to [get_clocks clk1]
############################################################
# Read back SDC and report
############################################################
read_sdc $sdc1
report_checks
############################################################
# Re-write after read
############################################################
set sdc4 [make_result_file sdc_delay_borrow_group4.sdc]
write_sdc -no_timestamp $sdc4

76
sdc/test/sdc_design_rules_limits.ok
View File

@ -1,76 +0,0 @@
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
max slew
Pin Limit Slew Slack
------------------------------------------------------------
nor1/ZN 0.20 0.01 0.19 (MET)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
in1 10 1 9 (MET)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
or1/ZN 0.20 3.32 -3.12 (VIOLATED)
Required Actual
Pin Width Width Slack
------------------------------------------------------------
reg2/CK (high) 0.35 5.00 4.65 (MET)

35
sdc/test/sdc_design_rules_limits.tcl
View File

@ -26,9 +26,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Max/min transition limits on design, ports, and clocks
############################################################
set_max_transition 0.5 [current_design]
set_max_transition 0.3 [get_ports out1]
@ -44,9 +42,7 @@ set_max_transition -clock_path -fall 0.22 [get_clocks clk2]
set_max_transition -data_path -rise 0.38 [get_clocks clk2]
set_max_transition -data_path -fall 0.42 [get_clocks clk2]
############################################################
# Max/min capacitance limits
############################################################
set_max_capacitance 0.2 [current_design]
set_max_capacitance 0.1 [get_ports out1]
@ -60,22 +56,16 @@ set_min_capacitance 0.001 [current_design]
set_min_capacitance 0.0005 [get_ports out1]
############################################################
# Max/min fanout limits
############################################################
set_max_fanout 20 [current_design]
set_max_fanout 10 [get_ports in1]
set_max_fanout 15 [get_ports in2]
############################################################
# Max area
############################################################
set_max_area 500.0
############################################################
# Min pulse width on various targets
############################################################
# Global min pulse width
set_min_pulse_width 0.5
@ -95,9 +85,7 @@ set_min_pulse_width -low 0.25 [get_pins reg2/CK]
# Instance min pulse width
set_min_pulse_width 0.45 [get_cells reg3]
############################################################
# Latch borrow limits
############################################################
set_max_time_borrow 2.0 [get_clocks clk1]
set_max_time_borrow 1.5 [get_clocks clk2]
@ -105,15 +93,11 @@ set_max_time_borrow 1.0 [get_pins reg1/D]
set_max_time_borrow 1.2 [get_cells reg2]
############################################################
# Port slew limits
############################################################
set_max_transition 0.25 [get_ports in1]
set_max_transition 0.28 [get_ports in2]
############################################################
# Write SDC (exercises all design rule writing paths)
############################################################
set sdc1 [make_result_file sdc_design_rules1.sdc]
write_sdc -no_timestamp $sdc1
@ -122,22 +106,3 @@ write_sdc -no_timestamp -compatible $sdc2
set sdc3 [make_result_file sdc_design_rules3.sdc]
write_sdc -no_timestamp -digits 8 $sdc3
############################################################
# Read back and verify
############################################################
read_sdc $sdc1
report_checks
############################################################
# Check reporting
############################################################
report_check_types -max_slew -max_capacitance -max_fanout
report_check_types -min_pulse_width -min_period
############################################################
# Final write after read
############################################################
set sdc4 [make_result_file sdc_design_rules4.sdc]
write_sdc -no_timestamp $sdc4

53
sdc/test/sdc_drive_input_pvt.ok
View File

@ -210,56 +210,3 @@ Path Type: max
9.88 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

43
sdc/test/sdc_drive_input_pvt.tcl
View File

@ -30,9 +30,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Input transition / slew
############################################################
set_input_transition 0.15 [get_ports in1]
set_input_transition -rise -max 0.12 [get_ports in2]
set_input_transition -fall -min 0.08 [get_ports in2]
@ -42,9 +40,7 @@ set_input_transition -rise -min 0.06 [get_ports in1]
set_input_transition -fall -max 0.18 [get_ports in1]
report_checks
############################################################
# Drive resistance
############################################################
set_drive 100 [get_ports in1]
set_drive -rise 120 [get_ports in2]
@ -57,9 +53,7 @@ set_drive -fall -max 110 [get_ports in3]
report_checks
############################################################
# Driving cells - basic
############################################################
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
@ -86,25 +80,19 @@ set_driving_cell -lib_cell INV_X8 -pin ZN -max [get_ports in1]
report_checks
############################################################
# Write SDC - exercises writing drive resistance and driving cell
############################################################
set sdc1 [make_result_file sdc_drive_input1.sdc]
write_sdc -no_timestamp $sdc1
set sdc2 [make_result_file sdc_drive_input2.sdc]
write_sdc -no_timestamp -compatible $sdc2
############################################################
# Operating conditions
############################################################
set_operating_conditions typical
report_checks
############################################################
# Analysis type
############################################################
sta::set_analysis_type_cmd single
sta::set_analysis_type_cmd bc_wc
@ -119,16 +107,12 @@ set_operating_conditions -analysis_type bc_wc
set_operating_conditions -analysis_type single
############################################################
# PVT settings on instances
############################################################
set_pvt [get_cells buf1] -process 1.0 -voltage 1.1 -temperature 25.0
set_pvt [get_cells inv1] -process 0.9 -voltage 1.0 -temperature 85.0
############################################################
# Wire load model and mode
############################################################
set_wire_load_model -name "5K_hvratio_1_1"
set_wire_load_mode enclosed
@ -137,40 +121,13 @@ set_wire_load_mode top
set_wire_load_mode segmented
############################################################
# Propagate all clocks variable
############################################################
sta::set_propagate_all_clocks 1
############################################################
# Write after all environment settings
############################################################
set sdc3 [make_result_file sdc_drive_input3.sdc]
write_sdc -no_timestamp $sdc3
# Write with digits
set sdc4 [make_result_file sdc_drive_input4.sdc]
write_sdc -no_timestamp -digits 6 $sdc4
############################################################
# Read back and verify
############################################################
read_sdc $sdc1
report_checks
############################################################
# Port external capacitance
############################################################
set_load -pin_load 0.05 [get_ports out1]
set_load -wire_load 0.02 [get_ports out1]
set_load -pin_load -rise 0.04 [get_ports out2]
set_load -pin_load -fall 0.045 [get_ports out2]
set_port_fanout_number 4 [get_ports out1]
set_port_fanout_number 6 [get_ports out2]
############################################################
# Final write
############################################################
set sdc5 [make_result_file sdc_drive_input5.sdc]
write_sdc -no_timestamp $sdc5

108
sdc/test/sdc_exception_advanced.ok
View File

@ -79,111 +79,3 @@ Path Type: max
No paths found.
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk_cross
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: reg2reg
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.07 ^ nor1/ZN (NOR2_X1)
0.00 2.07 ^ reg2/D (DFF_X1)
2.07 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-2.07 data arrival time
---------------------------------------------------------
7.89 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)

26
sdc/test/sdc_exception_advanced.tcl
View File

@ -8,9 +8,7 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdc_test2.v
link_design sdc_test2
############################################################
# Setup clocks and basic delays
############################################################
create_clock -name clk1 -period 10 [get_ports clk1]
create_clock -name clk2 -period 20 [get_ports clk2]
@ -20,9 +18,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# False path with rise/fall from/to combinations
############################################################
# rise_from to specific port
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
@ -45,16 +41,12 @@ set_false_path -fall_from [get_ports in3] -rise_to [get_ports out2]
# Report after false paths
report_checks
############################################################
# Write SDC (to cover exception writing with rise/fall)
############################################################
set sdc_file1 [make_result_file sdc_exception_adv1.sdc]
write_sdc -no_timestamp $sdc_file1
############################################################
# Unset all false paths and create through paths
############################################################
unset_path_exceptions -rise_from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -fall_from [get_ports in2] -to [get_ports out1]
@ -63,9 +55,7 @@ unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out2]
unset_path_exceptions -rise_from [get_ports in3] -fall_to [get_ports out1]
unset_path_exceptions -fall_from [get_ports in3] -rise_to [get_ports out2]
############################################################
# False path with -through
############################################################
set_false_path -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out1]
@ -82,9 +72,7 @@ unset_path_exceptions -from [get_ports in1] -through [get_pins buf1/Z] -to [get_
unset_path_exceptions -from [get_ports in2] -through [get_pins inv1/ZN] -through [get_pins and1/ZN] -to [get_ports out1]
unset_path_exceptions -from [get_ports in1] -through [get_pins or1/ZN] -to [get_ports out2]
############################################################
# Multicycle path with rise/fall combinations
############################################################
# Setup multicycle with rise_from
set_multicycle_path -setup 2 -rise_from [get_ports in1] -to [get_ports out1]
@ -107,9 +95,7 @@ write_sdc -no_timestamp $sdc_file3
# Report
report_checks -from [get_ports in1] -to [get_ports out1]
############################################################
# Unset multicycles and add max/min delay
############################################################
unset_path_exceptions -setup -rise_from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -hold -from [get_ports in1] -fall_to [get_ports out1]
@ -117,9 +103,7 @@ unset_path_exceptions -setup -from [get_clocks clk1] -to [get_clocks clk2]
unset_path_exceptions -hold -from [get_clocks clk1] -to [get_clocks clk2]
unset_path_exceptions -setup -from [get_ports in2] -through [get_pins and1/ZN] -to [get_ports out1]
############################################################
# Max/min delay with various options
############################################################
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
set_min_delay -from [get_ports in1] -to [get_ports out1] 1.0
@ -140,9 +124,7 @@ write_sdc -no_timestamp -compatible $sdc_file5
set sdc_file6 [make_result_file sdc_exception_adv6.sdc]
write_sdc -no_timestamp -digits 6 $sdc_file6
############################################################
# Group paths (exercises group_path writing)
############################################################
group_path -name reg2reg -from [get_clocks clk1] -to [get_clocks clk1]
group_path -name in2out -from [get_ports {in1 in2 in3}] -to [get_ports {out1 out2}]
@ -155,11 +137,3 @@ report_checks -path_group in2out
# Write with group paths
set sdc_file7 [make_result_file sdc_exception_adv7.sdc]
write_sdc -no_timestamp $sdc_file7
############################################################
# Read back SDC to verify
############################################################
read_sdc $sdc_file4
report_checks

1
sdc/test/sdc_exception_intersect.ok
View File

@ -2,4 +2,3 @@ No differences found.
No differences found.
No differences found.
No differences found.
No differences found.

20
sdc/test/sdc_exception_intersect.tcl
View File

@ -31,9 +31,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Exception with -through using nets, instances, and pins combined
############################################################
# Through net only
set_false_path -through [get_nets n1] -to [get_ports out1]
@ -63,16 +61,12 @@ set_false_path -from [get_ports in1] \
-fall_through [get_pins buf1/Z] \
-to [get_ports out2]
############################################################
# Write SDC with through exceptions
############################################################
set sdc1 [make_result_file sdc_exception_int1.sdc]
write_sdc -no_timestamp $sdc1
diff_files sdc_exception_int1.sdcok $sdc1
############################################################
# Unset all paths and create new set for merging tests
############################################################
unset_path_exceptions -through [get_nets n1] -to [get_ports out1]
unset_path_exceptions -through [get_cells inv1] -to [get_ports out2]
unset_path_exceptions -from [get_ports in1] -through [get_pins buf1/Z] -through [get_nets n3] -to [get_ports out1]
@ -80,9 +74,7 @@ unset_path_exceptions -from [get_ports in2] -through [get_cells and1] -through [
unset_path_exceptions -from [get_ports in3] -rise_through [get_pins or1/ZN] -to [get_ports out2]
unset_path_exceptions -from [get_ports in1] -fall_through [get_pins buf1/Z] -to [get_ports out2]
############################################################
# Exception merging: multiple exceptions on overlapping paths
############################################################
# False path that should merge when same from/to
set_false_path -from [get_ports in1] -to [get_ports out1]
@ -123,9 +115,7 @@ group_path -name grp_inst \
-through [get_cells and1] \
-to [get_ports out1]
############################################################
# Write SDC with all exception types
############################################################
set sdc2 [make_result_file sdc_exception_int2.sdc]
write_sdc -no_timestamp $sdc2
diff_files sdc_exception_int2.sdcok $sdc2
@ -137,13 +127,3 @@ diff_files sdc_exception_int3.sdcok $sdc3
set sdc4 [make_result_file sdc_exception_int4.sdc]
write_sdc -no_timestamp -digits 6 $sdc4
diff_files sdc_exception_int4.sdcok $sdc4
############################################################
# Read back SDC
############################################################
read_sdc $sdc2
# Re-write to verify roundtrip
set sdc5 [make_result_file sdc_exception_int5.sdc]
write_sdc -no_timestamp $sdc5
diff_files sdc_exception_int5.sdcok $sdc5

21
sdc/test/sdc_exception_match_filter.tcl
View File

@ -24,9 +24,7 @@ set_output_delay -clock clk2 3.0 [get_ports out2]
report_checks > /dev/null
############################################################
# Test 1: Multi-thru false paths with pin types
############################################################
puts "--- multi-thru state matching ---"
# 2-stage thru: pin then pin
@ -50,9 +48,7 @@ unset_path_exceptions -from [get_ports in2] -through [get_pins inv1/ZN] \
-through [get_pins nand1/ZN] -to [get_ports out1]
report_checks -path_delay max
############################################################
# Test 2: Exception filter matching (report_checks -from/-to/-through)
############################################################
puts "--- exception filter matching ---"
set_false_path -from [get_ports in1] -to [get_ports out2]
@ -74,18 +70,14 @@ report_checks -path_delay max -through [get_pins buf1/Z]
puts "--- report_checks -through instance ---"
report_checks -path_delay max -through [get_cells and1]
############################################################
# Test 3: Unset exceptions
############################################################
puts "--- unset all exceptions ---"
unset_path_exceptions -from [get_ports in1] -to [get_ports out2]
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
unset_path_exceptions -from [get_ports in3] -to [get_ports out2]
report_checks -path_delay max
############################################################
# Test 4: group_path with filter
############################################################
puts "--- group_path filter ---"
group_path -name gp_in1 -from [get_ports in1]
group_path -name gp_out1 -to [get_ports out1]
@ -95,9 +87,7 @@ report_checks -path_delay max -path_group gp_in1
report_checks -path_delay max -path_group gp_out1
report_checks -path_delay max -path_group gp_thru
############################################################
# Test 5: From/to with instances
############################################################
puts "--- from instance ---"
set_false_path -from [get_cells reg1] -to [get_ports out2]
report_checks -path_delay max
@ -110,18 +100,14 @@ report_checks -path_delay max
unset_path_exceptions -from [get_ports in1] -to [get_cells reg2]
############################################################
# Test 6: From/to with clock objects
############################################################
puts "--- from clock ---"
set_false_path -from [get_clocks clk1] -to [get_ports out2]
report_checks -path_delay max
unset_path_exceptions -from [get_clocks clk1] -to [get_ports out2]
############################################################
# Test 7: Rise/fall through
############################################################
puts "--- rise_through ---"
set_false_path -rise_through [get_pins buf1/Z] -to [get_ports out1]
report_checks -path_delay max
@ -134,17 +120,10 @@ report_checks -path_delay max
unset_path_exceptions -through [get_pins inv1/ZN] -to [get_ports out1]
############################################################
# Test 8: Write SDC roundtrip with complex exceptions
############################################################
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
set_multicycle_path 3 -setup -from [get_clocks clk1] -to [get_clocks clk2]
set sdc_out [make_result_file sdc_exc_match_filter.sdc]
write_sdc -no_timestamp $sdc_out
read_sdc $sdc_out
set sdc_out2 [make_result_file sdc_exc_match_filter2.sdc]
write_sdc -no_timestamp $sdc_out2

82
sdc/test/sdc_exception_merge_priority.ok
View File

@ -1179,85 +1179,3 @@ Path Type: max
--- write_sdc with exceptions ---
--- write_sdc compatible with exceptions ---
--- read_sdc back ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: grp1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
20.00 20.00 clock clk1 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: grp3
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.07 ^ nor1/ZN (NOR2_X1)
0.00 2.07 ^ reg2/D (DFF_X1)
2.07 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg2/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-2.07 data arrival time
---------------------------------------------------------
7.89 slack (MET)

31
sdc/test/sdc_exception_merge_priority.tcl
View File

@ -21,16 +21,12 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Simple false path
############################################################
puts "--- false path clock to clock ---"
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
report_checks
############################################################
# False path with rise_from/fall_to
############################################################
puts "--- false path rise_from/fall_to ---"
set_false_path -rise_from [get_ports in1] -fall_to [get_ports out1]
report_checks
@ -39,9 +35,7 @@ puts "--- false path fall_from/rise_to ---"
set_false_path -fall_from [get_ports in2] -rise_to [get_ports out2]
report_checks
############################################################
# False path with -through
############################################################
puts "--- false path through single pin ---"
set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
report_checks
@ -54,9 +48,7 @@ puts "--- false path through second pin ---"
set_false_path -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out2]
report_checks
############################################################
# Multicycle paths with various options
############################################################
puts "--- multicycle setup ---"
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
report_checks
@ -81,9 +73,7 @@ puts "--- multicycle with fall_to ---"
set_multicycle_path -hold 2 -fall_to [get_ports out1]
report_checks
############################################################
# Max/min delay constraints
############################################################
puts "--- max_delay ---"
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
report_checks -path_delay max
@ -104,9 +94,7 @@ puts "--- max_delay rise_from ---"
set_max_delay -rise_from [get_ports in3] -to [get_ports out2] 7.0
report_checks -path_delay max
############################################################
# Group paths
############################################################
puts "--- group_path ---"
group_path -name grp1 -from [get_clocks clk1]
group_path -name grp2 -from [get_ports in1] -to [get_ports out1]
@ -121,17 +109,13 @@ puts "--- is_path_group_name ---"
puts "grp1 is group: [sta::is_path_group_name grp1]"
puts "nonexistent is group: [sta::is_path_group_name nonexistent]"
############################################################
# Exception priority and overriding
############################################################
puts "--- exception override: false path then max_delay ---"
# More specific exception should override broader one
set_max_delay -from [get_ports in3] -to [get_ports out2] 5.0
report_checks
############################################################
# remove_constraints (remove all SDC constraints)
############################################################
puts "--- remove_constraints ---"
# TODO: sta::remove_constraints removed from Sta API
# sta::remove_constraints
@ -153,9 +137,7 @@ set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
group_path -name grp1 -from [get_clocks clk1]
report_checks
############################################################
# Write SDC with all exception types
############################################################
puts "--- write_sdc with exceptions ---"
set sdc1 [make_result_file sdc_exception_merge1.sdc]
write_sdc -no_timestamp $sdc1
@ -163,16 +145,3 @@ write_sdc -no_timestamp $sdc1
puts "--- write_sdc compatible with exceptions ---"
set sdc2 [make_result_file sdc_exception_merge2.sdc]
write_sdc -no_timestamp -compatible $sdc2
############################################################
# Read back and verify
############################################################
puts "--- read_sdc back ---"
read_sdc $sdc1
report_checks
############################################################
# Additional write after re-read
############################################################
set sdc3 [make_result_file sdc_exception_merge3.sdc]
write_sdc -no_timestamp $sdc3

1
sdc/test/sdc_exception_override_priority.ok
View File

@ -2,4 +2,3 @@ No differences found.
No differences found.
No differences found.
No differences found.
No differences found.

25
sdc/test/sdc_exception_override_priority.tcl
View File

@ -33,10 +33,8 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Test 1: Override max_delay with false_path
# (FalsePath::overrides, PathDelay::overrides)
############################################################
# Set max_delay first
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
@ -50,10 +48,8 @@ set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
# Override min_delay with another min_delay (same endpoints)
set_min_delay -from [get_ports in2] -to [get_ports out1] 2.0
############################################################
# Test 2: Multicycle path overrides
# (MultiCyclePath::overrides, MultiCyclePath::mergeable)
############################################################
# Setup multicycle
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out2]
@ -73,10 +69,8 @@ set_multicycle_path -setup -start 4 -from [get_ports in2] -to [get_ports out2]
# Multicycle with -end (exercises use_end_clk=true)
set_multicycle_path -hold -end 2 -from [get_ports in2] -to [get_ports out2]
############################################################
# Test 3: Exception with rise/fall transitions on to/from
# (ExceptionTo::matchesFilter with endTransition)
############################################################
# False path with rise_from only
set_false_path -rise_from [get_ports in3] -to [get_ports out1]
@ -95,10 +89,8 @@ set_multicycle_path -setup 2 -rise_from [get_clocks clk1] -to [get_clocks clk2]
set_multicycle_path -setup 3 -from [get_clocks clk1] -fall_to [get_clocks clk2]
############################################################
# Test 4: Group path overrides
# (GroupPath::overrides, GroupPath::mergeable)
############################################################
# Named group path
group_path -name grp_a -from [get_ports in1] -to [get_ports out1]
@ -130,10 +122,8 @@ group_path -name grp_inst \
-through [get_cells and1] \
-to [get_ports out2]
############################################################
# Test 5: Complex through combinations
# (ExceptionThru with pins + nets + instances)
############################################################
# Multiple through points: pin then net then pin
set_false_path -from [get_ports in1] \
@ -158,16 +148,12 @@ set_max_delay -from [get_ports in1] \
-through [get_nets n1] \
-to [get_ports out1] 6.0
############################################################
# Test 6: False path with -setup and -hold only
############################################################
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
############################################################
# Write SDC with all exception types
############################################################
set sdc1 [make_result_file sdc_exc_override1.sdc]
write_sdc -no_timestamp $sdc1
diff_files sdc_exc_override1.sdcok $sdc1
@ -180,9 +166,7 @@ set sdc3 [make_result_file sdc_exc_override3.sdc]
write_sdc -no_timestamp -digits 6 $sdc3
diff_files sdc_exc_override3.sdcok $sdc3
############################################################
# Unset some exceptions and verify
############################################################
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -from [get_ports in2] -rise_to [get_ports out1]
@ -192,12 +176,3 @@ unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out2]
set sdc_unset [make_result_file sdc_exc_override_unset.sdc]
write_sdc -no_timestamp $sdc_unset
diff_files sdc_exc_override_unset.sdcok $sdc_unset
############################################################
# Read back and verify roundtrip
############################################################
read_sdc $sdc1
set sdc4 [make_result_file sdc_exc_override4.sdc]
write_sdc -no_timestamp $sdc4
diff_files sdc_exc_override4.sdcok $sdc4

53
sdc/test/sdc_exception_rise_fall_transitions.ok
View File

@ -196,56 +196,3 @@ Path Type: max
7.89 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

30
sdc/test/sdc_exception_rise_fall_transitions.tcl
View File

@ -22,30 +22,22 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Test 1: false_path with -rise_from / -fall_from
############################################################
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
set_false_path -fall_from [get_ports in2] -to [get_ports out1]
############################################################
# Test 2: false_path with -rise_to / -fall_to
############################################################
set_false_path -from [get_ports in1] -rise_to [get_ports out2]
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
############################################################
# Test 3: false_path with -rise_through / -fall_through
############################################################
set_false_path -rise_through [get_pins buf1/Z] -to [get_ports out1]
set_false_path -fall_through [get_pins inv1/ZN] -to [get_ports out2]
############################################################
# Test 4: Combination of rise/fall from + through + to
############################################################
set_false_path -rise_from [get_ports in3] \
-through [get_pins or1/ZN] \
-fall_to [get_ports out2]
@ -54,9 +46,7 @@ set_false_path -fall_from [get_ports in3] \
-rise_through [get_pins or1/ZN] \
-to [get_ports out1]
############################################################
# Test 5: multicycle_path with rise/fall
############################################################
set_multicycle_path -setup 2 -rise_from [get_ports in1] -to [get_ports out1]
set_multicycle_path -hold 1 -fall_from [get_ports in1] -to [get_ports out1]
@ -65,9 +55,7 @@ set_multicycle_path -setup 3 -from [get_ports in2] -rise_to [get_ports out1]
set_multicycle_path -hold 2 -from [get_ports in2] -fall_to [get_ports out1]
############################################################
# Test 6: max_delay with rise/fall
############################################################
set_max_delay -rise_from [get_ports in1] -to [get_ports out2] 7.0
set_max_delay -from [get_ports in3] -fall_to [get_ports out1] 8.0
@ -76,18 +64,14 @@ set_min_delay -fall_from [get_ports in2] -to [get_ports out2] 0.5
set_min_delay -from [get_ports in3] -rise_to [get_ports out2] 0.3
############################################################
# Test 7: Write SDC and verify rise/fall transitions preserved
############################################################
set sdc1 [make_result_file sdc_exc_risefall1.sdc]
write_sdc -no_timestamp $sdc1
set sdc2 [make_result_file sdc_exc_risefall2.sdc]
write_sdc -no_timestamp -compatible $sdc2
############################################################
# Test 8: report_checks to validate exceptions applied
############################################################
report_checks -path_delay max
report_checks -path_delay min
@ -98,9 +82,7 @@ report_checks -path_delay max -from [get_ports in2]
report_checks -path_delay max -from [get_ports in3]
############################################################
# Test 9: Unset rise/fall exceptions
############################################################
unset_path_exceptions -rise_from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -fall_from [get_ports in2] -to [get_ports out1]
@ -109,18 +91,6 @@ unset_path_exceptions -from [get_ports in1] -rise_to [get_ports out2]
unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out2]
############################################################
# Test 10: Write after unset
############################################################
set sdc3 [make_result_file sdc_exc_risefall3.sdc]
write_sdc -no_timestamp $sdc3
############################################################
# Test 11: Read back SDC
############################################################
read_sdc $sdc1
report_checks -path_delay max
set sdc4 [make_result_file sdc_exc_risefall4.sdc]
write_sdc -no_timestamp $sdc4

1
sdc/test/sdc_exception_thru_complex.ok
View File

@ -2,4 +2,3 @@ No differences found.
No differences found.
No differences found.
No differences found.
No differences found.

27
sdc/test/sdc_exception_thru_complex.tcl
View File

@ -33,9 +33,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Test 1: Through nets (exercises ExceptionThru with nets)
############################################################
set_false_path -through [get_nets n1] -to [get_ports out1]
set_false_path -through [get_nets n2] -to [get_ports out2]
@ -48,9 +46,7 @@ set_false_path -rise_through [get_nets n4] -to [get_ports out2]
# Through net with fall_through
set_false_path -fall_through [get_nets n5] -to [get_ports out1]
############################################################
# Test 2: Through instances (exercises ExceptionThru with instances)
############################################################
set_false_path -through [get_cells buf1] -to [get_ports out2]
set_false_path -from [get_ports in2] -through [get_cells and1] -to [get_ports out1]
@ -58,10 +54,8 @@ set_false_path -from [get_ports in2] -through [get_cells and1] -to [get_ports ou
# Rise through instance
set_false_path -from [get_ports in3] -rise_through [get_cells or1] -to [get_ports out2]
############################################################
# Test 3: Multiple through points with mixed types
# (net then pin, instance then pin, pin then net)
############################################################
# Net then pin
set_false_path -from [get_ports in1] \
@ -88,9 +82,7 @@ set_false_path -from [get_ports in2] \
-through [get_cells nand1] \
-to [get_ports out1]
############################################################
# Test 4: From with mixed objects (pins + clocks)
############################################################
set_false_path -from [list [get_ports in1] [get_ports in2]] \
-to [list [get_ports out1] [get_ports out2]]
@ -103,9 +95,7 @@ set_false_path -from [get_cells reg1] -to [get_ports out2]
# To with instances
set_false_path -from [get_ports in1] -to [get_cells reg2]
############################################################
# Test 5: Max/min delay with through
############################################################
set_max_delay -from [get_ports in1] -through [get_nets n1] -to [get_ports out1] 7.0
set_max_delay -from [get_ports in2] -through [get_cells and1] -to [get_ports out1] 6.5
@ -119,9 +109,7 @@ set_min_delay -from [get_ports in1] -through [get_nets n1] -to [get_ports out1]
# Max delay with -ignore_clock_latency
set_max_delay -from [get_ports in3] -to [get_ports out2] -ignore_clock_latency 9.0
############################################################
# Test 6: Multicycle with through
############################################################
set_multicycle_path -setup 2 -from [get_ports in1] \
-through [get_pins buf1/Z] \
-to [get_ports out1]
@ -130,9 +118,7 @@ set_multicycle_path -hold 1 -from [get_ports in1] \
-through [get_pins buf1/Z] \
-to [get_ports out1]
############################################################
# Test 7: Group path with through nets/instances
############################################################
group_path -name gp_net -from [get_ports in1] \
-through [get_nets n1] \
-to [get_ports out1]
@ -147,9 +133,7 @@ group_path -name gp_pin -from [get_ports in3] \
group_path -default -from [get_ports in1] -to [get_ports out2]
############################################################
# Write SDC
############################################################
set sdc1 [make_result_file sdc_exc_thru_complex1.sdc]
write_sdc -no_timestamp $sdc1
diff_files sdc_exc_thru_complex1.sdcok $sdc1
@ -162,9 +146,7 @@ set sdc3 [make_result_file sdc_exc_thru_complex3.sdc]
write_sdc -no_timestamp -digits 6 $sdc3
diff_files sdc_exc_thru_complex3.sdcok $sdc3
############################################################
# Unset and verify
############################################################
unset_path_exceptions -through [get_nets n1] -to [get_ports out1]
unset_path_exceptions -through [get_nets n2] -to [get_ports out2]
unset_path_exceptions -from [get_ports in1] -through [get_nets n3] -to [get_ports out1]
@ -176,12 +158,3 @@ unset_path_exceptions -from [get_ports in2] -through [get_cells and1] -to [get_p
set sdc_unset [make_result_file sdc_exc_thru_complex_unset.sdc]
write_sdc -no_timestamp $sdc_unset
diff_files sdc_exc_thru_complex_unset.sdcok $sdc_unset
############################################################
# Read back SDC and verify roundtrip
############################################################
read_sdc $sdc1
set sdc4 [make_result_file sdc_exc_thru_complex4.sdc]
write_sdc -no_timestamp $sdc4
diff_files sdc_exc_thru_complex4.sdcok $sdc4

26
sdc/test/sdc_exception_thru_override.tcl
View File

@ -28,9 +28,7 @@ set_output_delay -clock clk2 3.0 [get_ports out2]
report_checks > /dev/null
############################################################
# Test 1: Rise/fall from exceptions
############################################################
puts "--- set_false_path -rise_from ---"
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
report_checks -path_delay max -from [get_ports in1]
@ -43,9 +41,7 @@ puts "--- unset rise/fall from ---"
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -from [get_ports in2] -to [get_ports out1]
############################################################
# Test 2: Rise/fall to exceptions
############################################################
puts "--- set_false_path -rise_to ---"
set_false_path -from [get_ports in1] -rise_to [get_ports out1]
report_checks -path_delay max -to [get_ports out1]
@ -58,9 +54,7 @@ puts "--- unset rise/fall to ---"
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -from [get_ports in2] -to [get_ports out1]
############################################################
# Test 3: Rise/fall through exceptions
############################################################
puts "--- set_false_path -rise_through ---"
set_false_path -rise_through [get_pins buf1/Z] -to [get_ports out1]
report_checks -path_delay max
@ -73,9 +67,7 @@ puts "--- unset rise/fall through ---"
unset_path_exceptions -through [get_pins buf1/Z] -to [get_ports out1]
unset_path_exceptions -through [get_pins inv1/ZN] -to [get_ports out1]
############################################################
# Test 4: Exception priority ordering (more specific overrides less specific)
############################################################
puts "--- priority: broad false_path ---"
set_false_path -from [get_ports in1]
report_checks -path_delay max -from [get_ports in1]
@ -93,9 +85,7 @@ unset_path_exceptions -from [get_ports in1]
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -from [get_ports in1] -through [get_pins buf1/Z] -to [get_ports out1]
############################################################
# Test 5: Clock-based from/to exceptions
############################################################
puts "--- false_path from clock ---"
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
report_checks -path_delay max
@ -111,9 +101,7 @@ report_checks -path_delay max
puts "--- unset rise_from clock ---"
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
############################################################
# Test 6: Multiple overlapping exceptions (merge testing)
############################################################
puts "--- overlapping exceptions ---"
set_false_path -from [get_ports in1] -to [get_ports out1]
set_false_path -from [get_ports in1] -to [get_ports out2]
@ -126,9 +114,7 @@ unset_path_exceptions -from [get_ports in1] -to [get_ports out2]
unset_path_exceptions -from [get_ports in2] -to [get_ports out1]
report_checks -path_delay max
############################################################
# Test 7: Multicycle with -start/-end and rise/fall
############################################################
puts "--- mcp -start -rise_from ---"
set_multicycle_path 2 -setup -start -rise_from [get_clocks clk1] -to [get_clocks clk2]
report_checks -path_delay max
@ -140,9 +126,7 @@ report_checks -path_delay max
puts "--- unset mcp ---"
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
############################################################
# Test 8: Max/min delay with rise/fall from/to
############################################################
puts "--- max_delay -rise_from -to ---"
set_max_delay 6.0 -rise_from [get_ports in1] -to [get_ports out1]
report_checks -path_delay max
@ -154,9 +138,7 @@ report_checks -path_delay min
puts "--- unset max/min delays ---"
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
############################################################
# Test 9: write_sdc with exception paths
############################################################
set_false_path -rise_from [get_ports in1] -to [get_ports out1]
set_false_path -from [get_ports in2] -fall_to [get_ports out2]
set_multicycle_path 2 -setup -from [get_clocks clk1] -to [get_clocks clk2]
@ -167,11 +149,3 @@ write_sdc -no_timestamp $sdc1
set sdc2 [make_result_file sdc_exc_override2.sdc]
write_sdc -no_timestamp -compatible $sdc2
############################################################
# Test 10: Read back SDC
############################################################
read_sdc $sdc1
set sdc3 [make_result_file sdc_exc_override3.sdc]
write_sdc -no_timestamp $sdc3

108
sdc/test/sdc_net_wire_voltage.ok
View File

@ -540,111 +540,3 @@ Path Type: max
--- write_sdc native ---
--- write_sdc compatible ---
--- write_sdc digits 8 ---
--- read_sdc back ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.09 0.09 ^ reg2/Q (DFF_X1)
0.00 0.09 ^ out1 (out)
0.09 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.09 data arrival time
---------------------------------------------------------
6.91 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
--- reset deratings ---
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)

46
sdc/test/sdc_net_wire_voltage.tcl
View File

@ -20,9 +20,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Net wire capacitance
############################################################
puts "--- set net wire cap ---"
set_load 0.01 [get_nets n1]
set_load 0.02 [get_nets n2]
@ -31,9 +29,7 @@ set_load 0.015 [get_nets n4]
set_load 0.03 [get_nets n5]
report_checks
############################################################
# Port loads (pin_load and wire_load)
############################################################
puts "--- port loads ---"
set_load -pin_load 0.04 [get_ports out1]
set_load -wire_load 0.02 [get_ports out1]
@ -41,17 +37,13 @@ set_load -pin_load 0.03 [get_ports out2]
set_load -wire_load 0.01 [get_ports out2]
report_checks
############################################################
# Port fanout
############################################################
puts "--- port fanout ---"
set_port_fanout_number 4 [get_ports out1]
set_port_fanout_number 6 [get_ports out2]
report_checks
############################################################
# Net resistance
############################################################
puts "--- net resistance ---"
set_resistance -min 10.0 [get_nets n1]
set_resistance -max 20.0 [get_nets n1]
@ -60,9 +52,7 @@ set_resistance -max 15.0 [get_nets n2]
set_resistance 12.0 [get_nets n3]
report_checks
############################################################
# Voltage settings
############################################################
puts "--- voltage ---"
set_voltage 1.1 -min 0.9
report_checks
@ -70,9 +60,7 @@ report_checks
set_voltage 1.2 -min 1.0 -object_list [get_nets n1]
report_checks
############################################################
# Timing deratings: global
############################################################
puts "--- timing derate global ---"
set_timing_derate -early 0.95
set_timing_derate -late 1.05
@ -80,9 +68,7 @@ set_timing_derate -early -clock 0.97
set_timing_derate -late -clock 1.03
report_checks
############################################################
# Timing deratings: on lib cells
############################################################
puts "--- timing derate lib cell ---"
set_timing_derate -early -cell_delay 0.91 [get_lib_cells NangateOpenCellLibrary/INV_X1]
set_timing_derate -late -cell_delay 1.09 [get_lib_cells NangateOpenCellLibrary/INV_X1]
@ -90,9 +76,7 @@ set_timing_derate -early -cell_delay 0.92 [get_lib_cells NangateOpenCellLibrary/
set_timing_derate -late -cell_delay 1.08 [get_lib_cells NangateOpenCellLibrary/BUF_X1]
report_checks
############################################################
# Timing deratings: on instances
############################################################
puts "--- timing derate instance ---"
set_timing_derate -early -cell_delay 0.90 [get_cells buf1]
set_timing_derate -late -cell_delay 1.10 [get_cells buf1]
@ -100,9 +84,7 @@ set_timing_derate -early -cell_delay 0.93 [get_cells inv1]
set_timing_derate -late -cell_delay 1.07 [get_cells inv1]
report_checks
############################################################
# Timing deratings: on nets
############################################################
puts "--- timing derate net ---"
set_timing_derate -early -net_delay 0.88 [get_nets n1]
set_timing_derate -late -net_delay 1.12 [get_nets n1]
@ -110,9 +92,7 @@ set_timing_derate -early -net_delay 0.89 [get_nets n3]
set_timing_derate -late -net_delay 1.11 [get_nets n3]
report_checks
############################################################
# Write SDC and verify all sections are written
############################################################
puts "--- write_sdc native ---"
set sdc1 [make_result_file sdc_net_wire_voltage1.sdc]
write_sdc -no_timestamp $sdc1
@ -124,29 +104,3 @@ write_sdc -no_timestamp -compatible $sdc2
puts "--- write_sdc digits 8 ---"
set sdc3 [make_result_file sdc_net_wire_voltage3.sdc]
write_sdc -no_timestamp -digits 8 $sdc3
############################################################
# Read back and verify constraints survive roundtrip
############################################################
puts "--- read_sdc back ---"
read_sdc $sdc1
report_checks
############################################################
# Write after re-read
############################################################
set sdc4 [make_result_file sdc_net_wire_voltage4.sdc]
write_sdc -no_timestamp $sdc4
############################################################
# Reset deratings
############################################################
puts "--- reset deratings ---"
unset_timing_derate
report_checks
############################################################
# Final write with cleared deratings
############################################################
set sdc5 [make_result_file sdc_net_wire_voltage5.sdc]
write_sdc -no_timestamp $sdc5

53
sdc/test/sdc_removal_reset.ok
View File

@ -211,56 +211,3 @@ Path Type: max
16.39 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.40 0.40 clock network delay (ideal)
0.00 0.40 ^ reg2/CK (DFF_X1)
0.10 0.50 ^ reg2/Q (DFF_X1)
0.00 0.50 ^ out1 (out)
0.50 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.40 10.40 clock network delay (ideal)
-0.25 10.15 clock uncertainty
0.00 10.15 clock reconvergence pessimism
-3.00 7.15 output external delay
7.15 data required time
---------------------------------------------------------
7.15 data required time
-0.50 data arrival time
---------------------------------------------------------
6.65 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.15 0.15 clock network delay (ideal)
0.00 0.15 ^ reg3/CK (DFF_X1)
0.11 0.26 ^ reg3/Q (DFF_X1)
0.00 0.26 ^ out2 (out)
0.26 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.15 20.15 clock network delay (ideal)
0.00 20.15 clock reconvergence pessimism
-3.50 16.65 output external delay
16.65 data required time
---------------------------------------------------------
16.65 data required time
-0.26 data arrival time
---------------------------------------------------------
16.39 slack (MET)

19
sdc/test/sdc_removal_reset.tcl
View File

@ -14,9 +14,7 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdc_test2.v
link_design sdc_test2
############################################################
# Phase 1: Create comprehensive constraints
############################################################
# Clocks
create_clock -name clk1 -period 10 [get_ports clk1]
@ -97,9 +95,7 @@ write_sdc -no_timestamp $sdc_phase1
report_checks
############################################################
# Phase 2: Remove constraints systematically
############################################################
# Remove exceptions
unset_path_exceptions -from [get_clocks clk1] -to [get_clocks clk2]
@ -138,11 +134,9 @@ write_sdc -no_timestamp $sdc_phase2
report_checks
############################################################
# Phase 3: Delete and re-create clocks
# (this is the key test - deleting clocks should remove
# all referencing constraints)
############################################################
# Delete generated clocks first
delete_generated_clock [get_clocks gclk1]
@ -160,9 +154,7 @@ write_sdc -no_timestamp $sdc_phase3a
report_checks
############################################################
# Phase 4: Re-create everything fresh
############################################################
# Re-create virtual clock with different period
create_clock -name vclk_new -period 12
@ -202,14 +194,3 @@ set sdc_phase4_compat [make_result_file sdc_removal_phase4_compat.sdc]
write_sdc -no_timestamp -compatible $sdc_phase4_compat
report_checks
############################################################
# Phase 5: Read back SDC and verify
############################################################
read_sdc $sdc_phase4
report_checks
set sdc_phase5 [make_result_file sdc_removal_phase5.sdc]
write_sdc -no_timestamp $sdc_phase5

83
sdc/test/sdc_sense_unset_override.ok
View File

@ -194,86 +194,3 @@ Path Type: max
16.62 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: grp_multi
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.07 ^ nor1/ZN (NOR2_X1)
0.00 2.07 ^ reg2/D (DFF_X1)
2.07 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
-0.32 9.68 inter-clock uncertainty
0.00 9.68 clock reconvergence pessimism
9.68 ^ reg2/CK (DFF_X1)
-0.03 9.65 library setup time
9.65 data required time
---------------------------------------------------------
9.65 data required time
-2.07 data arrival time
---------------------------------------------------------
7.57 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
-0.30 19.70 clock uncertainty
0.00 19.70 clock reconvergence pessimism
-3.00 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-0.08 data arrival time
---------------------------------------------------------
16.62 slack (MET)

20
sdc/test/sdc_sense_unset_override.tcl
View File

@ -23,9 +23,7 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdc_test2.v
link_design sdc_test2
############################################################
# Create clocks
############################################################
create_clock -name clk1 -period 10 [get_ports clk1]
create_clock -name clk2 -period 20 [get_ports clk2]
create_clock -name vclk -period 5
@ -35,9 +33,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Clock sense: positive, negative, stop
############################################################
# Positive sense on a pin with specific clock
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
@ -63,9 +59,7 @@ set_clock_sense -negative -clocks [get_clocks clk1] [get_pins buf1/Z]
report_checks
############################################################
# Clock uncertainty: set and unset
############################################################
# Simple uncertainty
set_clock_uncertainty -setup 0.2 [get_clocks clk1]
set_clock_uncertainty -hold 0.1 [get_clocks clk1]
@ -92,9 +86,7 @@ unset_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold
report_checks
############################################################
# Clock insertion (source latency)
############################################################
set_clock_latency -source -early 0.3 [get_clocks clk1]
set_clock_latency -source -late 0.5 [get_clocks clk1]
set_clock_latency -source -rise -early 0.25 [get_clocks clk1]
@ -103,9 +95,7 @@ set_clock_latency -source -fall -late 0.55 [get_clocks clk1]
# Remove clock insertion
unset_clock_latency -source [get_clocks clk1]
############################################################
# Clock groups: all three types
############################################################
# Asynchronous
set_clock_groups -asynchronous -name async1 -group {clk1} -group {clk2}
@ -128,9 +118,7 @@ write_sdc -no_timestamp $sdc3
# Unset
unset_clock_groups -physically_exclusive -name phys1
############################################################
# Exception overrides: same from/to with different types
############################################################
# First set a max_delay
set_max_delay -from [get_ports in1] -to [get_ports out1] 8.0
@ -170,18 +158,10 @@ write_sdc -no_timestamp $sdc4
set sdc5 [make_result_file sdc_sense5.sdc]
write_sdc -no_timestamp -compatible $sdc5
############################################################
# Unset exceptions and re-report
############################################################
unset_path_exceptions -from [get_ports in1] -to [get_ports out1]
unset_path_exceptions -from [get_ports in2] -rise_to [get_ports out1]
unset_path_exceptions -from [get_ports in2] -fall_to [get_ports out1]
report_checks
############################################################
# Read back SDC
############################################################
read_sdc $sdc4
report_checks

79
sdc/test/sdc_write_comprehensive.ok
View File

@ -1,80 +1 @@
Warning 415: sdc_write_comprehensive.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
Warning 1061: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: group_clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.60 0.60 clock network delay (propagated)
0.00 0.60 ^ reg2/CK (DFF_X1)
0.09 0.69 ^ reg2/Q (DFF_X1)
0.00 0.69 ^ out1 (out)
0.69 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.50 10.50 clock network delay (propagated)
-0.20 10.30 clock uncertainty
0.00 10.30 clock reconvergence pessimism
-3.00 7.30 output external delay
7.30 data required time
---------------------------------------------------------
7.30 data required time
-0.69 data arrival time
---------------------------------------------------------
6.61 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1_fast)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock clk1_fast (rise edge)
0.00 5.00 clock network delay (ideal)
0.00 5.00 ^ reg2/CK (DFF_X1)
0.09 5.09 ^ reg2/Q (DFF_X1)
0.00 5.09 ^ out1 (out)
5.09 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.50 10.50 clock network delay (propagated)
-0.20 10.30 clock uncertainty
0.00 10.30 clock reconvergence pessimism
-3.00 7.30 output external delay
7.30 data required time
---------------------------------------------------------
7.30 data required time
-5.09 data arrival time
---------------------------------------------------------
2.21 slack (MET)
Startpoint: reg3/Q (clock source 'gen_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
13.33 13.33 clock gen_mul3 (rise edge)
0.00 13.33 clock network delay
13.33 ^ out2 (out)
13.33 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.20 20.20 clock network delay (ideal)
0.00 20.20 clock reconvergence pessimism
-3.50 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-13.33 data arrival time
---------------------------------------------------------
3.37 slack (MET)

45
sdc/test/sdc_write_comprehensive.tcl
View File

@ -6,9 +6,7 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdc_test2.v
link_design sdc_test2
############################################################
# Create multiple clocks with various options
############################################################
# Basic clocks
create_clock -name clk1 -period 10 [get_ports clk1]
@ -23,9 +21,7 @@ create_generated_clock -name gen_mul3 -source [get_ports clk2] -multiply_by 3 [g
# Propagated clock
set_propagated_clock [get_clocks clk1]
############################################################
# Clock constraints
############################################################
# Clock latency (source and network)
set_clock_latency -source 0.5 [get_clocks clk1]
@ -46,9 +42,7 @@ set_clock_transition -rise -max 0.15 [get_clocks clk1]
set_clock_transition -fall -min 0.08 [get_clocks clk1]
set_clock_transition 0.1 [get_clocks clk2]
############################################################
# IO constraints
############################################################
# Input delays with various options
set_input_delay -clock clk1 2.0 [get_ports in1]
@ -62,9 +56,7 @@ set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
set_output_delay -clock clk2 -fall -min 1.5 [get_ports out2] -add_delay
############################################################
# Driving cell and load
############################################################
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
@ -81,9 +73,7 @@ set_input_transition 0.15 [get_ports in1]
set_input_transition -rise -max 0.12 [get_ports in2]
set_input_transition -fall -min 0.08 [get_ports in2]
############################################################
# Design limits
############################################################
set_max_transition 0.5 [current_design]
set_max_capacitance 0.2 [current_design]
@ -93,9 +83,7 @@ set_max_capacitance 0.1 [get_ports out1]
set_max_transition -clock_path 0.2 [get_clocks clk1]
set_max_transition -data_path 0.4 [get_clocks clk1]
############################################################
# Exception paths
############################################################
# False path
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
@ -114,91 +102,58 @@ set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
group_path -name group_clk1 -from [get_clocks clk1]
group_path -name group_io -from [get_ports in1] -to [get_ports out1]
############################################################
# Clock groups
############################################################
set_clock_groups -asynchronous -group {clk1 clk1_fast} -group {clk2}
############################################################
# Clock sense
############################################################
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
############################################################
# Case analysis and logic values
############################################################
set_case_analysis 0 [get_ports in3]
############################################################
# Operating conditions
############################################################
set_operating_conditions typical
############################################################
# Wire load
############################################################
set_wire_load_model -name "5K_hvratio_1_1"
set_wire_load_mode enclosed
############################################################
# Timing derate
############################################################
set_timing_derate -early 0.95
set_timing_derate -late 1.05
############################################################
# Disable timing
############################################################
set_disable_timing [get_cells buf1]
set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
############################################################
# Min pulse width
############################################################
set_min_pulse_width 1.0 [get_clocks clk1]
############################################################
# Port external pin cap
############################################################
set_port_fanout_number 4 [get_ports out1]
############################################################
# Resistance
############################################################
set_resistance -min 10.0 [get_nets n1]
set_resistance -max 20.0 [get_nets n1]
############################################################
# set_max_area
############################################################
set_max_area 100.0
############################################################
# Write SDC with various options
############################################################
set sdc_file1 [make_result_file sdc_write_comprehensive1.sdc]
write_sdc -no_timestamp $sdc_file1
set sdc_file2 [make_result_file sdc_write_comprehensive2.sdc]
write_sdc -no_timestamp -digits 6 $sdc_file2
############################################################
# Read back SDC
############################################################
# Read the SDC file (re-applying constraints)
read_sdc $sdc_file1
report_checks

82
sdc/test/sdc_write_disabled_groups.ok
View File

@ -82,85 +82,3 @@ Path Type: max
16.92 slack (MET)
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: grp_reg
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.50 0.50 clock network delay (propagated)
0.00 0.50 ^ reg2/CK (DFF_X1)
0.08 0.58 ^ reg2/Q (DFF_X1)
0.00 0.58 ^ out1 (out)
0.58 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.30 10.30 clock network delay (propagated)
0.00 10.30 clock reconvergence pessimism
-3.00 7.30 output external delay
7.30 data required time
---------------------------------------------------------
7.30 data required time
-0.58 data arrival time
---------------------------------------------------------
6.72 slack (MET)
Startpoint: in3 (input port clocked by clk2)
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 v input external delay
0.00 2.00 v in3 (in)
0.05 2.05 v or1/ZN (OR2_X1)
0.03 2.08 ^ nor1/ZN (NOR2_X1)
0.00 2.08 ^ reg2/D (DFF_X1)
2.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.30 10.30 clock network delay (propagated)
-0.28 10.02 inter-clock uncertainty
0.00 10.02 clock reconvergence pessimism
10.02 ^ reg2/CK (DFF_X1)
-0.03 9.99 library setup time
9.99 data required time
---------------------------------------------------------
9.99 data required time
-2.08 data arrival time
---------------------------------------------------------
7.91 slack (MET)
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk2 (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ reg3/CK (DFF_X1)
0.08 0.08 ^ reg3/Q (DFF_X1)
0.00 0.08 ^ out2 (out)
0.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
-3.00 17.00 output external delay
17.00 data required time
---------------------------------------------------------
17.00 data required time
-0.08 data arrival time
---------------------------------------------------------
16.92 slack (MET)

34
sdc/test/sdc_write_disabled_groups.tcl
View File

@ -29,9 +29,7 @@ set_input_delay -clock clk2 2.0 [get_ports in3]
set_output_delay -clock clk1 3.0 [get_ports out1]
set_output_delay -clock clk2 3.0 [get_ports out2]
############################################################
# Disable timing on ports (exercises writeDisabledPorts)
############################################################
set_disable_timing [get_ports in1]
set_disable_timing [get_ports in2]
@ -62,9 +60,7 @@ unset_disable_timing [get_lib_cells NangateOpenCellLibrary/AND2_X1] -from A1 -to
unset_disable_timing [get_lib_cells NangateOpenCellLibrary/OR2_X1]
unset_disable_timing [get_pins nand1/A1]
############################################################
# Clock groups - all three types (exercises writeClockGroups)
############################################################
set_clock_groups -asynchronous -name async1 -group {clk1} -group {clk2}
set sdc2 [make_result_file sdc_wdg2.sdc]
@ -86,9 +82,7 @@ write_sdc -no_timestamp $sdc4
unset_clock_groups -physically_exclusive -name phys1
############################################################
# Group paths - named and default (exercises writeGroupPath)
############################################################
group_path -name grp_reg -from [get_clocks clk1] -to [get_clocks clk1]
group_path -name grp_cross -from [get_clocks clk1] -to [get_clocks clk2]
group_path -default -from [get_ports in1] -to [get_ports out1]
@ -103,9 +97,7 @@ group_path -name grp_thru -from [get_ports in1] \
-through [get_pins and1/ZN] \
-to [get_ports out1]
############################################################
# Output drives (exercises writeOutputDrives/writeDriveResistances)
############################################################
set_driving_cell -lib_cell BUF_X1 [get_ports in1]
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
set_driving_cell -lib_cell BUF_X4 [get_ports in3]
@ -119,19 +111,15 @@ set_input_transition 0.15 [get_ports in1]
set_input_transition -rise -max 0.12 [get_ports in2]
set_input_transition -fall -min 0.08 [get_ports in2]
############################################################
# Inter-clock uncertainty with all combinations
# (exercises writeInterClockUncertainty)
############################################################
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
############################################################
# Min pulse width on multiple target types
# (exercises writeMinPulseWidths)
############################################################
set_min_pulse_width 0.5
set_min_pulse_width -high 0.6 [get_clocks clk1]
@ -143,24 +131,18 @@ set_min_pulse_width 0.3 [get_pins reg1/CK]
set_min_pulse_width 0.45 [get_cells reg3]
############################################################
# Port loads (exercises writePortLoads/writePortExtCap)
############################################################
set_load -pin_load 0.05 [get_ports out1]
set_load -wire_load 0.02 [get_ports out1]
set_load -pin_load -rise 0.04 [get_ports out2]
set_load -pin_load -fall 0.045 [get_ports out2]
set_port_fanout_number 4 [get_ports out1]
############################################################
# Clock sense (exercises writeClockSenses)
############################################################
set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
set_clock_sense -negative -clocks [get_clocks clk2] [get_pins or1/ZN]
############################################################
# Propagated clocks (exercises writePropagatedClkPins)
############################################################
set_propagated_clock [get_clocks clk1]
set_propagated_clock [get_ports clk2]
@ -168,23 +150,17 @@ set_propagated_clock [get_ports clk2]
set_clock_latency -source -early 0.3 [get_clocks clk1]
set_clock_latency -source -late 0.5 [get_clocks clk1]
############################################################
# Clock transition
############################################################
set_clock_transition -rise -max 0.15 [get_clocks clk1]
set_clock_transition -fall -min 0.08 [get_clocks clk1]
set_clock_transition 0.1 [get_clocks clk2]
############################################################
# False paths with -setup/-hold only
# (exercises writeFalsePaths branches)
############################################################
set_false_path -setup -from [get_clocks clk1] -to [get_clocks clk2]
set_false_path -hold -from [get_clocks clk2] -to [get_clocks clk1]
############################################################
# Comprehensive write with all constraint types
############################################################
set sdc5 [make_result_file sdc_wdg5.sdc]
write_sdc -no_timestamp $sdc5
@ -198,13 +174,3 @@ set sdc8 [make_result_file sdc_wdg8.sdc]
write_sdc -no_timestamp -map_hpins $sdc8
report_checks
############################################################
# Read back SDC and verify roundtrip
############################################################
read_sdc $sdc5
set sdc9 [make_result_file sdc_wdg9.sdc]
write_sdc -no_timestamp $sdc9
report_checks

102
sdc/test/sdc_write_options.ok
View File

@ -1,103 +1 @@
Warning 415: sdc_write_options.tcl line 1, set_clock_sense is deprecated as of SDC 2.1. Use set_sense -type clock.
Warning 1061: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
Warning 1061: generated clock gen_edges pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2/Q (clock source 'gen_edges')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gen_edges (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.25 10.25 clock network delay (propagated)
-0.20 10.05 clock uncertainty
0.00 10.05 clock reconvergence pessimism
-3.00 7.05 output external delay
7.05 data required time
---------------------------------------------------------
7.05 data required time
-5.00 data arrival time
---------------------------------------------------------
2.05 slack (MET)
Startpoint: reg3/Q (clock source 'gen_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
13.33 13.33 clock gen_mul3 (rise edge)
0.00 13.33 clock network delay
13.33 ^ out2 (out)
13.33 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.20 20.20 clock network delay (ideal)
0.00 20.20 clock reconvergence pessimism
-3.50 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-13.33 data arrival time
---------------------------------------------------------
3.37 slack (MET)
Warning 1061: generated clock gen_div2 pin clk1 is in the fanout of multiple clocks.
Warning 1061: generated clock gen_edges pin clk1 is in the fanout of multiple clocks.
Startpoint: reg2/Q (clock source 'gen_edges')
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
5.00 5.00 clock gen_edges (fall edge)
0.00 5.00 clock network delay
5.00 v out1 (out)
5.00 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.25 10.25 clock network delay (propagated)
-0.20 10.05 clock uncertainty
0.00 10.05 clock reconvergence pessimism
-3.00 7.05 output external delay
7.05 data required time
---------------------------------------------------------
7.05 data required time
-5.00 data arrival time
---------------------------------------------------------
2.05 slack (MET)
Startpoint: reg3/Q (clock source 'gen_mul3')
Endpoint: out2 (output port clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
13.33 13.33 clock gen_mul3 (rise edge)
0.00 13.33 clock network delay
13.33 ^ out2 (out)
13.33 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.20 20.20 clock network delay (ideal)
0.00 20.20 clock reconvergence pessimism
-3.50 16.70 output external delay
16.70 data required time
---------------------------------------------------------
16.70 data required time
-13.33 data arrival time
---------------------------------------------------------
3.37 slack (MET)

18
sdc/test/sdc_write_options.tcl
View File

@ -7,9 +7,7 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
read_verilog sdc_test2.v
link_design sdc_test2
############################################################
# Create comprehensive constraints to maximize write_sdc coverage
############################################################
# Multiple clocks
create_clock -name clk1 -period 10 [get_ports clk1]
@ -151,9 +149,7 @@ set_clock_gating_check -hold 0.3 [get_clocks clk1]
# set_voltage
set_voltage 1.1 -min 0.9
############################################################
# Write SDC with all option combinations
############################################################
# Option 1: basic (native mode, default digits)
set sdc_file1 [make_result_file sdc_write_opt_basic.sdc]
@ -178,17 +174,3 @@ write_sdc -no_timestamp -compatible -digits 6 $sdc_file5
# Option 6: -map_hpins
set sdc_file6 [make_result_file sdc_write_opt_hpins.sdc]
write_sdc -no_timestamp -map_hpins $sdc_file6
############################################################
# Read back and verify
############################################################
# Read back native SDC
read_sdc $sdc_file1
report_checks
# Read back compatible SDC
read_sdc $sdc_file2
report_checks