mirror of
https://github.com/The-OpenROAD-Project/OpenSTA.git
synced 2026-09-03 16:29:50 +02:00
Merge upstream STA update and adapt all tests to new API
Major upstream refactoring: Corner→Scene, Mode architecture, warning format change (Warning ID:), command renames, and many API signature changes. Adapted all C++ test files and TCL test scripts/expected output files to pass with the new API. 6159/6159 tests pass. Co-Authored-By: Claude Opus 4.6 <[email protected]> Signed-off-by: Jaehyun Kim <[email protected]>
This commit is contained in:
Jaehyun Kim
Claude Opus 4.6
+72
-175
@@ -125,12 +125,9 @@ TEST(VertexStandaloneTest, DefaultConstructor)
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EXPECT_FALSE(v.visited());
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EXPECT_FALSE(v.visited2());
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EXPECT_FALSE(v.isRegClk());
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EXPECT_FALSE(v.isDisabledConstraint());
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EXPECT_FALSE(v.hasChecks());
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EXPECT_FALSE(v.isCheckClk());
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EXPECT_FALSE(v.isGatedClkEnable());
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EXPECT_FALSE(v.hasDownstreamClkPin());
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EXPECT_FALSE(v.isConstrained());
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EXPECT_FALSE(v.slewAnnotated());
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}
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@@ -163,15 +160,6 @@ TEST(VertexStandaloneTest, SetVisited2)
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EXPECT_FALSE(v.visited2());
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}
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TEST(VertexStandaloneTest, SetIsDisabledConstraint)
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{
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Vertex v;
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v.setIsDisabledConstraint(true);
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EXPECT_TRUE(v.isDisabledConstraint());
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v.setIsDisabledConstraint(false);
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EXPECT_FALSE(v.isDisabledConstraint());
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}
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TEST(VertexStandaloneTest, SetHasChecks)
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{
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Vertex v;
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@@ -190,15 +178,6 @@ TEST(VertexStandaloneTest, SetIsCheckClk)
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EXPECT_FALSE(v.isCheckClk());
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}
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TEST(VertexStandaloneTest, SetIsGatedClkEnable)
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{
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Vertex v;
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v.setIsGatedClkEnable(true);
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EXPECT_TRUE(v.isGatedClkEnable());
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v.setIsGatedClkEnable(false);
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EXPECT_FALSE(v.isGatedClkEnable());
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}
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TEST(VertexStandaloneTest, SetHasDownstreamClkPin)
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{
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Vertex v;
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@@ -208,31 +187,16 @@ TEST(VertexStandaloneTest, SetHasDownstreamClkPin)
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EXPECT_FALSE(v.hasDownstreamClkPin());
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}
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TEST(VertexStandaloneTest, SetIsConstrained)
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TEST(VertexStandaloneTest, HasSimValue)
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{
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Vertex v;
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v.setIsConstrained(true);
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EXPECT_TRUE(v.isConstrained());
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v.setIsConstrained(false);
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EXPECT_FALSE(v.isConstrained());
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}
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EXPECT_FALSE(v.hasSimValue());
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TEST(VertexStandaloneTest, SimValue)
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{
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Vertex v;
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EXPECT_EQ(v.simValue(), LogicValue::unknown);
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EXPECT_FALSE(v.isConstant());
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v.setHasSimValue(true);
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EXPECT_TRUE(v.hasSimValue());
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v.setSimValue(LogicValue::zero);
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EXPECT_EQ(v.simValue(), LogicValue::zero);
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EXPECT_TRUE(v.isConstant());
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v.setSimValue(LogicValue::one);
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EXPECT_EQ(v.simValue(), LogicValue::one);
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EXPECT_TRUE(v.isConstant());
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v.setSimValue(LogicValue::unknown);
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EXPECT_FALSE(v.isConstant());
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v.setHasSimValue(false);
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EXPECT_FALSE(v.hasSimValue());
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}
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TEST(VertexStandaloneTest, TagGroupIndex)
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@@ -256,10 +220,7 @@ TEST(VertexStandaloneTest, BfsInQueue)
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EXPECT_FALSE(v.bfsInQueue(BfsIndex::dcalc));
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}
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TEST(VertexStandaloneTest, TransitionCount)
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{
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EXPECT_EQ(Vertex::transitionCount(), 2);
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}
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// Vertex::transitionCount() was removed from upstream API
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TEST(VertexStandaloneTest, ObjectIdx)
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{
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@@ -332,7 +293,7 @@ TEST(EdgeStandaloneTest, DefaultConstructor)
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EXPECT_FALSE(e.delay_Annotation_Is_Incremental());
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EXPECT_FALSE(e.isBidirectInstPath());
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EXPECT_FALSE(e.isBidirectNetPath());
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EXPECT_FALSE(e.isDisabledCond());
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EXPECT_FALSE(e.hasDisabledCond());
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EXPECT_FALSE(e.isDisabledLoop());
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}
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@@ -366,10 +327,10 @@ TEST(EdgeStandaloneTest, SetIsBidirectNetPath)
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TEST(EdgeStandaloneTest, SetIsDisabledCond)
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{
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Edge e;
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e.setIsDisabledCond(true);
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EXPECT_TRUE(e.isDisabledCond());
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e.setIsDisabledCond(false);
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EXPECT_FALSE(e.isDisabledCond());
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e.setHasDisabledCond(true);
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EXPECT_TRUE(e.hasDisabledCond());
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e.setHasDisabledCond(false);
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EXPECT_FALSE(e.hasDisabledCond());
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}
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TEST(EdgeStandaloneTest, SetIsDisabledLoop)
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@@ -381,21 +342,6 @@ TEST(EdgeStandaloneTest, SetIsDisabledLoop)
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EXPECT_FALSE(e.isDisabledLoop());
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}
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TEST(EdgeStandaloneTest, SimTimingSense)
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{
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Edge e;
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EXPECT_EQ(e.simTimingSense(), TimingSense::unknown);
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e.setSimTimingSense(TimingSense::positive_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::positive_unate);
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e.setSimTimingSense(TimingSense::negative_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::negative_unate);
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e.setSimTimingSense(TimingSense::non_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::non_unate);
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}
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TEST(EdgeStandaloneTest, ObjectIdx)
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{
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Edge e;
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@@ -403,17 +349,6 @@ TEST(EdgeStandaloneTest, ObjectIdx)
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EXPECT_EQ(e.objectIdx(), 77u);
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}
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TEST(EdgeStandaloneTest, SetIsDisabledConstraint)
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{
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ASSERT_NO_THROW(( [&](){
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Edge e;
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e.setIsDisabledConstraint(true);
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// Can only fully test when arc_set is set; test the setter at least
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e.setIsDisabledConstraint(false);
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}() ));
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}
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TEST(EdgeStandaloneTest, RemoveDelayAnnotated)
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{
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Edge e;
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@@ -534,20 +469,6 @@ TEST(VertexStandaloneTest, SetPaths)
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EXPECT_EQ(v.paths(), nullptr);
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}
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// Test Edge timing sense combinations
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TEST(EdgeStandaloneTest, SimTimingSenseCombinations)
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{
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Edge e;
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e.setSimTimingSense(TimingSense::positive_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::positive_unate);
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e.setSimTimingSense(TimingSense::negative_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::negative_unate);
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e.setSimTimingSense(TimingSense::non_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::non_unate);
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e.setSimTimingSense(TimingSense::unknown);
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EXPECT_EQ(e.simTimingSense(), TimingSense::unknown);
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}
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// Test multiple BFS queue indices
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TEST(VertexStandaloneTest, BfsMultipleQueues)
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{
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@@ -683,39 +604,32 @@ TEST(VertexStandaloneTest, BfsAllIndices)
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EXPECT_FALSE(v.bfsInQueue(BfsIndex::other));
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}
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// Test Vertex SimValue with all LogicValues
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// Covers: Vertex::setSimValue, Vertex::simValue, Vertex::isConstant
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TEST(VertexStandaloneTest, SimValueAllStates)
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// Test Vertex hasSimValue flag
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// Covers: Vertex::setHasSimValue, Vertex::hasSimValue
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TEST(VertexStandaloneTest, HasSimValueToggle)
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{
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Vertex v;
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v.setSimValue(LogicValue::zero);
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EXPECT_EQ(v.simValue(), LogicValue::zero);
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EXPECT_TRUE(v.isConstant());
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EXPECT_FALSE(v.hasSimValue());
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v.setSimValue(LogicValue::one);
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EXPECT_EQ(v.simValue(), LogicValue::one);
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EXPECT_TRUE(v.isConstant());
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v.setHasSimValue(true);
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EXPECT_TRUE(v.hasSimValue());
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v.setSimValue(LogicValue::unknown);
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EXPECT_EQ(v.simValue(), LogicValue::unknown);
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EXPECT_FALSE(v.isConstant());
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v.setHasSimValue(false);
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EXPECT_FALSE(v.hasSimValue());
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}
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// Test Edge simTimingSense all values
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// Covers: Edge::setSimTimingSense, Edge::simTimingSense
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TEST(EdgeStandaloneTest, SimTimingSenseAllValues)
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// Test Edge hasSimSense flag
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// Covers: Edge::setHasSimSense, Edge::hasSimSense
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TEST(EdgeStandaloneTest, HasSimSenseAllValues)
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{
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Edge e;
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e.setSimTimingSense(TimingSense::unknown);
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EXPECT_EQ(e.simTimingSense(), TimingSense::unknown);
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e.setSimTimingSense(TimingSense::positive_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::positive_unate);
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e.setSimTimingSense(TimingSense::negative_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::negative_unate);
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e.setSimTimingSense(TimingSense::non_unate);
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EXPECT_EQ(e.simTimingSense(), TimingSense::non_unate);
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e.setSimTimingSense(TimingSense::unknown);
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EXPECT_EQ(e.simTimingSense(), TimingSense::unknown);
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EXPECT_FALSE(e.hasSimSense());
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e.setHasSimSense(true);
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EXPECT_TRUE(e.hasSimSense());
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e.setHasSimSense(false);
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EXPECT_FALSE(e.hasSimSense());
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}
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// Test Vertex slewAnnotated with all rf/mm combinations
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@@ -798,40 +712,28 @@ TEST(VertexStandaloneTest, MultipleFlagCombinations)
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{
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Vertex v;
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// Set multiple flags and verify they don't interfere
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v.setIsDisabledConstraint(true);
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v.setHasChecks(true);
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v.setIsCheckClk(true);
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v.setIsGatedClkEnable(true);
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v.setHasDownstreamClkPin(true);
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v.setIsConstrained(true);
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v.setVisited(true);
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v.setVisited2(true);
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EXPECT_TRUE(v.isDisabledConstraint());
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EXPECT_TRUE(v.hasChecks());
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EXPECT_TRUE(v.isCheckClk());
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EXPECT_TRUE(v.isGatedClkEnable());
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EXPECT_TRUE(v.hasDownstreamClkPin());
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EXPECT_TRUE(v.isConstrained());
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EXPECT_TRUE(v.visited());
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EXPECT_TRUE(v.visited2());
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// Clear all
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v.setIsDisabledConstraint(false);
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v.setHasChecks(false);
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v.setIsCheckClk(false);
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v.setIsGatedClkEnable(false);
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v.setHasDownstreamClkPin(false);
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v.setIsConstrained(false);
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v.setVisited(false);
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v.setVisited2(false);
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EXPECT_FALSE(v.isDisabledConstraint());
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EXPECT_FALSE(v.hasChecks());
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EXPECT_FALSE(v.isCheckClk());
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EXPECT_FALSE(v.isGatedClkEnable());
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EXPECT_FALSE(v.hasDownstreamClkPin());
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EXPECT_FALSE(v.isConstrained());
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EXPECT_FALSE(v.visited());
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EXPECT_FALSE(v.visited2());
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}
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@@ -843,25 +745,25 @@ TEST(EdgeStandaloneTest, MultipleFlagCombinations)
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Edge e;
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e.setIsBidirectInstPath(true);
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e.setIsBidirectNetPath(true);
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e.setIsDisabledCond(true);
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e.setHasDisabledCond(true);
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e.setIsDisabledLoop(true);
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e.setDelayAnnotationIsIncremental(true);
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EXPECT_TRUE(e.isBidirectInstPath());
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EXPECT_TRUE(e.isBidirectNetPath());
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EXPECT_TRUE(e.isDisabledCond());
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EXPECT_TRUE(e.hasDisabledCond());
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EXPECT_TRUE(e.isDisabledLoop());
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EXPECT_TRUE(e.delay_Annotation_Is_Incremental());
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e.setIsBidirectInstPath(false);
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e.setIsBidirectNetPath(false);
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e.setIsDisabledCond(false);
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e.setHasDisabledCond(false);
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e.setIsDisabledLoop(false);
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e.setDelayAnnotationIsIncremental(false);
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EXPECT_FALSE(e.isBidirectInstPath());
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EXPECT_FALSE(e.isBidirectNetPath());
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EXPECT_FALSE(e.isDisabledCond());
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EXPECT_FALSE(e.hasDisabledCond());
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EXPECT_FALSE(e.isDisabledLoop());
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EXPECT_FALSE(e.delay_Annotation_Is_Incremental());
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}
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@@ -903,27 +805,23 @@ TEST(VertexStandaloneTest, MultipleFlagInteraction)
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Vertex v;
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v.setHasChecks(true);
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v.setIsCheckClk(true);
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v.setIsGatedClkEnable(true);
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v.setHasDownstreamClkPin(true);
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v.setIsConstrained(true);
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v.setVisited(true);
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v.setVisited2(true);
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v.setIsDisabledConstraint(true);
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v.setHasSimValue(true);
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EXPECT_TRUE(v.hasChecks());
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EXPECT_TRUE(v.isCheckClk());
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EXPECT_TRUE(v.isGatedClkEnable());
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EXPECT_TRUE(v.hasDownstreamClkPin());
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EXPECT_TRUE(v.isConstrained());
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EXPECT_TRUE(v.visited());
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EXPECT_TRUE(v.visited2());
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EXPECT_TRUE(v.isDisabledConstraint());
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EXPECT_TRUE(v.hasSimValue());
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// Clear each individually and verify others unaffected
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v.setHasChecks(false);
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EXPECT_FALSE(v.hasChecks());
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EXPECT_TRUE(v.isCheckClk());
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EXPECT_TRUE(v.isConstrained());
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EXPECT_TRUE(v.hasSimValue());
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}
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// Test Edge multiple flag combinations
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@@ -933,13 +831,13 @@ TEST(EdgeStandaloneTest, MultipleFlagInteraction)
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Edge e;
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e.setIsBidirectInstPath(true);
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e.setIsBidirectNetPath(true);
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e.setIsDisabledCond(true);
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e.setHasDisabledCond(true);
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e.setIsDisabledLoop(true);
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e.setDelayAnnotationIsIncremental(true);
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EXPECT_TRUE(e.isBidirectInstPath());
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EXPECT_TRUE(e.isBidirectNetPath());
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EXPECT_TRUE(e.isDisabledCond());
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EXPECT_TRUE(e.hasDisabledCond());
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EXPECT_TRUE(e.isDisabledLoop());
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EXPECT_TRUE(e.delay_Annotation_Is_Incremental());
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@@ -956,11 +854,10 @@ TEST(EdgeStandaloneTest, MultipleFlagInteraction)
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#include "Network.hh"
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#include "Liberty.hh"
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#include "ReportTcl.hh"
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#include "Corner.hh"
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#include "Scene.hh"
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#include "Search.hh"
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#include "TimingArc.hh"
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#include "PortDirection.hh"
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#include "DcalcAnalysisPt.hh"
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namespace sta {
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@@ -976,7 +873,7 @@ protected:
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if (report)
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report->setTclInterp(interp_);
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Corner *corner = sta_->cmdCorner();
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Scene *corner = sta_->cmdScene();
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const MinMaxAll *min_max = MinMaxAll::all();
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bool infer_latches = false;
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@@ -1151,7 +1048,7 @@ protected:
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if (report)
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report->setTclInterp(interp_);
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Corner *corner = sta_->cmdCorner();
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Scene *corner = sta_->cmdScene();
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const MinMaxAll *min_max = MinMaxAll::all();
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LibertyLibrary *lib = sta_->readLiberty(
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"test/nangate45/Nangate45_typ.lib", corner, min_max, false);
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@@ -1172,28 +1069,28 @@ protected:
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FloatSeq *waveform = new FloatSeq;
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waveform->push_back(0.0f);
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waveform->push_back(5.0f);
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sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr);
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sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr, sta_->cmdMode());
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Clock *clk = sta_->sdc()->findClock("clk");
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Clock *clk = sta_->cmdSdc()->findClock("clk");
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ASSERT_NE(clk, nullptr);
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Pin *d1_pin = network->findPin(top, "d1");
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ASSERT_NE(d1_pin, nullptr);
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sta_->setInputDelay(d1_pin, RiseFallBoth::riseFall(), clk,
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RiseFall::rise(), nullptr, false, false,
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MinMaxAll::all(), false, 1.0f);
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MinMaxAll::all(), false, 1.0f, sta_->cmdSdc());
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Pin *d2_pin = network->findPin(top, "d2");
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ASSERT_NE(d2_pin, nullptr);
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sta_->setInputDelay(d2_pin, RiseFallBoth::riseFall(), clk,
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RiseFall::rise(), nullptr, false, false,
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MinMaxAll::all(), false, 1.0f);
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MinMaxAll::all(), false, 1.0f, sta_->cmdSdc());
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Pin *en_pin = network->findPin(top, "en");
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ASSERT_NE(en_pin, nullptr);
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sta_->setInputDelay(en_pin, RiseFallBoth::riseFall(), clk,
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RiseFall::rise(), nullptr, false, false,
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MinMaxAll::all(), false, 1.0f);
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MinMaxAll::all(), false, 1.0f, sta_->cmdSdc());
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design_loaded_ = true;
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}
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@@ -1530,7 +1427,7 @@ protected:
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if (report)
|
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report->setTclInterp(interp_);
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|
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Corner *corner = sta_->cmdCorner();
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Scene *corner = sta_->cmdScene();
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const MinMaxAll *min_max = MinMaxAll::all();
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LibertyLibrary *lib = sta_->readLiberty(
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"test/nangate45/Nangate45_typ.lib", corner, min_max, false);
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@@ -1552,7 +1449,7 @@ protected:
|
||||
FloatSeq *wave1 = new FloatSeq;
|
||||
wave1->push_back(0.0f);
|
||||
wave1->push_back(5.0f);
|
||||
sta_->makeClock("clk1", clk1_pins, false, 10.0f, wave1, nullptr);
|
||||
sta_->makeClock("clk1", clk1_pins, false, 10.0f, wave1, nullptr, sta_->cmdMode());
|
||||
|
||||
// Create clock2
|
||||
Pin *clk2_pin = network->findPin(top, "clk2");
|
||||
@@ -1562,10 +1459,10 @@ protected:
|
||||
FloatSeq *wave2 = new FloatSeq;
|
||||
wave2->push_back(0.0f);
|
||||
wave2->push_back(2.5f);
|
||||
sta_->makeClock("clk2", clk2_pins, false, 5.0f, wave2, nullptr);
|
||||
sta_->makeClock("clk2", clk2_pins, false, 5.0f, wave2, nullptr, sta_->cmdMode());
|
||||
|
||||
// Input delays
|
||||
Clock *clk1 = sta_->sdc()->findClock("clk1");
|
||||
Clock *clk1 = sta_->cmdSdc()->findClock("clk1");
|
||||
ASSERT_NE(clk1, nullptr);
|
||||
const char *inputs[] = {"d1", "d2", "d3", "d4"};
|
||||
for (const char *name : inputs) {
|
||||
@@ -1573,7 +1470,7 @@ protected:
|
||||
ASSERT_NE(pin, nullptr);
|
||||
sta_->setInputDelay(pin, RiseFallBoth::riseFall(), clk1,
|
||||
RiseFall::rise(), nullptr, false, false,
|
||||
MinMaxAll::all(), false, 1.0f);
|
||||
MinMaxAll::all(), false, 1.0f, sta_->cmdSdc());
|
||||
}
|
||||
|
||||
design_loaded_ = true;
|
||||
@@ -1741,7 +1638,7 @@ protected:
|
||||
if (report)
|
||||
report->setTclInterp(interp_);
|
||||
|
||||
Corner *corner = sta_->cmdCorner();
|
||||
Scene *corner = sta_->cmdScene();
|
||||
const MinMaxAll *min_max = MinMaxAll::all();
|
||||
LibertyLibrary *lib = sta_->readLiberty(
|
||||
"test/nangate45/Nangate45_typ.lib", corner, min_max, false);
|
||||
@@ -1761,22 +1658,22 @@ protected:
|
||||
FloatSeq *waveform = new FloatSeq;
|
||||
waveform->push_back(0.0f);
|
||||
waveform->push_back(5.0f);
|
||||
sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr);
|
||||
sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr, sta_->cmdMode());
|
||||
|
||||
Clock *clk = sta_->sdc()->findClock("clk");
|
||||
Clock *clk = sta_->cmdSdc()->findClock("clk");
|
||||
ASSERT_NE(clk, nullptr);
|
||||
|
||||
Pin *d1_pin = network->findPin(top, "d1");
|
||||
ASSERT_NE(d1_pin, nullptr);
|
||||
sta_->setInputDelay(d1_pin, RiseFallBoth::riseFall(), clk,
|
||||
RiseFall::rise(), nullptr, false, false,
|
||||
MinMaxAll::all(), false, 1.0f);
|
||||
MinMaxAll::all(), false, 1.0f, sta_->cmdSdc());
|
||||
|
||||
Pin *d2_pin = network->findPin(top, "d2");
|
||||
ASSERT_NE(d2_pin, nullptr);
|
||||
sta_->setInputDelay(d2_pin, RiseFallBoth::riseFall(), clk,
|
||||
RiseFall::rise(), nullptr, false, false,
|
||||
MinMaxAll::all(), false, 1.0f);
|
||||
MinMaxAll::all(), false, 1.0f, sta_->cmdSdc());
|
||||
|
||||
design_loaded_ = true;
|
||||
}
|
||||
@@ -1992,13 +1889,13 @@ protected:
|
||||
report->setTclInterp(interp_);
|
||||
|
||||
// Define two corners
|
||||
StringSet corner_names;
|
||||
corner_names.insert("fast");
|
||||
corner_names.insert("slow");
|
||||
sta_->makeCorners(&corner_names);
|
||||
StringSeq scene_names;
|
||||
scene_names.push_back("fast");
|
||||
scene_names.push_back("slow");
|
||||
sta_->makeScenes(&scene_names);
|
||||
|
||||
Corner *fast_corner = sta_->findCorner("fast");
|
||||
Corner *slow_corner = sta_->findCorner("slow");
|
||||
Scene *fast_corner = sta_->findScene("fast");
|
||||
Scene *slow_corner = sta_->findScene("slow");
|
||||
ASSERT_NE(fast_corner, nullptr);
|
||||
ASSERT_NE(slow_corner, nullptr);
|
||||
|
||||
@@ -2026,16 +1923,16 @@ protected:
|
||||
FloatSeq *waveform = new FloatSeq;
|
||||
waveform->push_back(0.0f);
|
||||
waveform->push_back(5.0f);
|
||||
sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr);
|
||||
sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr, sta_->cmdMode());
|
||||
|
||||
Clock *clk = sta_->sdc()->findClock("clk");
|
||||
Clock *clk = sta_->cmdSdc()->findClock("clk");
|
||||
ASSERT_NE(clk, nullptr);
|
||||
|
||||
Pin *d1_pin = network->findPin(top, "d1");
|
||||
ASSERT_NE(d1_pin, nullptr);
|
||||
sta_->setInputDelay(d1_pin, RiseFallBoth::riseFall(), clk,
|
||||
RiseFall::rise(), nullptr, false, false,
|
||||
MinMaxAll::all(), false, 1.0f);
|
||||
MinMaxAll::all(), false, 1.0f, sta_->cmdSdc());
|
||||
|
||||
fast_corner_ = fast_corner;
|
||||
slow_corner_ = slow_corner;
|
||||
@@ -2051,8 +1948,8 @@ protected:
|
||||
|
||||
Sta *sta_;
|
||||
Tcl_Interp *interp_;
|
||||
Corner *fast_corner_ = nullptr;
|
||||
Corner *slow_corner_ = nullptr;
|
||||
Scene *fast_corner_ = nullptr;
|
||||
Scene *slow_corner_ = nullptr;
|
||||
bool design_loaded_ = false;
|
||||
};
|
||||
|
||||
@@ -2078,8 +1975,8 @@ TEST_F(GraphMultiCornerTest, DelaysDifferByCorner) {
|
||||
ASSERT_NE(arc, nullptr);
|
||||
|
||||
// Get delay for each corner
|
||||
DcalcAPIndex fast_idx = fast_corner_->findDcalcAnalysisPt(MinMax::max())->index();
|
||||
DcalcAPIndex slow_idx = slow_corner_->findDcalcAnalysisPt(MinMax::max())->index();
|
||||
DcalcAPIndex fast_idx = fast_corner_->dcalcAnalysisPtIndex(MinMax::max());
|
||||
DcalcAPIndex slow_idx = slow_corner_->dcalcAnalysisPtIndex(MinMax::max());
|
||||
ArcDelay fast_delay = graph->arcDelay(edge, arc, fast_idx);
|
||||
ArcDelay slow_delay = graph->arcDelay(edge, arc, slow_idx);
|
||||
|
||||
@@ -2101,8 +1998,8 @@ TEST_F(GraphMultiCornerTest, SlewsDifferByCorner) {
|
||||
Vertex *v = graph->pinDrvrVertex(buf1_z);
|
||||
ASSERT_NE(v, nullptr);
|
||||
|
||||
DcalcAPIndex fast_idx = fast_corner_->findDcalcAnalysisPt(MinMax::max())->index();
|
||||
DcalcAPIndex slow_idx = slow_corner_->findDcalcAnalysisPt(MinMax::max())->index();
|
||||
DcalcAPIndex fast_idx = fast_corner_->dcalcAnalysisPtIndex(MinMax::max());
|
||||
DcalcAPIndex slow_idx = slow_corner_->dcalcAnalysisPtIndex(MinMax::max());
|
||||
const Slew &fast_slew = graph->slew(v, RiseFall::rise(), fast_idx);
|
||||
const Slew &slow_slew = graph->slew(v, RiseFall::rise(), slow_idx);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user