Merge branch 'parallaxsw:master' into master
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commit
85ae6b6d27
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@ -8,6 +8,7 @@ member variable - snake case with trailing underscore (member_variable_)
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Trailing underscore prevents conflict with accessor
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member function name.
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function - lower camel case (functionName)
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variable - snake case
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comments - use capitalized sentences that end with periods
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C++ code files should use a .cc file extension
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@ -55,7 +56,7 @@ this:
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instead, write this:
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foo = (char *) malloc (sizeof *foo);
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if (foo == 0)
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if (foo == nullptr)
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fatal ("virtual memory exhausted");
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@ -1236,7 +1236,7 @@ public:
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void setCmdCorner(Corner *corner);
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Corner *findCorner(const char *corner_name);
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bool multiCorner();
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void makeCorners(StringSet *corner_names);
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virtual void makeCorners(StringSet *corner_names);
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// Find all arc delays and vertex slews with delay calculator.
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virtual void findDelays();
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// Find arc delays and vertex slews thru to level of to_vertex.
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@ -1852,10 +1852,15 @@ LibertyCell::makeLatchEnable(LibertyPort *d,
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latch_d_to_q_map_[d_to_q] = latch_enable;
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latch_check_map_[setup_check] = latch_enable;
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latch_data_ports_.insert(d);
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debugPrint(debug, "liberty", 2, "latch d=%s en=%s %s q=%s",
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debugPrint(debug, "liberty_latch", 1,
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"latch %s -> %s | %s %s -> %s | %s %s -> %s setup",
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d->name(),
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q->name(),
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en->name(),
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en_rf->name(),
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en_rf->shortName(),
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q->name(),
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en->name(),
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setup_check->arcs()[0]->fromEdge()->asRiseFall()->shortName(),
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q->name());
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return latch_enable;
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}
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@ -425,13 +425,15 @@ void
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SdfReader::timingCheck(TimingRole *role, SdfPortSpec *data_edge,
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SdfPortSpec *clk_edge, SdfTriple *triple)
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{
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const char *data_port_name = data_edge->port();
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const char *clk_port_name = clk_edge->port();
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Cell *cell = network_->cell(instance_);
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Port *data_port = findPort(cell, data_port_name);
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Port *clk_port = findPort(cell, clk_port_name);
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if (data_port && clk_port)
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timingCheck1(role, data_port, data_edge, clk_port, clk_edge, triple);
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if (instance_) {
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const char *data_port_name = data_edge->port();
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const char *clk_port_name = clk_edge->port();
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Cell *cell = network_->cell(instance_);
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Port *data_port = findPort(cell, data_port_name);
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Port *clk_port = findPort(cell, clk_port_name);
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if (data_port && clk_port)
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timingCheck1(role, data_port, data_edge, clk_port, clk_edge, triple);
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}
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deletePortSpec(data_edge);
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deletePortSpec(clk_edge);
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deleteTriple(triple);
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