ArrivalVisitor::visit rm Sdc::isPathDelayInternalEndpoint dependence
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry
parent
0e9974bf63
commit
8401a27857
118
search/Search.cc
118
search/Search.cc
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@ -1083,71 +1083,65 @@ ArrivalVisitor::visit(Vertex *vertex)
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debugPrint(debug, "search", 2, "find arrivals %s",
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vertex->name(sdc_network));
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Pin *pin = vertex->pin();
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// Don't clobber clock sources.
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if (!sdc->isLeafPinClock(pin)
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// Unless it is an internal path delay endpoint.
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|| sdc->isPathDelayInternalEndpoint(pin)) {
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tag_bldr_->init(vertex);
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has_fanin_one_ = graph->hasFaninOne(vertex);
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if (crpr_active_
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&& !has_fanin_one_)
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tag_bldr_no_crpr_->init(vertex);
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tag_bldr_->init(vertex);
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has_fanin_one_ = graph->hasFaninOne(vertex);
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if (crpr_active_
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&& !has_fanin_one_)
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tag_bldr_no_crpr_->init(vertex);
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visitFaninPaths(vertex);
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if (crpr_active_
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&& search->crprPathPruningEnabled()
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&& !vertex->crprPathPruningDisabled()
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&& !has_fanin_one_)
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pruneCrprArrivals();
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visitFaninPaths(vertex);
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if (crpr_active_
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&& search->crprPathPruningEnabled()
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&& !vertex->crprPathPruningDisabled()
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&& !has_fanin_one_)
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pruneCrprArrivals();
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// Insert paths that originate here but
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if (!network->isTopLevelPort(pin)
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&& sdc->hasInputDelay(pin))
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// set_input_delay on internal pin.
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search->seedInputSegmentArrival(pin, vertex, tag_bldr_);
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if (sdc->isPathDelayInternalStartpoint(pin))
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// set_min/max_delay on internal pin.
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search->makeUnclkedPaths(vertex, true, true, tag_bldr_);
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if (sdc->isPathDelayInternalEndpoint(pin)
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&& sdc->isLeafPinClock(pin))
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// set_min/max_delay on internal pin also a clock src. Bizzaroland.
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// Re-seed the clock arrivals on top of the propagated paths.
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search->seedClkArrivals(pin, vertex, tag_bldr_);
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// Register/latch clock pin that is not connected to a declared clock.
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// Seed with unclocked tag, zero arrival and allow search thru reg
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// clk->q edges.
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// These paths are required to report path delays from unclocked registers
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// For example, "set_max_delay -to" from an unclocked source register.
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bool is_clk = tag_bldr_->hasClkTag();
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if (vertex->isRegClk() && !is_clk) {
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debugPrint(debug, "search", 2, "arrival seed unclked reg clk %s",
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network->pathName(pin));
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search->makeUnclkedPaths(vertex, true, false, tag_bldr_);
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}
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bool arrivals_changed = search->arrivalsChanged(vertex, tag_bldr_);
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// If vertex is a latch data input arrival that changed from the
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// previous eval pass enqueue the latch outputs to be re-evaled on the
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// next pass.
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if (network->isLatchData(pin)) {
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if (arrivals_changed
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&& network->isLatchData(pin))
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search->enqueueLatchDataOutputs(vertex);
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}
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if (!search->arrivalsAtEndpointsExist()
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|| always_to_endpoints_
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|| arrivals_changed)
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search->arrivalIterator()->enqueueAdjacentVertices(vertex, adj_pred_);
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if (arrivals_changed) {
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debugPrint(debug, "search", 4, "arrival changed");
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// Only update arrivals when delays change by more than
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// fuzzyEqual can distinguish.
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search->setVertexArrivals(vertex, tag_bldr_);
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search->tnsInvalid(vertex);
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constrainedRequiredsInvalid(vertex, is_clk);
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}
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enqueueRefPinInputDelays(pin);
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// Insert paths that originate here.
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if (!network->isTopLevelPort(pin)
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&& sdc->hasInputDelay(pin))
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// set_input_delay on internal pin.
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search->seedInputSegmentArrival(pin, vertex, tag_bldr_);
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if (sdc->isPathDelayInternalStartpoint(pin))
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// set_min/max_delay -from internal pin.
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search->makeUnclkedPaths(vertex, true, true, tag_bldr_);
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if (sdc->isLeafPinClock(pin))
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// set_min/max_delay -to internal pin also a clock src. Bizzaroland.
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// Re-seed the clock arrivals on top of the propagated paths.
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search->seedClkArrivals(pin, vertex, tag_bldr_);
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// Register/latch clock pin that is not connected to a declared clock.
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// Seed with unclocked tag, zero arrival and allow search thru reg
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// clk->q edges.
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// These paths are required to report path delays from unclocked registers
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// For example, "set_max_delay -to" from an unclocked source register.
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bool is_clk = tag_bldr_->hasClkTag();
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if (vertex->isRegClk() && !is_clk) {
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debugPrint(debug, "search", 2, "arrival seed unclked reg clk %s",
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network->pathName(pin));
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search->makeUnclkedPaths(vertex, true, false, tag_bldr_);
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}
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bool arrivals_changed = search->arrivalsChanged(vertex, tag_bldr_);
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// If vertex is a latch data input arrival that changed from the
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// previous eval pass enqueue the latch outputs to be re-evaled on the
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// next pass.
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if (network->isLatchData(pin)) {
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if (arrivals_changed
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&& network->isLatchData(pin))
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search->enqueueLatchDataOutputs(vertex);
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}
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if (!search->arrivalsAtEndpointsExist()
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|| always_to_endpoints_
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|| arrivals_changed)
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search->arrivalIterator()->enqueueAdjacentVertices(vertex, adj_pred_);
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if (arrivals_changed) {
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debugPrint(debug, "search", 4, "arrival changed");
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// Only update arrivals when delays change by more than
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// fuzzyEqual can distinguish.
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search->setVertexArrivals(vertex, tag_bldr_);
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search->tnsInvalid(vertex);
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constrainedRequiredsInvalid(vertex, is_clk);
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}
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enqueueRefPinInputDelays(pin);
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}
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// When a clock arrival changes, the required time changes for any
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