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WriteSpice rm dead code 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2026-01-11 19:52:55 -08:00
parent b58ff962d6
commit 7f65853afa
1 changed files with 1 additions and 100 deletions
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101
spice/WriteSpice.cc
View File

@ -43,6 +43,7 @@
#include "Path.hh" #include "Path.hh"
#include "DcalcAnalysisPt.hh" #include "DcalcAnalysisPt.hh"
#include "Bdd.hh" #include "Bdd.hh"
#include "cudd.h"
namespace sta { namespace sta {
@ -850,8 +851,6 @@ WriteSpice::gatePortValues(const Pin *input_pin,
} }
} }
#if CUDD
void void
WriteSpice::gatePortValues(const Instance *, WriteSpice::gatePortValues(const Instance *,
const FuncExpr *expr, const FuncExpr *expr,
@ -895,104 +894,6 @@ WriteSpice::gatePortValues(const Instance *,
bdd_.clearVarMap(); bdd_.clearVarMap();
} }
#else
void
WriteSpice::gatePortValues(const Instance *inst,
const FuncExpr *expr,
const LibertyPort *input_port,
// Return values.
LibertyPortLogicValues &port_values)
{
FuncExpr *left = expr->left();
FuncExpr *right = expr->right();
switch (expr->op()) {
case FuncExpr::op_port:
break;
case FuncExpr::op_not:
gatePortValues(inst, left, input_port, port_values);
break;
case FuncExpr::op_or:
if (left->hasPort(input_port)
&& right->op() == FuncExpr::op_port) {
gatePortValues(inst, left, input_port, port_values);
port_values[right->port()] = LogicValue::zero;
}
else if (left->hasPort(input_port)
&& right->op() == FuncExpr::op_not
&& right->left()->op() == FuncExpr::op_port) {
// input_port + !right_port
gatePortValues(inst, left, input_port, port_values);
port_values[right->left()->port()] = LogicValue::one;
}
else if (right->hasPort(input_port)
&& left->op() == FuncExpr::op_port) {
gatePortValues(inst, right, input_port, port_values);
port_values[left->port()] = LogicValue::zero;
}
else if (right->hasPort(input_port)
&& left->op() == FuncExpr::op_not
&& left->left()->op() == FuncExpr::op_port) {
// input_port + !left_port
gatePortValues(inst, right, input_port, port_values);
port_values[left->left()->port()] = LogicValue::one;
}
else {
gatePortValues(inst, left, input_port, port_values);
gatePortValues(inst, right, input_port, port_values);
}
break;
case FuncExpr::op_and:
if (left->hasPort(input_port)
&& right->op() == FuncExpr::op_port) {
gatePortValues(inst, left, input_port, port_values);
port_values[right->port()] = LogicValue::one;
}
else if (left->hasPort(input_port)
&& right->op() == FuncExpr::op_not
&& right->left()->op() == FuncExpr::op_port) {
// input_port * !right_port
gatePortValues(inst, left, input_port, port_values);
port_values[right->left()->port()] = LogicValue::zero;
}
else if (right->hasPort(input_port)
&& left->op() == FuncExpr::op_port) {
gatePortValues(inst, right, input_port, port_values);
port_values[left->port()] = LogicValue::one;
}
else if (right->hasPort(input_port)
&& left->op() == FuncExpr::op_not
&& left->left()->op() == FuncExpr::op_port) {
// input_port * !left_port
gatePortValues(inst, right, input_port, port_values);
port_values[left->left()->port()] = LogicValue::zero;
}
else {
gatePortValues(inst, left, input_port, port_values);
gatePortValues(inst, right, input_port, port_values);
}
break;
case FuncExpr::op_xor:
// Need to know timing arc sense to get this right.
if (left->port() == input_port
&& right->op() == FuncExpr::op_port)
port_values[right->port()] = LogicValue::zero;
else if (right->port() == input_port
&& left->op() == FuncExpr::op_port)
port_values[left->port()] = LogicValue::zero;
else {
gatePortValues(inst, left, input_port, port_values);
gatePortValues(inst, right, input_port, port_values);
}
break;
case FuncExpr::op_one:
case FuncExpr::op_zero:
break;
}
}
#endif
void void
WriteSpice::regPortValues(const Pin *input_pin, WriteSpice::regPortValues(const Pin *input_pin,
const RiseFall *drvr_rf, const RiseFall *drvr_rf,