input ref pin graph edges

Signed-off-by: James Cherry <[email protected]>

include/sta/PortDelay.hh

@@ -51,6 +51,8 @@ public:
   const Pin *refPin() const { return ref_pin_; }
   void setRefPin(const Pin *ref_pin);
   const RiseFall *refTransition() const;
+  bool refPinEdgesExist() const { return ref_pin_edges_exist_; }
+  void setRefPinEdgesExist(bool exists);
 
 protected:
   PortDelay(const Pin *pin,
@@ -62,6 +64,7 @@ protected:
   bool source_latency_included_{false};
   bool network_latency_included_{false};
   const Pin *ref_pin_{nullptr};
+  bool ref_pin_edges_exist_{false};
   RiseFallMinMax delays_;
   PinSet leaf_pins_;
 };

include/sta/Sdc.hh

@@ -576,6 +576,7 @@ public:
                         const Clock *clk,
                         const RiseFall *clk_rf,
                         const MinMaxAll *min_max);
+  void ensureInputDelayRefPinEdges();
   void setOutputDelay(const Pin *pin,
                       const RiseFallBoth *rf,
                       const Clock *clk,
@@ -806,7 +807,6 @@ public:
                             const MinMaxAll *min_max);
 
   // STA interface.
-  InputDelaySet *refPinInputDelays(const Pin *ref_pin) const;
   const LogicValueMap &logicValues() const { return logic_value_map_; }
   const LogicValueMap &caseLogicValues() const { return case_value_map_; }
   // Returns nullptr if set_operating_conditions has not been called.
@@ -1217,6 +1217,7 @@ protected:
                          InputDelay *except);
   void deleteInputDelaysReferencing(const Clock *clk);
   void deleteInputDelay(InputDelay *input_delay);
+
   OutputDelay *findOutputDelay(const Pin *pin,
                                const ClockEdge *clk_edge);
   OutputDelay *makeOutputDelay(const Pin *pin,
@@ -1225,6 +1226,7 @@ protected:
                           OutputDelay *except);
   void deleteOutputDelaysReferencing(const Clock *clk);
   void deleteOutputDelay(OutputDelay *output_delay);
+
   void deleteClockInsertion(ClockInsertion *insertion);
   void deleteClockInsertionsReferencing(Clock *clk);
   void deleteInterClockUncertainty(InterClockUncertainty *uncertainties);
@@ -1330,7 +1332,7 @@ protected:
 
   InputDelaySet input_delays_;
   InputDelaysPinMap input_delay_pin_map_;
-  InputDelaysPinMap input_delay_ref_pin_map_;
+  bool have_input_delay_ref_pins_{false};
   // Input delays on hierarchical pins are indexed by the load pins.
   InputDelaysPinMap input_delay_leaf_pin_map_;
   InputDelaysPinMap input_delay_internal_pin_map_;

include/sta/Search.hh

@@ -800,8 +800,6 @@ public:
 
 protected:
   void init0();
-  void enqueueRefPinInputDelays(const Pin *ref_pin,
-                                const Sdc *sdc);
   void seedArrivals(Vertex *vertex);
   void pruneCrprArrivals();
   void constrainedRequiredsInvalid(Vertex *vertex,

include/sta/TimingArc.hh

@@ -204,6 +204,9 @@ public:
   static int wireArcIndex(const RiseFall *rf);
   static int wireArcCount() { return 2; }
 
+  // Psuedo definition for port ref_pin arcs.
+  static TimingArcSet *portRefPinTimingArcSet() { return port_refpin_timing_arc_set_; }
+
 protected:
   TimingArcSet(const TimingRole *role,
                TimingArcAttrsPtr attrs);
@@ -230,6 +233,7 @@ protected:
 
   static TimingArcAttrsPtr wire_timing_arc_attrs_;
   static TimingArcSet *wire_timing_arc_set_;
+  static TimingArcSet *port_refpin_timing_arc_set_;
 };
 
 // A timing arc is a single from/to transition between two ports.

include/sta/TimingRole.hh

@@ -68,6 +68,7 @@ public:
   static const TimingRole *nonSeqHold() { return &non_seq_hold_; }
   static const TimingRole *clockTreePathMin() { return &clock_tree_path_min_; }
   static const TimingRole *clockTreePathMax() { return &clock_tree_path_max_; }
+  static const TimingRole *portDelayRefPin() { return &port_delay_ref_pin_; }
   const std::string &to_string() const { return name_; }
   int index() const { return index_; }
   bool isWire() const;
@@ -139,6 +140,8 @@ private:
   static const TimingRole non_seq_hold_;
   static const TimingRole clock_tree_path_min_;
   static const TimingRole clock_tree_path_max_;
+  // Artificial timing from input/output_delay ref_pin to the input/output.
+  static const TimingRole port_delay_ref_pin_;
   static TimingRoleMap timing_roles_;
 
   friend class TimingRoleLess;