dcalc
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@ -779,8 +779,8 @@ DmpCap::loadDelaySlew(const Pin *,
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ArcDelay &delay,
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Slew &slew)
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{
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delay = static_cast<float>(elmore);
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slew = static_cast<float>(gate_slew_);
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delay = elmore;
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slew = gate_slew_;
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}
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bool
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@ -1645,22 +1645,25 @@ DmpCeffDelayCalc::setCeffAlgorithm(const LibertyLibrary *drvr_library,
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double rpi,
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double c1)
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{
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double rd = gate_model
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? gateModelRd(drvr_cell, gate_model, in_slew, c2, c1,
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related_out_cap, pvt, pocv_enabled_)
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: 0.0;
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// Zero Rd means the table is constant and thus independent of load cap.
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if (rd < 1e-2
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// Rpi is small compared to Rd, which makes the load capacitive.
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|| rpi < rd * 1e-3
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// c1/Rpi can be ignored.
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|| (c1 == 0.0 || c1 < c2 * 1e-3 || rpi == 0.0))
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dmp_alg_ = dmp_cap_;
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else if (c2 < c1 * 1e-3)
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dmp_alg_ = dmp_zero_c2_;
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double rd = 0.0;
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if (gate_model) {
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rd = gateModelRd(drvr_cell, gate_model, in_slew, c2, c1,
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related_out_cap, pvt, pocv_enabled_);
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// Zero Rd means the table is constant and thus independent of load cap.
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if (rd < 1e-2
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// Rpi is small compared to Rd, which makes the load capacitive.
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|| rpi < rd * 1e-3
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// c1/Rpi can be ignored.
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|| (c1 == 0.0 || c1 < c2 * 1e-3 || rpi == 0.0))
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dmp_alg_ = dmp_cap_;
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else if (c2 < c1 * 1e-3)
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dmp_alg_ = dmp_zero_c2_;
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else
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// The full monty.
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dmp_alg_ = dmp_pi_;
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}
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else
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// The full monty.
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dmp_alg_ = dmp_pi_;
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dmp_alg_ = dmp_cap_;
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dmp_alg_->init(drvr_library, drvr_cell, pvt, gate_model,
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drvr_rf_, rd, in_slew, related_out_cap, c2, rpi, c1);
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debugPrint6(debug_, "dmp_ceff", 3,
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