factor variables out of sdc

Signed-off-by: James Cherry <[email protected]>

include/sta/GraphDelayCalc.hh

@@ -132,6 +132,7 @@ public:
 		    const RiseFall *from_rf,
                     const TimingRole *role,
 		    const DcalcAnalysisPt *dcalc_ap);
+  bool bidirectDrvrSlewFromLoad(const Pin *pin) const;
 
 protected:
   void seedInvalidDelays();
@@ -246,7 +247,6 @@ protected:
   Slew checkEdgeClkSlew(const Vertex *from_vertex,
 			const RiseFall *from_rf,
 			const DcalcAnalysisPt *dcalc_ap);
-  bool bidirectDrvrSlewFromLoad(const Vertex *vertex) const;
   float loadCap(const Pin *drvr_pin,
                 const RiseFall *rf,
                 const DcalcAnalysisPt *dcalc_ap,

include/sta/Sdc.hh

@@ -733,6 +733,7 @@ public:
   // combinational loops when dynamic loop breaking is enabled.
   void makeLoopExceptions();
   void makeLoopExceptions(GraphLoop *loop);
+  void deleteLoopExceptions();
   void makeMulticyclePath(ExceptionFrom *from,
 			  ExceptionThruSeq *thrus,
 			  ExceptionTo *to,
@@ -793,54 +794,6 @@ public:
   const WireloadSelection *wireloadSelection(const MinMax *min_max);
   void setWireloadSelection(WireloadSelection *selection,
 			    const MinMaxAll *min_max);
-  // Common reconvergent clock pessimism.
-  // TCL variable sta_crpr_enabled.
-  bool crprEnabled() const;
-  void setCrprEnabled(bool enabled);
-  // TCL variable sta_crpr_mode.
-  CrprMode crprMode() const;
-  void setCrprMode(CrprMode mode);
-  // True when analysis type is on chip variation and crpr is enabled.
-  bool crprActive() const;
-  // TCL variable sta_propagate_gated_clock_enable.
-  // Propagate gated clock enable arrivals.
-  bool propagateGatedClockEnable() const;
-  void setPropagateGatedClockEnable(bool enable);
-  // TCL variable sta_preset_clear_arcs_enabled.
-  // Enable search through preset/clear arcs.
-  bool presetClrArcsEnabled() const;
-  void setPresetClrArcsEnabled(bool enable);
-  // TCL variable sta_cond_default_arcs_enabled.
-  // Enable/disable default arcs when conditional arcs exist.
-  bool condDefaultArcsEnabled() const;
-  void setCondDefaultArcsEnabled(bool enabled);
-  bool isDisabledCondDefault(Edge *edge) const;
-  // TCL variable sta_internal_bidirect_instance_paths_enabled.
-  // Enable/disable timing from bidirect pins back into the instance.
-  bool bidirectInstPathsEnabled() const;
-  void setBidirectInstPathsEnabled(bool enabled);
-  // TCL variable sta_bidirect_net_paths_enabled.
-  // Enable/disable timing from bidirect driver pins to their own loads.
-  bool bidirectNetPathsEnabled() const;
-  void setBidirectNetPathsEnabled(bool enabled);
-  // TCL variable sta_recovery_removal_checks_enabled.
-  bool recoveryRemovalChecksEnabled() const;
-  void setRecoveryRemovalChecksEnabled(bool enabled);
-  // TCL variable sta_gated_clock_checks_enabled.
-  bool gatedClkChecksEnabled() const;
-  void setGatedClkChecksEnabled(bool enabled);
-  // TCL variable sta_dynamic_loop_breaking.
-  bool dynamicLoopBreaking() const;
-  void setDynamicLoopBreaking(bool enable);
-  // TCL variable sta_propagate_all_clocks.
-  bool propagateAllClocks() const;
-  void setPropagateAllClocks(bool prop);
-  // TCL var sta_clock_through_tristate_enabled.
-  bool clkThruTristateEnabled() const;
-  void setClkThruTristateEnabled(bool enable);
-  // TCL variable sta_input_port_default_clock.
-  bool useDefaultArrivalClock();
-  void setUseDefaultArrivalClock(bool enable);
 
   // STA interface.
   InputDelaySet *refPinInputDelays(const Pin *ref_pin) const;
@@ -1071,7 +1024,6 @@ public:
 			  const Pin *drvr,
 			  const Pin *load);
   void ensureClkHpinDisables();
-  bool bidirectDrvrSlewFromLoad(const Pin *pin) const;
 
 protected:
   void portMembers(const Port *port,
@@ -1214,7 +1166,6 @@ protected:
 			 const Pin *loop_prev_pin);
   void makeLoopExceptionThru(const Pin *pin,
 			     ExceptionThruSeq *thrus);
-  void deleteLoopExceptions();
   void deleteConstraints();
   InputDelay *findInputDelay(const Pin *pin,
 			     const ClockEdge *clk_edge);
@@ -1317,7 +1268,6 @@ protected:
   int clk_index_;
   // Default clock used for unclocked input arrivals.
   Clock *default_arrival_clk_;
-  bool use_default_arrival_clock_;
   ClockNameMap clock_name_map_;
   ClockPinMap clock_pin_map_;
   // Clocks on hierarchical pins are indexed by the load pins.
@@ -1430,19 +1380,6 @@ protected:
   Wireload *wireload_[MinMax::index_count];
   WireloadMode wireload_mode_;
   WireloadSelection *wireload_selection_[MinMax::index_count];
-  bool crpr_enabled_;
-  CrprMode crpr_mode_;
-  bool pocv_enabled_;
-  bool propagate_gated_clock_enable_;
-  bool preset_clr_arcs_enabled_;
-  bool cond_default_arcs_enabled_;
-  bool bidirect_net_paths_enabled_;
-  bool bidirect_inst_paths_enabled_;
-  bool recovery_removal_checks_enabled_;
-  bool gated_clk_checks_enabled_;
-  bool clk_thru_tristate_enabled_;
-  bool dynamic_loop_breaking_;
-  bool propagate_all_clks_;
 
   // Annotations on graph objects that are stored in constraints
   // rather on the graph itself.

include/sta/SdcClass.hh

@@ -122,8 +122,6 @@ public:
 class ExceptionPath;
 typedef Set<ExceptionState*, ExceptionStateLess> ExceptionStateSet;
 
-enum class CrprMode { same_pin, same_transition };
-
 // Constraint applies to clock or data paths.
 enum class PathClkOrData { clk, data };
 

include/sta/Search.hh

@@ -861,11 +861,11 @@ protected:
 class DynLoopSrchPred
 {
 public:
-  explicit DynLoopSrchPred(TagGroupBldr *tag_bldr);
+  DynLoopSrchPred(TagGroupBldr *tag_bldr);
 
 protected:
   bool loopEnabled(Edge *edge,
-		   const Sdc *sdc,
+                   bool dynamic_loop_breaking_enabled,
 		   const Graph *graph,
 		   Search *search);
   bool hasPendingLoopPaths(Edge *edge,

include/sta/Sta.hh

@@ -38,6 +38,7 @@
 #include "PowerClass.hh"
 #include "ArcDelayCalc.hh"
 #include "CircuitSim.hh"
+#include "Variables.hh"
 
 struct Tcl_Interp;
 
@@ -436,8 +437,6 @@ public:
   void removeDisable(TimingArcSet *arc_set);
   // Edge is disabled by constant.
   bool isDisabledConstant(Edge *edge);
-  // Edge is default cond disabled by timing_disable_cond_default_arcs var.
-  bool isDisabledCondDefault(Edge *edge);
   // Return a set of constant pins that disabled edge.
   // Caller owns the returned set.
   PinSet disabledConstantPins(Edge *edge);
@@ -793,61 +792,7 @@ public:
 		bool no_version);
   // Remove all delay and slew annotations.
   void removeDelaySlewAnnotations();
-  // TCL variable sta_crpr_enabled.
-  // Common Reconvergent Clock Removal (CRPR).
-  // Timing check source/target common clock path overlap for search
-  // with analysis mode on_chip_variation.
-  bool crprEnabled() const;
-  void setCrprEnabled(bool enabled);
-  // TCL variable sta_crpr_mode.
-  CrprMode crprMode() const;
-  void setCrprMode(CrprMode mode);
-  // TCL variable sta_pocv_enabled.
-  // Parametric on chip variation (statisical sta).
-  bool pocvEnabled() const;
-  void setPocvEnabled(bool enabled);
-  // Number of std deviations from mean to use for normal distributions.
-  void setSigmaFactor(float factor);
-  // TCL variable sta_propagate_gated_clock_enable.
-  // Propagate gated clock enable arrivals.
-  bool propagateGatedClockEnable() const;
-  void setPropagateGatedClockEnable(bool enable);
-  // TCL variable sta_preset_clear_arcs_enabled.
-  // Enable search through preset/clear arcs.
-  bool presetClrArcsEnabled() const;
-  void setPresetClrArcsEnabled(bool enable);
-  // TCL variable sta_cond_default_arcs_enabled.
-  // Enable/disable default arcs when conditional arcs exist.
-  bool condDefaultArcsEnabled() const;
-  void setCondDefaultArcsEnabled(bool enabled);
-  // TCL variable sta_internal_bidirect_instance_paths_enabled.
-  // Enable/disable timing from bidirect pins back into the instance.
-  bool bidirectInstPathsEnabled() const;
-  void setBidirectInstPathsEnabled(bool enabled);
-  // TCL variable sta_bidirect_net_paths_enabled.
-  // Enable/disable timing from bidirect driver pins to their own loads.
-  bool bidirectNetPathsEnabled() const;
-  void setBidirectNetPathsEnabled(bool enabled);
-  // TCL variable sta_recovery_removal_checks_enabled.
-  bool recoveryRemovalChecksEnabled() const;
-  void setRecoveryRemovalChecksEnabled(bool enabled);
-  // TCL variable sta_gated_clock_checks_enabled.
-  bool gatedClkChecksEnabled() const;
-  void setGatedClkChecksEnabled(bool enabled);
-  // TCL variable sta_dynamic_loop_breaking.
-  bool dynamicLoopBreaking() const;
-  void setDynamicLoopBreaking(bool enable);
-  // TCL variable sta_propagate_all_clocks.
-  // Clocks defined after sta_propagate_all_clocks is true
-  // are propagated (existing clocks are not effected).
-  bool propagateAllClocks() const;
-  void setPropagateAllClocks(bool prop);
-  // TCL var sta_clock_through_tristate_enabled.
-  bool clkThruTristateEnabled() const;
-  void setClkThruTristateEnabled(bool enable);
-  // TCL variable sta_input_port_default_clock.
-  bool useDefaultArrivalClock() const;
-  void setUseDefaultArrivalClock(bool enable);
+
   virtual CheckErrorSeq &checkTiming(bool no_input_delay,
 				     bool no_output_delay,
 				     bool reg_multiple_clks,
@@ -1178,7 +1123,9 @@ public:
                                   bool includes_pin_caps,
                                   const ParasiticAnalysisPt *ap);
 
+  ////////////////////////////////////////////////////////////////
   // TCL network edit function support.
+
   virtual Instance *makeInstance(const char *name,
 				 LibertyCell *cell,
 				 Instance *parent);
@@ -1322,10 +1269,71 @@ public:
                       const char *gnd_name,
                       CircuitSim ckt_sim);
 
+  ////////////////////////////////////////////////////////////////
+  // TCL Variables
+
+  // TCL variable sta_crpr_enabled.
+  // Common Reconvergent Clock Removal (CRPR).
+  // Timing check source/target common clock path overlap for search
+  // with analysis mode on_chip_variation.
+  bool crprEnabled() const;
+  void setCrprEnabled(bool enabled);
+  // TCL variable sta_crpr_mode.
+  CrprMode crprMode() const;
+  void setCrprMode(CrprMode mode);
+  // TCL variable sta_pocv_enabled.
+  // Parametric on chip variation (statisical sta).
+  bool pocvEnabled() const;
+  void setPocvEnabled(bool enabled);
+  // Number of std deviations from mean to use for normal distributions.
+  void setSigmaFactor(float factor);
+  // TCL variable sta_propagate_gated_clock_enable.
+  // Propagate gated clock enable arrivals.
+  bool propagateGatedClockEnable() const;
+  void setPropagateGatedClockEnable(bool enable);
+  // TCL variable sta_preset_clear_arcs_enabled.
+  // Enable search through preset/clear arcs.
+  bool presetClrArcsEnabled() const;
+  void setPresetClrArcsEnabled(bool enable);
+  // TCL variable sta_cond_default_arcs_enabled.
+  // Enable/disable default arcs when conditional arcs exist.
+  bool condDefaultArcsEnabled() const;
+  void setCondDefaultArcsEnabled(bool enabled);
+  // TCL variable sta_internal_bidirect_instance_paths_enabled.
+  // Enable/disable timing from bidirect pins back into the instance.
+  bool bidirectInstPathsEnabled() const;
+  void setBidirectInstPathsEnabled(bool enabled);
+  // TCL variable sta_bidirect_net_paths_enabled.
+  // Enable/disable timing from bidirect driver pins to their own loads.
+  bool bidirectNetPathsEnabled() const;
+  void setBidirectNetPathsEnabled(bool enabled);
+  // TCL variable sta_recovery_removal_checks_enabled.
+  bool recoveryRemovalChecksEnabled() const;
+  void setRecoveryRemovalChecksEnabled(bool enabled);
+  // TCL variable sta_gated_clock_checks_enabled.
+  bool gatedClkChecksEnabled() const;
+  void setGatedClkChecksEnabled(bool enabled);
+  // TCL variable sta_dynamic_loop_breaking.
+  bool dynamicLoopBreaking() const;
+  void setDynamicLoopBreaking(bool enable);
+  // TCL variable sta_propagate_all_clocks.
+  // Clocks defined after sta_propagate_all_clocks is true
+  // are propagated (existing clocks are not effected).
+  bool propagateAllClocks() const;
+  void setPropagateAllClocks(bool prop);
+  // TCL var sta_clock_through_tristate_enabled.
+  bool clkThruTristateEnabled() const;
+  void setClkThruTristateEnabled(bool enable);
+  // TCL variable sta_input_port_default_clock.
+  bool useDefaultArrivalClock() const;
+  void setUseDefaultArrivalClock(bool enable);
+  ////////////////////////////////////////////////////////////////
+
 protected:
   // Default constructors that are called by makeComponents in the Sta
   // constructor.  These can be redefined by a derived class to
   // specialize the sta components.
+  virtual void makeVariables();
   virtual void makeReport();
   virtual void makeDebug();
   virtual void makeUnits();

include/sta/StaState.hh

@@ -35,6 +35,7 @@ class NetworkReader;
 class Sdc;
 class Corners;
 class Graph;
+class Edge;
 class Levelize;
 class Sim;
 class Search;
@@ -44,6 +45,7 @@ class GraphDelayCalc;
 class Latches;
 class ClkNetwork;
 class DispatchQueue;
+class Variables;
 
 // Most STA components use functionality in other components.
 // This class simplifies the process of copying pointers to the
@@ -54,7 +56,7 @@ class StaState
 public:
   // Make an empty state.
   StaState();
-  explicit StaState(const StaState *sta);
+  StaState(const StaState *sta);
   // Copy the state from sta.  This is virtual so that a component
   // can notify sub-components.
   virtual void copyState(const StaState *sta);
@@ -102,8 +104,12 @@ public:
   ClkNetwork *clkNetwork() { return clk_network_; }
   ClkNetwork *clkNetwork() const { return clk_network_; }
   unsigned threadCount() const { return thread_count_; }
-  bool pocvEnabled() const { return pocv_enabled_; }
   float sigmaFactor() const { return sigma_factor_; }
+  bool crprActive() const;
+  Variables *variables() { return variables_; }
+  const Variables *variables() const { return variables_; }
+  // Edge is default cond disabled by timing_disable_cond_default_arcs var.
+  bool isDisabledCondDefault(Edge *edge) const;
 
 protected:
   Report *report_;
@@ -126,8 +132,8 @@ protected:
   ClkNetwork *clk_network_;
   int thread_count_;
   DispatchQueue *dispatch_queue_;
-  bool pocv_enabled_;
   float sigma_factor_;
+  Variables *variables_;
 };
 
 } // namespace

include/sta/Variables.hh

@@ -0,0 +1,98 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2025, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+#pragma once
+
+namespace sta {
+
+enum class CrprMode { same_pin, same_transition };
+
+// TCL Variables
+class Variables
+{
+public:
+  Variables();
+  // TCL variable sta_propagate_gated_clock_enable.
+  bool crprEnabled() const { return crpr_enabled_; }
+  void setCrprEnabled(bool enabled);
+  CrprMode crprMode() const { return crpr_mode_; }
+  void setCrprMode(CrprMode mode);
+  // Propagate gated clock enable arrivals.
+  bool propagateGatedClockEnable() const { return propagate_gated_clock_enable_; }
+  void setPropagateGatedClockEnable(bool enable);
+  // TCL variable sta_preset_clear_arcs_enabled.
+  // Enable search through preset/clear arcs.
+  bool presetClrArcsEnabled() const { return preset_clr_arcs_enabled_; }
+  void setPresetClrArcsEnabled(bool enable);
+  // TCL variable sta_cond_default_arcs_enabled.
+  // Enable/disable default arcs when conditional arcs exist.
+  bool condDefaultArcsEnabled() const { return cond_default_arcs_enabled_; }
+  void setCondDefaultArcsEnabled(bool enabled);
+  // TCL variable sta_internal_bidirect_instance_paths_enabled.
+  // Enable/disable timing from bidirect pins back into the instance.
+  bool bidirectInstPathsEnabled() const { return bidirect_inst_paths_enabled_; }
+  void setBidirectInstPathsEnabled(bool enabled);
+  // TCL variable sta_bidirect_net_paths_enabled.
+  // Enable/disable timing from bidirect driver pins to their own loads.
+  bool bidirectNetPathsEnabled() const { return bidirect_net_paths_enabled_; }
+  void setBidirectNetPathsEnabled(bool enabled);
+  // TCL variable sta_recovery_removal_checks_enabled.
+  bool recoveryRemovalChecksEnabled() const { return recovery_removal_checks_enabled_; }
+  void setRecoveryRemovalChecksEnabled(bool enabled);
+  // TCL variable sta_gated_clock_checks_enabled.
+  bool gatedClkChecksEnabled() const { return gated_clk_checks_enabled_; }
+  void setGatedClkChecksEnabled(bool enabled);
+  // TCL variable sta_dynamic_loop_breaking.
+  bool dynamicLoopBreaking() const { return dynamic_loop_breaking_; }
+  void setDynamicLoopBreaking(bool enable);
+  // TCL variable sta_propagate_all_clocks.
+  bool propagateAllClocks() const { return propagate_all_clks_; }
+  void setPropagateAllClocks(bool prop);
+  // TCL var sta_clock_through_tristate_enabled.
+  bool clkThruTristateEnabled() const { return clk_thru_tristate_enabled_; }
+  void setClkThruTristateEnabled(bool enable);
+  // TCL variable sta_input_port_default_clock.
+  bool useDefaultArrivalClock() { return use_default_arrival_clock_; }
+  void setUseDefaultArrivalClock(bool enable);
+  bool pocvEnabled() const { return pocv_enabled_; }
+  void setPocvEnabled(bool enabled);
+
+private:
+  bool crpr_enabled_;
+  CrprMode crpr_mode_;
+  bool propagate_gated_clock_enable_;
+  bool preset_clr_arcs_enabled_;
+  bool cond_default_arcs_enabled_;
+  bool bidirect_net_paths_enabled_;
+  bool bidirect_inst_paths_enabled_;
+  bool recovery_removal_checks_enabled_;
+  bool gated_clk_checks_enabled_;
+  bool clk_thru_tristate_enabled_;
+  bool dynamic_loop_breaking_;
+  bool propagate_all_clks_;
+  bool use_default_arrival_clock_;
+  bool pocv_enabled_;
+};
+
+} // namespace