tidy round1

network/ConcreteLibrary.cc

@@ -351,8 +351,8 @@ BusPort::addBusBit(ConcretePort *port,
 }
 
 void
-ConcreteCell::groupBusPorts(const char bus_brkt_left,
-                            const char bus_brkt_right,
+ConcreteCell::groupBusPorts(char bus_brkt_left,
+                            char bus_brkt_right,
                             std::function<bool(std::string_view)> port_msb_first)
 {
   const char bus_brkts_left[2]{bus_brkt_left, '\0'};
@@ -625,4 +625,4 @@ ConcreteCellPortBitIterator::findNext()
   next_ = nullptr;
 }
 
-} // namespace
+} // namespace sta

network/ConcreteNetwork.cc

@@ -2125,4 +2125,4 @@ ConcreteBindingTbl::ensureBinding(Net *proto_net,
   return net;
 }
 
-} // namespace
+} // namespace sta

network/HpinDrvrLoad.cc

@@ -326,4 +326,4 @@ HpinDrvrLoadLess::operator()(const HpinDrvrLoad *drvr_load1,
     return load1 < load2;
 }
 
-} // namespace
+} // namespace sta

network/Network.cc

@@ -2040,4 +2040,4 @@ NetSet::NetSet(const Network *network) :
 {
 }
 
-} // namespace
+} // namespace sta

network/NetworkCmp.cc

@@ -137,4 +137,4 @@ sortByPathName(NetSet *set,
   return nets;
 }
 
-} // namespace
+} // namespace sta

network/ParseBus.cc

@@ -190,4 +190,4 @@ escapeChars(std::string_view token,
   return escaped;
 }
 
-} // namespace
+} // namespace sta

network/PortDirection.cc

@@ -76,7 +76,7 @@ PortDirection::destroy()
 }
 
 PortDirection::PortDirection(const char *name,
-                             int index) :
+                             size_t index) :
   name_(name),
   index_(index)
 {
@@ -135,4 +135,4 @@ PortDirection::isPowerGround() const
     || this == well_;
 }
 
-} // namespace
+} // namespace sta

network/SdcNetwork.cc

@@ -1271,4 +1271,4 @@ escapeBrackets(std::string_view name,
   return escapeChars(name, '[', ']', network->pathEscape());
 }
 
-} // namespace
+} // namespace sta

network/VerilogNamespace.cc

@@ -219,4 +219,4 @@ verilogToSta(std::string_view verilog_name)
     return std::string(verilog_name);
 }
 
-} // namespace
+} // namespace sta