Merge remote-tracking branch 'upstream/master'
Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
commit
60a45c13b7
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@ -423,6 +423,8 @@ public:
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void setIsMemory(bool is_memory);
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bool isPad() const { return is_pad_; }
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void setIsPad(bool is_pad);
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bool isClockCell() const { return is_clock_cell_; }
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void setIsClockCell(bool is_clock_cell);
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bool isLevelShifter() const { return is_level_shifter_; }
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void setIsLevelShifter(bool is_level_shifter);
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LevelShifterType levelShifterType() const { return level_shifter_type_; }
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@ -564,6 +566,7 @@ protected:
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bool is_macro_;
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bool is_memory_;
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bool is_pad_;
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bool is_clock_cell_;
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bool is_level_shifter_;
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LevelShifterType level_shifter_type_;
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bool is_isolation_cell_;
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@ -925,6 +925,7 @@ LibertyCell::LibertyCell(LibertyLibrary *library,
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is_macro_(false),
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is_memory_(false),
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is_pad_(false),
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is_clock_cell_(false),
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is_level_shifter_(false),
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level_shifter_type_(LevelShifterType::HL_LH),
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is_isolation_cell_(false),
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@ -1077,6 +1078,12 @@ LibertyCell::LibertyCell::setIsPad(bool is_pad)
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is_pad_ = is_pad;
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}
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void
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LibertyCell::LibertyCell::setIsClockCell(bool is_clock_cell)
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{
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is_clock_cell_ = is_clock_cell;
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}
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void
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LibertyCell::setIsLevelShifter(bool is_level_shifter)
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{
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@ -298,6 +298,7 @@ LibertyReader::defineVisitors()
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defineAttrVisitor("is_macro", &LibertyReader::visitIsMacro);
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defineAttrVisitor("is_memory", &LibertyReader::visitIsMemory);
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defineAttrVisitor("is_pad", &LibertyReader::visitIsPad);
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defineAttrVisitor("is_clock_cell", &LibertyReader::visitIsClockCell);
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defineAttrVisitor("is_level_shifter", &LibertyReader::visitIsLevelShifter);
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defineAttrVisitor("level_shifter_type", &LibertyReader::visitLevelShifterType);
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defineAttrVisitor("is_isolation_cell", &LibertyReader::visitIsIsolationCell);
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@ -2819,6 +2820,17 @@ LibertyReader::visitIsPad(LibertyAttr *attr)
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}
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}
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void
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LibertyReader::visitIsClockCell(LibertyAttr *attr)
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{
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if (cell_) {
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bool is_clock_cell, exists;
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getAttrBool(attr, is_clock_cell, exists);
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if (exists)
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cell_->setIsClockCell(is_clock_cell);
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}
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}
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void
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LibertyReader::visitIsLevelShifter(LibertyAttr *attr)
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{
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@ -188,6 +188,7 @@ public:
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virtual void visitIsMacro(LibertyAttr *attr);
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virtual void visitIsMemory(LibertyAttr *attr);
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virtual void visitIsPad(LibertyAttr *attr);
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virtual void visitIsClockCell(LibertyAttr *attr);
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virtual void visitIsLevelShifter(LibertyAttr *attr);
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virtual void visitLevelShifterType(LibertyAttr *attr);
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virtual void visitIsIsolationCell(LibertyAttr *attr);
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@ -17,7 +17,6 @@
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#include "Units.hh"
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#include <cmath> // abs
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#include <limits>
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#include "StringUtil.hh"
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#include "MinMax.hh" // INF
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@ -17,6 +17,7 @@
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#include "ConcreteLibrary.hh"
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#include <cstdlib>
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#include <limits>
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#include "PatternMatch.hh"
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#include "PortDirection.hh"
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@ -26,6 +27,10 @@
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namespace sta {
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using std::map;
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using std::min;
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using std::max;
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using std::abs;
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using std::swap;
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static constexpr char escape_ = '\\';
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@ -289,67 +294,47 @@ ConcreteCell::portBitIterator() const
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////////////////////////////////////////////////////////////////
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// Helper class for ConcreteCell::groupBusPorts.
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class BusPort
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{
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public:
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BusPort(const char *name,
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int from,
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PortDirection *direction);
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~BusPort();
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const char *name() const { return name_; }
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void pushMember(ConcretePort *port);
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void setFrom(int from);
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void setTo(int to);
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BusPort();
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void addBusBit(ConcretePort *port,
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int index);
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int from() const { return from_; }
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int to() const { return to_; }
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ConcretePortSeq *members() { return members_; }
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ConcretePortSeq &members() { return members_; }
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void setDirection(PortDirection *direction);
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PortDirection *direction() { return direction_; }
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private:
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const char *name_;
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int from_;
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int to_;
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PortDirection *direction_;
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ConcretePortSeq *members_;
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ConcretePortSeq members_;
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};
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BusPort::BusPort(const char *name,
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int from,
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PortDirection *direction) :
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name_(stringCopy(name)),
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from_(from),
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to_(from),
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direction_(direction),
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members_(new ConcretePortSeq)
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BusPort::BusPort() :
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from_(std::numeric_limits<int>::max()),
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to_(std::numeric_limits<int>::min())
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{
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}
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BusPort::~BusPort()
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{
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// members_ ownership is transfered to bus port.
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stringDelete(name_);
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}
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void
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BusPort::pushMember(ConcretePort *port)
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BusPort::setDirection(PortDirection *direction)
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{
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members_->push_back(port);
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direction_ = direction;
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}
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void
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BusPort::setFrom(int from)
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BusPort::addBusBit(ConcretePort *port,
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int index)
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{
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from_ = from;
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from_ = min(from_, index);
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to_ = max(to_, index);
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members_.push_back(port);
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}
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void
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BusPort::setTo(int to)
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{
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to_ = to;
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}
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typedef Map<const char*, BusPort*, CharPtrLess> BusPortMap;
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void
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ConcreteCell::groupBusPorts(const char bus_brkt_left,
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const char bus_brkt_right,
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@ -357,7 +342,7 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
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{
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const char bus_brkts_left[2]{bus_brkt_left, '\0'};
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const char bus_brkts_right[2]{bus_brkt_right, '\0'};
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map<string, BusPort*> port_map;
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map<string, BusPort> bus_map;
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// Find ungrouped bus ports.
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// Remove bus bit ports from the ports_ vector during the scan by
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// keeping an index to the next insertion index and skipping over
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@ -373,64 +358,35 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
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is_bus, bus_name, index);
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if (is_bus) {
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if (!port->isBusBit()) {
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auto name_bus_port = port_map.find(bus_name);
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BusPort *bus_port;
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if (name_bus_port == port_map.end()) {
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bus_port = new BusPort(bus_name.c_str(), index, port->direction());
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port_map[bus_name] = bus_port;
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}
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else
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bus_port = name_bus_port->second;
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bus_port->pushMember(port);
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BusPort &bus_port = bus_map[bus_name];
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bus_port.addBusBit(port, index);
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port->setBusBitIndex(index);
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bus_port.setDirection(port->direction());
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}
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else
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ports_.push_back(port);
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}
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else
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ports_.push_back(port);
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}
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// Make the bus ports.
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for (auto name_bus : port_map) {
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const string &bus_name = name_bus.first;
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BusPort *bus_port = name_bus.second;
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for (auto name_bus : bus_map) {
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string bus_name = name_bus.first;
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BusPort &bus_port = name_bus.second;
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int from = bus_port.from();
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int to = bus_port.to();
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size_t size = to - from + 1;
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bool msb_first = port_msb_first(bus_name.c_str());
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ConcretePortSeq *members = bus_port->members();
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sort(members, [&](ConcretePort *port1,
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ConcretePort *port2) {
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bool is_bus;
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string bus_name;
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int index1, index2;
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parseBusName(port1->name(), bus_brkts_left, bus_brkts_right, escape_,
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is_bus, bus_name, index1);
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parseBusName(port2->name(), bus_brkts_left, bus_brkts_right, escape_,
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is_bus, bus_name, index2);
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return msb_first ? index1 > index2 : index1 < index2;
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});
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bool is_bus1;
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string bus_name1;
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int from_index, to_index;
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parseBusName((*members)[0]->name(),
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bus_brkts_left, bus_brkts_right, escape_,
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is_bus1, bus_name1, from_index);
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parseBusName((*members)[members->size() - 1]->name(),
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bus_brkts_left, bus_brkts_right, escape_,
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is_bus1, bus_name1, to_index);
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ConcretePort *port = makeBusPort(bus_name.c_str(), from_index,
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to_index, members);
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port->setDirection(bus_port->direction());
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delete bus_port;
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for (ConcretePort *port : *members) {
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bool is_bus;
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string bus_name;
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int index;
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parseBusName(port->name(), bus_brkts_left, bus_brkts_right, escape_,
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is_bus, bus_name, index);
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port->setBusBitIndex(index);
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ConcretePortSeq *members = new ConcretePortSeq(size);
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// Index the bus bit ports.
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for (ConcretePort *bus_bit : bus_port.members()) {
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int bit_index = bus_bit->busBitIndex();
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int member_index = msb_first ? to - bit_index : bit_index - from;
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(*members)[member_index] = bus_bit;
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}
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if (msb_first)
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swap(from, to);
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ConcretePort *port = makeBusPort(bus_name.c_str(), from, to, members);
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port->setDirection(bus_port.direction());
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}
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}
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@ -546,7 +502,8 @@ ConcretePort::setDirection(PortDirection *dir)
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ConcretePortMemberIterator *member_iter = memberIterator();
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while (member_iter->hasNext()) {
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ConcretePort *port_bit = member_iter->next();
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port_bit->setDirection(dir);
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if (port_bit)
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port_bit->setDirection(dir);
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}
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delete member_iter;
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}
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@ -853,21 +853,24 @@ ConcreteNetwork::hasMembers(const Port *port) const
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////////////////////////////////////////////////////////////////
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// This has to skip over missing bus bits in the members.
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class ConcretePortMemberIterator1 : public PortMemberIterator
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{
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public:
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explicit ConcretePortMemberIterator1(const ConcretePort *port);
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~ConcretePortMemberIterator1();
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virtual bool hasNext() { return iter_->hasNext(); }
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virtual bool hasNext();
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virtual Port *next();
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private:
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ConcretePortMemberIterator *iter_;
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ConcretePort *next_;
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};
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ConcretePortMemberIterator1::ConcretePortMemberIterator1(const ConcretePort *
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port) :
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iter_(port->memberIterator())
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iter_(port->memberIterator()),
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next_(nullptr)
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{
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}
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@ -876,10 +879,21 @@ ConcretePortMemberIterator1::~ConcretePortMemberIterator1()
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delete iter_;
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}
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bool
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ConcretePortMemberIterator1::hasNext()
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{
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while (next_ == nullptr
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&& iter_->hasNext())
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next_ = iter_->next();
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return next_ != nullptr;
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}
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Port *
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ConcretePortMemberIterator1::next()
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{
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return reinterpret_cast<Port*>(iter_->next());
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ConcretePort *next = next_;
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next_ = nullptr;
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return reinterpret_cast<Port*>(next);
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}
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PortMemberIterator *
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@ -16,7 +16,6 @@
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#include "ConcreteParasitics.hh"
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#include <limits>
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#include <algorithm> // max
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#include "Report.hh"
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@ -16,8 +16,6 @@
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#include "SpefReader.hh"
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#include <limits>
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#include "Zlib.hh"
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#include "Report.hh"
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#include "Debug.hh"
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@ -16,6 +16,8 @@
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#include "ReadVcdActivities.hh"
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#include <inttypes.h>
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#include "VcdReader.hh"
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#include "Debug.hh"
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#include "Network.hh"
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@ -212,7 +214,7 @@ ReadVcdActivities::findVarActivity(const VcdValues &var_values,
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for (const VcdValue &var_value : var_values) {
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VcdTime time = var_value.time();
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char value = var_value.value(value_bit);
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debugPrint(debug_, "read_vcd_activities", 3, " %ld %c", time, value);
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debugPrint(debug_, "read_vcd_activities", 3, " %" PRId64 " %c", time, value);
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if (prev_value == '1')
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high_time += time - prev_time;
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if (value != prev_value)
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