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prima multi-corner 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2024-07-30 09:15:45 -07:00
parent 330c3aaf24
commit 5f6ff47d83
5 changed files with 17 additions and 12 deletions
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3
dcalc/CcsCeffDelayCalc.cc
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@ -104,7 +104,8 @@ CcsCeffDelayCalc::gateDelay(const Pin *drvr_pin,
vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_; vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_;
vh_ = drvr_library->slewUpperThreshold(drvr_rf_) * vdd_; vh_ = drvr_library->slewUpperThreshold(drvr_rf_) * vdd_;
drvr_cell->ensureVoltageWaveforms(dcalc_ap); const DcalcAnalysisPtSeq &dcalc_aps = corners_->dcalcAnalysisPts();
drvr_cell->ensureVoltageWaveforms(dcalc_aps);
in_slew_ = delayAsFloat(in_slew); in_slew_ = delayAsFloat(in_slew);
output_waveforms_ = output_waveforms; output_waveforms_ = output_waveforms;
ref_time_ = output_waveforms_->referenceTime(in_slew_); ref_time_ = output_waveforms_->referenceTime(in_slew_);

3
dcalc/PrimaDelayCalc.cc
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@ -206,6 +206,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
bool failed = false; bool failed = false;
output_waveforms_.resize(drvr_count_); output_waveforms_.resize(drvr_count_);
const DcalcAnalysisPtSeq &dcalc_aps = corners_->dcalcAnalysisPts();
for (size_t drvr_idx = 0; drvr_idx < drvr_count_; drvr_idx++) { for (size_t drvr_idx = 0; drvr_idx < drvr_count_; drvr_idx++) {
ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx]; ArcDcalcArg &dcalc_arg = dcalc_args[drvr_idx];
GateTableModel *table_model = dcalc_arg.arc()->gateTableModel(dcalc_ap); GateTableModel *table_model = dcalc_arg.arc()->gateTableModel(dcalc_ap);
@ -226,7 +227,7 @@ PrimaDelayCalc::gateDelays(ArcDcalcArgSeq &dcalc_args,
drvr_library->supplyVoltage("VDD", vdd_, vdd_exists); drvr_library->supplyVoltage("VDD", vdd_, vdd_exists);
if (!vdd_exists) if (!vdd_exists)
report_->error(1720, "VDD not defined in library %s", drvr_library->name()); report_->error(1720, "VDD not defined in library %s", drvr_library->name());
drvr_cell->ensureVoltageWaveforms(dcalc_ap); drvr_cell->ensureVoltageWaveforms(dcalc_aps);
if (drvr_idx == 0) { if (drvr_idx == 0) {
vth_ = drvr_library->outputThreshold(drvr_rf_) * vdd_; vth_ = drvr_library->outputThreshold(drvr_rf_) * vdd_;
vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_; vl_ = drvr_library->slewLowerThreshold(drvr_rf_) * vdd_;

3
include/sta/Liberty.hh
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@ -80,6 +80,7 @@ typedef Vector<InternalPowerAttrs*> InternalPowerAttrsSeq;
typedef Map<const char *, float, CharPtrLess> SupplyVoltageMap; typedef Map<const char *, float, CharPtrLess> SupplyVoltageMap;
typedef Map<const char *, LibertyPgPort*, CharPtrLess> LibertyPgPortMap; typedef Map<const char *, LibertyPgPort*, CharPtrLess> LibertyPgPortMap;
typedef Map<const char *, DriverWaveform*, CharPtrLess> DriverWaveformMap; typedef Map<const char *, DriverWaveform*, CharPtrLess> DriverWaveformMap;
typedef Vector<DcalcAnalysisPt*> DcalcAnalysisPtSeq;
enum class ClockGateType { none, latch_posedge, latch_negedge, other }; enum class ClockGateType { none, latch_posedge, latch_negedge, other };
@ -532,7 +533,7 @@ public:
// Check all liberty cells to make sure they exist // Check all liberty cells to make sure they exist
// for all the defined corners. // for all the defined corners.
static void checkLibertyCorners(); static void checkLibertyCorners();
void ensureVoltageWaveforms(const DcalcAnalysisPt *dcalc_ap); void ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps);
protected: protected:
void addPort(ConcretePort *port); void addPort(ConcretePort *port);

14
liberty/Liberty.cc
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@ -1933,7 +1933,7 @@ LibertyCell::latchCheckEnableEdge(TimingArcSet *check_set)
} }
void void
LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPt *dcalc_ap) LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPtSeq &dcalc_aps)
{ {
if (!have_voltage_waveforms_) { if (!have_voltage_waveforms_) {
float vdd = 0.0; // shutup gcc float vdd = 0.0; // shutup gcc
@ -1943,11 +1943,13 @@ LibertyCell::ensureVoltageWaveforms(const DcalcAnalysisPt *dcalc_ap)
criticalError(1120, "library missing vdd"); criticalError(1120, "library missing vdd");
for (TimingArcSet *arc_set : timingArcSets()) { for (TimingArcSet *arc_set : timingArcSets()) {
for (TimingArc *arc : arc_set->arcs()) { for (TimingArc *arc : arc_set->arcs()) {
GateTableModel *model = arc->gateTableModel(dcalc_ap); for (const DcalcAnalysisPt *dcalc_ap : dcalc_aps) {
if (model) { GateTableModel *model = arc->gateTableModel(dcalc_ap);
OutputWaveforms *output_waveforms = model->outputWaveforms(); if (model) {
if (output_waveforms) OutputWaveforms *output_waveforms = model->outputWaveforms();
output_waveforms->makeVoltageWaveforms(vdd); if (output_waveforms)
output_waveforms->makeVoltageWaveforms(vdd);
}
} }
} }
} }

6
liberty/Liberty.i
View File

@ -289,9 +289,9 @@ timing_arc_sets()
void void
ensure_voltage_waveforms() ensure_voltage_waveforms()
{ {
Corner *corner = Sta::sta()->cmdCorner(); Corners *corners = Sta::sta()->corners();
DcalcAnalysisPt *dcalc_ap = corner->findDcalcAnalysisPt(MinMax::max()); const DcalcAnalysisPtSeq &dcalc_aps = corners->dcalcAnalysisPts();
self->ensureVoltageWaveforms(dcalc_ap); self->ensureVoltageWaveforms(dcalc_aps);
} }
} // LibertyCell methods } // LibertyCell methods