Fix write_verilog escape seq Issue 3826

Signed-off-by: dsengupta0628 <[email protected]>

test/test_write_verilog_escape.tcl

@@ -0,0 +1,11 @@
+# Check if "h1\x" and \Y[2:1] are correctly processed from input to output of Verilog
+
+
+read_liberty gf180mcu_sram.lib.gz
+read_liberty asap7_small.lib.gz
+
+read_verilog test_write_verilog_escape.v
+
+link_design multi_sink
+
+write_verilog test_write_verilog_escape_out.v

test/test_write_verilog_escape.v

@@ -0,0 +1,14 @@
+
+module \multi_sink (clk);
+ input clk;
+ wire \alu_adder_result_ex[0] ;
+ \hier_block \h1\x (.childclk(clk),  .\Y[2:1] ({ \alu_adder_result_ex[0] , \alu_adder_result_ex[0]  }) );
+endmodule // multi_sink
+
+module \hier_block (childclk, \Y[2:1] );
+   input childclk; 
+   output [1:0] \Y[2:1] ;
+   wire [1:0] \Y[2:1] ;
+   BUFx2_ASAP7_75t_R \ff0/name (.A(childclk));
+endmodule // hier_block1
+