make timing model setup/hold
Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
parent
f2c6b49d07
commit
55ec1973d0
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@ -59,6 +59,14 @@ public:
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LeakagePower *makeLeakagePower(LibertyCell *cell,
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LeakagePowerAttrs *attrs);
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TimingArcSet *makeFromTransitionArcs(LibertyCell *cell,
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LibertyPort *from_port,
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LibertyPort *to_port,
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LibertyPort *related_out,
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RiseFall *from_rf,
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TimingRole *role,
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TimingArcAttrs *attrs);
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protected:
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ConcretePort *makeBusPort(const char *name,
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int from_index,
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@ -111,13 +119,6 @@ protected:
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LibertyPort *related_out,
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RiseFall *from_rf,
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TimingArcAttrs *attrs);
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TimingArcSet *makeFromTransitionArcs(LibertyCell *cell,
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LibertyPort *from_port,
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LibertyPort *to_port,
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LibertyPort *related_out,
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RiseFall *from_rf,
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TimingRole *role,
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TimingArcAttrs *attrs);
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TimingArcSet *makePresetClrArcs(LibertyCell *cell,
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LibertyPort *from_port,
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LibertyPort *to_port,
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@ -352,7 +352,7 @@ CheckTableModel::CheckTableModel(TableModel *model,
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model_(model)
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{
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for (auto el_index : EarlyLate::rangeIndex())
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sigma_models_[el_index] = sigma_models[el_index];
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sigma_models_[el_index] = sigma_models ? sigma_models[el_index] : nullptr;
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}
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CheckTableModel::~CheckTableModel()
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@ -20,6 +20,8 @@
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#include "Units.hh"
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#include "Transition.hh"
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#include "Liberty.hh"
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#include "TimingArc.hh"
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#include "TableModel.hh"
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#include "liberty/LibertyBuilder.hh"
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#include "LibertyWriter.hh"
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#include "Network.hh"
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@ -29,6 +31,7 @@
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#include "dcalc/GraphDelayCalc1.hh"
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#include "Sdc.hh"
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#include "StaState.hh"
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#include "PathEnd.hh"
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#include "Sta.hh"
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namespace sta {
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@ -89,6 +92,7 @@ MakeTimingModel::makeTimingModel(const char *cell_name,
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findClkedOutputPaths();
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#endif
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findInputSetupHolds();
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cell_->finish(false, report_, debug_);
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}
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void
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@ -190,41 +194,64 @@ MakeTimingModel::findInputSetupHolds()
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Pin *input_pin = input_iter->next();
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if (network_->direction(input_pin)->isInput()
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&& !sta_->isClockSrc(input_pin)) {
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LibertyPort *input_port = modelPort(input_pin);
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for (Clock *clk : *sdc_->clocks()) {
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for (RiseFall *clk_rf : RiseFall::range()) {
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for (MinMax *min_max : MinMax::range()) {
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MinMaxAll *min_max2 = min_max->asMinMaxAll();
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bool setup = min_max == MinMax::max();
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bool hold = !setup;
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for (RiseFall *input_rf : RiseFall::range()) {
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sdc_->setInputDelay(input_pin, RiseFallBoth::riseFall(), clk, clk_rf,
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nullptr, false, false, min_max2, false, 0.0);
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for (const Pin *clk_pin : clk->pins()) {
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LibertyPort *clk_port = modelPort(clk_pin);
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for (RiseFall *clk_rf : RiseFall::range()) {
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for (MinMax *min_max : MinMax::range()) {
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MinMaxAll *min_max2 = min_max->asMinMaxAll();
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bool setup = min_max == MinMax::max();
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bool hold = !setup;
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TimingRole *role = setup ? TimingRole::setup() : TimingRole::hold();
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TimingArcAttrs *attrs = nullptr;
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for (RiseFall *input_rf : RiseFall::range()) {
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sdc_->setInputDelay(input_pin, RiseFallBoth::riseFall(), clk, clk_rf,
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nullptr, false, false, min_max2, false, 0.0);
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PinSet *from_pins = new PinSet;
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from_pins->insert(input_pin);
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ExceptionFrom *from = sta_->makeExceptionFrom(from_pins, nullptr, nullptr,
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input_rf->asRiseFallBoth());
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PinSet *from_pins = new PinSet;
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from_pins->insert(input_pin);
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ExceptionFrom *from = sta_->makeExceptionFrom(from_pins, nullptr, nullptr,
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input_rf->asRiseFallBoth());
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ClockSet *to_clks = new ClockSet;
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to_clks->insert(clk);
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ExceptionTo *to = sta_->makeExceptionTo(nullptr, to_clks, nullptr,
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clk_rf->asRiseFallBoth(),
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RiseFallBoth::riseFall());
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PathEndSeq *ends = sta_->findPathEnds(from, nullptr, to, false, corner_,
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min_max2,
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1, 1, false,
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-INF, INF, false, nullptr,
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setup, hold, setup, hold, setup, hold);
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if (!ends->empty()) {
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debugPrint(debug_, "timing_model", 1, "%s %s %s -> clock %s %s",
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setup ? "setup" : "hold",
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network_->pathName(input_pin),
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input_rf->asString(),
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clk->name(),
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clk_rf->asString());
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PathEnd *end = (*ends)[0];
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sta_->reportPathEnd(end);
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ClockSet *to_clks = new ClockSet;
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to_clks->insert(clk);
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ExceptionTo *to = sta_->makeExceptionTo(nullptr, to_clks, nullptr,
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clk_rf->asRiseFallBoth(),
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RiseFallBoth::riseFall());
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PathEndSeq *ends = sta_->findPathEnds(from, nullptr, to, false, corner_,
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min_max2,
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1, 1, false,
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-INF, INF, false, nullptr,
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setup, hold, setup, hold, setup, hold);
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if (!ends->empty()) {
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PathEnd *end = (*ends)[0];
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debugPrint(debug_, "timing_model", 1, "%s %s %s -> clock %s %s",
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setup ? "setup" : "hold",
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network_->pathName(input_pin),
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input_rf->asString(),
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clk->name(),
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clk_rf->asString());
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if (debug_->check("timing_model", 2))
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sta_->reportPathEnd(end);
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Arrival data_arrival = end->path()->arrival(sta_);
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Delay clk_latency = end->targetClkDelay(sta_);
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ArcDelay check_setup = end->margin(sta_);
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float margin = data_arrival - clk_latency + check_setup;
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ScaleFactorType scale_type = setup
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? ScaleFactorType::setup
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: ScaleFactorType::hold;
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TimingModel *check_model = makeScalarCheckModel(margin, scale_type, input_rf);
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if (attrs == nullptr)
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attrs = new TimingArcAttrs();
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attrs->setModel(input_rf, check_model);
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}
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}
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if (attrs)
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lib_builder_->makeFromTransitionArcs(cell_, clk_port,
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input_port, nullptr,
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clk_rf, role, attrs);
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}
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}
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}
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@ -273,4 +300,24 @@ MakeTimingModel::findClkedOutputPaths()
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}
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}
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LibertyPort *
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MakeTimingModel::modelPort(const Pin *pin)
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{
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return cell_->findLibertyPort(network_->name(network_->port(pin)));
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}
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TimingModel *
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MakeTimingModel::makeScalarCheckModel(float value,
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ScaleFactorType scale_factor_type,
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RiseFall *rf)
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{
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Table *table = new Table0(value);
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TableTemplate *tbl_template =
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library_->findTableTemplate("scalar", TableTemplateType::delay);
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TableModel *table_model = new TableModel(table, tbl_template,
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scale_factor_type, rf);
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CheckTableModel *check_model = new CheckTableModel(table_model, nullptr);
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return check_model;
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}
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} // namespace
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@ -47,6 +47,11 @@ private:
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void findInputSetupHolds();
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void findClkedOutputPaths();
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LibertyPort *modelPort(const Pin *pin);
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TimingModel *makeScalarCheckModel(float value,
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ScaleFactorType scale_factor_type,
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RiseFall *rf);
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Sta *sta_;
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LibertyLibrary *library_;
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LibertyCell *cell_;
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