Merge pull request #86 from akashlevy/libarcs_smallfix
Smallfix to get `liberty_arcs_one2one` tests consistently passing in regression
This commit is contained in:
James Cherry
GitHub
commit
55069f5691
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@ -1,3 +1,5 @@
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# Test get_* -filter
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# Read in design and libraries
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read_liberty asap7_small.lib.gz
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read_verilog reg1_asap7.v
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@ -1,220 +0,0 @@
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Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes.
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Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes.
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TEST 1:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_8_to_4)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[1] (input port clocked by clk)
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Endpoint: y[1] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[1] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_8_to_4)
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0.00 1.00 ^ y[1] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[2] (input port clocked by clk)
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Endpoint: y[2] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[2] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_8_to_4)
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0.00 1.00 ^ y[2] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[3] (input port clocked by clk)
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Endpoint: y[3] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[3] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_8_to_4)
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0.00 1.00 ^ y[3] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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TEST 2:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_4_to_8)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[1] (input port clocked by clk)
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Endpoint: y[1] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[1] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_4_to_8)
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0.00 1.00 ^ y[1] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[2] (input port clocked by clk)
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Endpoint: y[2] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[2] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_4_to_8)
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0.00 1.00 ^ y[2] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[3] (input port clocked by clk)
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Endpoint: y[3] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[3] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_4_to_8)
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0.00 1.00 ^ y[3] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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@ -1,17 +0,0 @@
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read_liberty liberty_arcs_one2one.lib
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puts "TEST 1:"
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read_verilog liberty_arcs_one2one_1.v
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link_design liberty_arcs_one2one_1
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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report_checks -group_count 5
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puts "TEST 2:"
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read_verilog liberty_arcs_one2one_2.v
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link_design liberty_arcs_one2one_2
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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report_checks -group_count 5
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@ -1,4 +1,4 @@
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library (one_to_one_mismatched_width) {
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library (liberty_arcs_one2one_1) {
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delay_model : "table_lookup";
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simulation : false;
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capacitive_load_unit (1,pF);
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@ -47,34 +47,7 @@ library (one_to_one_mismatched_width) {
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direction : "output";
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timing () {
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related_pin : "A";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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}
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}
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cell (inv_4_to_8) {
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bus (A) {
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capacitance : 1;
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bus_type : "bus4";
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direction : "input";
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}
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bus (Y) {
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function : "!A";
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bus_type : "bus8";
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direction : "output";
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timing () {
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related_pin : "A";
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timing_sense : "negative_unate";
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cell_rise (scalar) {
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values ("1");
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}
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@ -0,0 +1,21 @@
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Warning: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
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report_edges -from partial_wide_inv_cell/A[0]
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A[0] -> Y[0] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -from partial_wide_inv_cell/A[1]
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A[1] -> Y[1] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -from partial_wide_inv_cell/A[2]
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A[2] -> Y[2] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -from partial_wide_inv_cell/A[3]
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A[3] -> Y[3] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -from partial_wide_inv_cell/A[4]
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report_edges -from partial_wide_inv_cell/A[5]
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report_edges -from partial_wide_inv_cell/A[6]
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report_edges -from partial_wide_inv_cell/A[7]
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@ -0,0 +1,11 @@
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# Test one-to-one functionality with mismatched widths where A width (8) is larger than Y width (4)
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read_liberty liberty_arcs_one2one_1.lib
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read_verilog liberty_arcs_one2one_1.v
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link_design liberty_arcs_one2one_1
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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for {set i 0} {$i < 8} {incr i} {
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puts "report_edges -from partial_wide_inv_cell/A[$i]"
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report_edges -from partial_wide_inv_cell/A[$i]
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}
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@ -0,0 +1,66 @@
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library (liberty_arcs_one2one_2) {
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delay_model : "table_lookup";
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simulation : false;
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capacitive_load_unit (1,pF);
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leakage_power_unit : "1pW";
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current_unit : "1A";
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pulling_resistance_unit : "1kohm";
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time_unit : "1ns";
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voltage_unit : "1v";
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library_features : "report_delay_calculation";
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input_threshold_pct_rise : 50;
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input_threshold_pct_fall : 50;
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output_threshold_pct_rise : 50;
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output_threshold_pct_fall : 50;
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slew_lower_threshold_pct_rise : 30;
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slew_lower_threshold_pct_fall : 30;
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slew_upper_threshold_pct_rise : 70;
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slew_upper_threshold_pct_fall : 70;
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slew_derate_from_library : 1.0;
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nom_process : 1.0;
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nom_temperature : 85.0;
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nom_voltage : 0.75;
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type (bus8) {
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base_type : "array";
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data_type : "bit";
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bit_width : 8;
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bit_from : 7;
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bit_to : 0;
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}
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type (bus4) {
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base_type : "array";
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data_type : "bit";
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bit_width : 4;
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bit_from : 3;
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bit_to : 0;
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}
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cell (inv_4_to_8) {
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bus (A) {
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capacitance : 1;
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bus_type : "bus4";
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direction : "input";
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}
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bus (Y) {
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function : "!A";
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bus_type : "bus8";
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direction : "output";
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timing () {
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related_pin : "A";
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timing_sense : "negative_unate";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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}
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}
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}
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@ -0,0 +1,21 @@
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Warning: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.
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report_edges -to partial_wide_inv_cell/Y[0]
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A[0] -> Y[0] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -to partial_wide_inv_cell/Y[1]
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A[1] -> Y[1] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -to partial_wide_inv_cell/Y[2]
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A[2] -> Y[2] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -to partial_wide_inv_cell/Y[3]
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A[3] -> Y[3] combinational
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^ -> v 1.00:1.00
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v -> ^ 1.00:1.00
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report_edges -to partial_wide_inv_cell/Y[4]
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report_edges -to partial_wide_inv_cell/Y[5]
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report_edges -to partial_wide_inv_cell/Y[6]
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report_edges -to partial_wide_inv_cell/Y[7]
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@ -0,0 +1,11 @@
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# Test one-to-one functionality with mismatched widths where Y width (8) is larger than A width (4)
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read_liberty liberty_arcs_one2one_2.lib
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read_verilog liberty_arcs_one2one_2.v
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link_design liberty_arcs_one2one_2
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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for {set i 0} {$i < 8} {incr i} {
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puts "report_edges -to partial_wide_inv_cell/Y[$i]"
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report_edges -to partial_wide_inv_cell/Y[$i]
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}
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@ -124,7 +124,8 @@ record_example_tests {
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record_sta_tests {
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prima3
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verilog_attribute
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liberty_arcs_one2one
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liberty_arcs_one2one_1
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liberty_arcs_one2one_2
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get_filter
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}
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@ -1,3 +1,4 @@
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# Tests whether Verilog attributes can be parsed and retrieved correctly
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read_liberty ../examples/sky130hd_tt.lib
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read_verilog verilog_attribute.v
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link_design counter
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