luke/OpenSTA
1
0
Fork 0
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git synced 2026-09-04 08:43:04 +02:00
Code Issues Packages Projects Releases Wiki Activity

test: Apply review feedback - part2

Browse Source 
- Remove stale line-number coverage comments (# Targets: line NNN, hit=0)
- Remove useless file-existence checks from verilog/sdf tests
- Delete 21 orphaned dcalc Tcl tests (C++ tests already cover them)
- Rename liberty_ccsn_ecsm -> liberty_ccsn (no ECSM libs available)
- Fix liberty_sky130_corners to use define_corners/-corner for real multi-corner testing
- Add report_checks per wireload model in liberty_wireload
- Fix test/regression to work from test/ directory (label mismatch)
- Refactor all module CMakeLists.txt with sta_module_tests() macro

Co-Authored-By: Claude Opus 4.6 <[email protected]>
This commit is contained in:
Jaehyun Kim
2026-02-20 01:13:42 +09:00
co-authored by Claude Opus 4.6
parent 6799b1909a
commit 547737f71e
95 changed files with 314 additions and 6552 deletions
Download Patch File Download Diff File Expand all files Collapse all files
graph/test/CMakeLists.txt
+13 -75
View File
@@ -1,78 +1,16 @@
add_test(
NAME tcl.graph.make_verify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_make_verify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
sta_module_tests("graph"
TESTS
advanced
bidirect
delay_corners
delete_modify
incremental
make_verify
modify
operations
timing_edges
vertex_edge_ops
wire_inst_edges
)
set_tests_properties(tcl.graph.make_verify PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.timing_edges
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_timing_edges
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.timing_edges PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.advanced
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_advanced
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.advanced PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.incremental
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_incremental
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.incremental PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.delay_corners
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delay_corners
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.delay_corners PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.operations
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_operations
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.operations PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.modify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_modify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.modify PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.bidirect
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_bidirect
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.bidirect PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.wire_inst_edges
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_wire_inst_edges
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.wire_inst_edges PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.delete_modify
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_delete_modify
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.delete_modify PROPERTIES LABELS "tcl;module_graph")
add_test(
NAME tcl.graph.vertex_edge_ops
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> graph_vertex_edge_ops
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
)
set_tests_properties(tcl.graph.vertex_edge_ops PROPERTIES LABELS "tcl;module_graph")
add_subdirectory(cpp)
graph/test/graph_bidirect.tcl
-12
View File
@@ -1,17 +1,5 @@
# Test graph construction with bidirectional pins, reconvergent paths,
# and various edge/vertex operations.
# Targets: Graph.cc uncovered paths:
# makePinVertices for bidirect pins
# pinVertices for bidirect direction
# pinDrvrVertex for bidirect
# makePortInstanceEdges: bidirect from_bidirect_drvr_vertex path
# makeWireEdgesFromPin with multiple drivers
# hasFaninOne
# gateEdgeArc
# deleteVertex via delete operations
# isIsolatedNet
# vertex/edge iterators
source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib
graph/test/graph_vertex_edge_ops.tcl
-12
View File
@@ -1,18 +1,6 @@
# Test graph vertex and edge operations in depth: makeVertex, deleteVertex,
# makeEdge, deleteEdge, edge arc queries, bidirectional pin handling,
# hasFaninOne, vertex iteration, edge linking.
# Targets: Graph.cc uncovered:
# deleteVertex: edge cleanup during vertex deletion
# deleteInEdge / deleteOutEdge: linked list manipulation for edges
# hasFaninOne: single fanin check
# pinDrvrVertex / pinLoadVertex: bidirect driver vertex lookup
# gateEdgeArc: arc lookup by rise/fall
# makePaths / paths / deletePaths: vertex path management
# slew / setSlew: slew value access
# makeWireEdgesToPin: create wire edges to a pin
# isIsolatedNet: isolated net detection
# arcDelay / setArcDelay: edge arc delay access
source ../../test/helpers.tcl
read_liberty ../../test/nangate45/Nangate45_typ.lib