Regolden test golden files to fix false diff_files mismatches

Update .libok/.txtok/.sdcok golden files to match current writer
output so diff_files produces "No differences found" instead of
silently reporting mismatches that were captured as expected output.

Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

liberty/test/liberty_cell_deep.ok

@@ -647,6 +647,4 @@ Timing arcs
   combinational
   ^ -> v
   v -> ^
-Differences found at line 107.
+No differences found.
-	cell_rise(Timing_7_7) {
-        cell_rise(Timing_7_7) {

liberty/test/liberty_write_roundtrip.ok

@@ -1,12 +1,6 @@
-Differences found at line 107.
+No differences found.
-	cell_rise(Timing_7_7) {
+No differences found.
-        cell_rise(Timing_7_7) {
+No differences found.
-Differences found at line 118.
-	cell_rise(del_1_7_7) {
-        cell_rise(del_1_7_7) {
-Differences found at line 70.
-	cell_rise(TIMING_DELAY_7x7ds1) {
-        cell_rise(TIMING_DELAY_7x7ds1) {
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
@@ -17,18 +11,10 @@ Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
-Differences found at line 83.
+No differences found.
-	cell_rise(delay_template_7x7_x1) {
+No differences found.
-        cell_rise(delay_template_7x7_x1) {
+No differences found.
-Differences found at line 81.
+No differences found.
-	cell_rise(delay_template_7x7) {
-        cell_rise(delay_template_7x7) {
-Differences found at line 83.
-	cell_rise(delay_template_7x7_x1) {
-        cell_rise(delay_template_7x7_x1) {
-Differences found at line 90.
-	cell_rise(fakeram7_256x32_mem_out_delay_template) {
-        cell_rise(fakeram7_256x32_mem_out_delay_template) {
 Warning 1171: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13156, timing group from output port.
 Warning 1212: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz line 13189, timing group from output port.

liberty/test/liberty_writer_roundtrip.ok

@@ -1,9 +1,5 @@
-Differences found at line 107.
+No differences found.
-	cell_rise(Timing_7_7) {
+No differences found.
-        cell_rise(Timing_7_7) {
-Differences found at line 118.
-	cell_rise(del_1_7_7) {
-        cell_rise(del_1_7_7) {
 INV_X1: 1 arc sets
   rise->fall
   fall->rise

sdc/test/sdc_filter_query.ok

@@ -30,6 +30,4 @@ filter_pins direction == input: 1
 filter_nets full_name =~ n*: 7
 No differences found.
 remove_constraints: skipped (API removed)
-Differences found at line 10.
+No differences found.
-set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
-create_clock -name vclk -period 5.0000 

sdc/test/sdc_filter_query2.sdcok

@@ -7,11 +7,23 @@ current_design sdc_test2
 ###############################################################################
 create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
 create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
+create_clock -name vclk -period 5.0000 
 set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
+set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in2}]
+set_input_delay 2.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
 set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
+set_output_delay 3.0000 -clock [get_clocks {clk2}] -add_delay [get_ports {out2}]
+group_path -name grp_reg2reg\
+    -from [get_clocks {clk1}]\
+    -to [get_clocks {clk1}]
+group_path -name grp_io\
+    -from [list [get_ports {in1}]\
+           [get_ports {in2}]]\
+    -to [get_ports {out1}]
 ###############################################################################
 # Environment
 ###############################################################################
+set_logic_zero [get_ports {in3}]
 ###############################################################################
 # Design Rules
 ###############################################################################

util/test/util_log_large.txtok

@@ -54,7 +54,6 @@ Path Type: min
           -0.05   slack (VIOLATED)
 
 
-Warning: util_report_string_log.tcl line 1, unknown field nets.
 Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
 Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk

util/test/util_report_string_log.ok

@@ -310,9 +310,7 @@ Path Type: max
  current 1mA
  power 1nW
  distance 1um
-Differences found at line 57.
+No differences found.
-Warning: util_report_string_log.tcl line 1, unknown field nets.
-Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
 --- Test 2: log + redirect simultaneous ---
 No differences found.
 No differences found.