One-to-one mismatched widths: partial timing arc creation

liberty/LibertyReader.cc

@@ -2402,11 +2402,28 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
   else {
     // bus -> bus
     if (timing->isOneToOne()) {
-      if (static_cast<int>(from_port_iter.size()) == to_port->size()) {
+      int from_size = from_port_iter.size();
-	LibertyPortMemberIterator to_iter(to_port);
+      int to_size = to_port->size();
-	while (from_port_iter.hasNext() && to_iter.hasNext()) {
+      LibertyPortMemberIterator to_port_iter(to_port);
+      // warn about different sizes
+      if (from_size != to_size)
+	libWarn(1216, timing->line(),
+		"timing port %s and related port %s are different sizes.",
+		from_port_name,
+		to_port->name());
+      // align to/from iterators for one-to-one mapping
+      while (from_size > to_size) {
+	from_size--;
+	from_port_iter.next();
+      }
+      while (to_size > from_size) {
+	to_size--;
+	to_port_iter.next();
+      }
+      // make timing arcs
+      while (from_port_iter.hasNext() && to_port_iter.hasNext()) {
 	LibertyPort *from_port_bit = from_port_iter.next();
-	  LibertyPort *to_port_bit = to_iter.next();
+	LibertyPort *to_port_bit = to_port_iter.next();
 	if (from_port_bit->direction()->isOutput())
 	  libWarn(1215, timing->line(), "timing group from output port.");
 	builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit,
@@ -2414,12 +2431,6 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
 				timing->line());
       }
     }
-      else
-	libWarn(1216, timing->line(),
-		"timing port %s and related port %s are different sizes.",
-		from_port_name,
-		to_port->name());
-    }
     else {
       while (from_port_iter.hasNext()) {
 	LibertyPort *from_port_bit = from_port_iter.next();

test/one2one.lib

@@ -0,0 +1,133 @@
+library (one_to_one_mismatched_width_test) {
+  delay_model : "table_lookup";
+  simulation : false;
+  capacitive_load_unit (1,pF);
+  leakage_power_unit : "1pW";
+  current_unit : "1A";
+  pulling_resistance_unit : "1kohm";
+  time_unit : "1ns";
+  voltage_unit : "1v";
+  library_features : "report_delay_calculation";
+  input_threshold_pct_rise : 50;
+  input_threshold_pct_fall : 50;
+  output_threshold_pct_rise : 50;
+  output_threshold_pct_fall : 50;
+  slew_lower_threshold_pct_rise : 30;
+  slew_lower_threshold_pct_fall : 30;
+  slew_upper_threshold_pct_rise : 70;
+  slew_upper_threshold_pct_fall : 70;
+  slew_derate_from_library : 1.0;
+  nom_process : 1.0;
+  nom_temperature : 85.0;
+  nom_voltage : 0.75;
+  type (bus20) {
+    base_type : "array";
+    data_type : "bit";
+    bit_width : 20;
+    bit_from : 19;
+    bit_to : 0;
+  }
+  type (bus32) {
+    base_type : "array";
+    data_type : "bit";
+    bit_width : 32;
+    bit_from : 31;
+    bit_to : 0;
+  }
+
+  cell (or_32_to_20) {
+    bus (A) {
+      capacitance : 1;
+      bus_type : "bus32";
+      direction : "input";
+    }
+    bus (B) {
+      capacitance : 1;
+      bus_type : "bus32";
+      direction : "input";
+    }
+    bus (Y) {
+      function : "A | B";
+      bus_type : "bus20";
+      direction : "output";
+      timing () {
+        related_pin : "A";
+        cell_rise (scalar) {
+          values ("1");
+        }
+        cell_fall (scalar) {
+          values ("1");
+        }
+        rise_transition (scalar) {
+          values ("1");
+        }
+        fall_transition (scalar) {
+          values ("1");
+        }
+      }
+      timing () {
+        related_pin : "B";
+        cell_rise (scalar) {
+          values ("1");
+        }
+        cell_fall (scalar) {
+          values ("1");
+        }
+        rise_transition (scalar) {
+          values ("1");
+        }
+        fall_transition (scalar) {
+          values ("1");
+        }
+      }
+    }
+  }
+
+  cell (or_20_to_32) {
+    bus (A) {
+      capacitance : 1;
+      bus_type : "bus20";
+      direction : "input";
+    }
+    bus (B) {
+      capacitance : 1;
+      bus_type : "bus20";
+      direction : "input";
+    }
+    bus (Y) {
+      function : "A | B";
+      bus_type : "bus32";
+      direction : "output";
+      timing () {
+        related_pin : "A";
+        cell_rise (scalar) {
+          values ("1");
+        }
+        cell_fall (scalar) {
+          values ("1");
+        }
+        rise_transition (scalar) {
+          values ("1");
+        }
+        fall_transition (scalar) {
+          values ("1");
+        }
+      }
+      timing () {
+        related_pin : "B";
+        cell_rise (scalar) {
+          values ("1");
+        }
+        cell_fall (scalar) {
+          values ("1");
+        }
+        rise_transition (scalar) {
+          values ("1");
+        }
+        fall_transition (scalar) {
+          values ("1");
+        }
+      }
+    }
+  }
+}

test/one2one.ok

@@ -0,0 +1,168 @@
+Warning: one2one.lib line 53, timing port A and related port Y are different sizes.
+Warning: one2one.lib line 68, timing port B and related port Y are different sizes.
+Warning: one2one.lib line 101, timing port A and related port Y are different sizes.
+Warning: one2one.lib line 116, timing port B and related port Y are different sizes.
+TEST 1:
+Startpoint: a[0] (input port clocked by clk)
+Endpoint: y[0] (output port clocked by clk)
+Path Group: clk
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 v input external delay
+   0.00    0.00 v a[0] (in)
+   1.00    1.00 ^ partial_wide_or_cell/Y[0] (or_32_to_20)
+   0.00    1.00 ^ y[0] (out)
+           1.00   data arrival time
+
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00   clock reconvergence pessimism
+   0.00    0.00   output external delay
+           0.00   data required time
+---------------------------------------------------------
+           0.00   data required time
+          -1.00   data arrival time
+---------------------------------------------------------
+          -1.00   slack (VIOLATED)
+
+
+Startpoint: a[10] (input port clocked by clk)
+Endpoint: y[10] (output port clocked by clk)
+Path Group: clk
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 v input external delay
+   0.00    0.00 v a[10] (in)
+   1.00    1.00 ^ partial_wide_or_cell/Y[10] (or_32_to_20)
+   0.00    1.00 ^ y[10] (out)
+           1.00   data arrival time
+
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00   clock reconvergence pessimism
+   0.00    0.00   output external delay
+           0.00   data required time
+---------------------------------------------------------
+           0.00   data required time
+          -1.00   data arrival time
+---------------------------------------------------------
+          -1.00   slack (VIOLATED)
+
+
+Startpoint: a[11] (input port clocked by clk)
+Endpoint: y[11] (output port clocked by clk)
+Path Group: clk
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 v input external delay
+   0.00    0.00 v a[11] (in)
+   1.00    1.00 ^ partial_wide_or_cell/Y[11] (or_32_to_20)
+   0.00    1.00 ^ y[11] (out)
+           1.00   data arrival time
+
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00   clock reconvergence pessimism
+   0.00    0.00   output external delay
+           0.00   data required time
+---------------------------------------------------------
+           0.00   data required time
+          -1.00   data arrival time
+---------------------------------------------------------
+          -1.00   slack (VIOLATED)
+
+
+TEST 2:
+Startpoint: a[0] (input port clocked by clk)
+Endpoint: y[0] (output port clocked by clk)
+Path Group: clk
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 v input external delay
+   0.00    0.00 v a[0] (in)
+   1.00    1.00 ^ wide_or_cell/Y[0] (or_20_to_32)
+   0.00    1.00 ^ y[0] (out)
+           1.00   data arrival time
+
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00   clock reconvergence pessimism
+   0.00    0.00   output external delay
+           0.00   data required time
+---------------------------------------------------------
+           0.00   data required time
+          -1.00   data arrival time
+---------------------------------------------------------
+          -1.00   slack (VIOLATED)
+
+
+Startpoint: a[10] (input port clocked by clk)
+Endpoint: y[10] (output port clocked by clk)
+Path Group: clk
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 v input external delay
+   0.00    0.00 v a[10] (in)
+   1.00    1.00 ^ wide_or_cell/Y[10] (or_20_to_32)
+   0.00    1.00 ^ y[10] (out)
+           1.00   data arrival time
+
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00   clock reconvergence pessimism
+   0.00    0.00   output external delay
+           0.00   data required time
+---------------------------------------------------------
+           0.00   data required time
+          -1.00   data arrival time
+---------------------------------------------------------
+          -1.00   slack (VIOLATED)
+
+
+Startpoint: a[11] (input port clocked by clk)
+Endpoint: y[11] (output port clocked by clk)
+Path Group: clk
+Path Type: max
+
+  Delay    Time   Description
+---------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 v input external delay
+   0.00    0.00 v a[11] (in)
+   1.00    1.00 ^ wide_or_cell/Y[11] (or_20_to_32)
+   0.00    1.00 ^ y[11] (out)
+           1.00   data arrival time
+
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00   clock reconvergence pessimism
+   0.00    0.00   output external delay
+           0.00   data required time
+---------------------------------------------------------
+           0.00   data required time
+          -1.00   data arrival time
+---------------------------------------------------------
+          -1.00   slack (VIOLATED)
+
+

test/one2one.tcl

@@ -0,0 +1,17 @@
+read_liberty one2one.lib
+
+puts "TEST 1:"
+read_verilog one2one_test1.v
+link_design one2one_test1
+create_clock -name clk -period 0
+set_input_delay -clock clk 0 [all_inputs]
+set_output_delay -clock clk 0 [all_outputs]
+report_checks -group_count 3
+
+puts "TEST 2:"
+read_verilog one2one_test2.v
+link_design one2one_test2
+create_clock -name clk -period 0
+set_input_delay -clock clk 0 [all_inputs]
+set_output_delay -clock clk 0 [all_outputs]
+report_checks -group_count 3

test/one2one_test1.v

@@ -0,0 +1,14 @@
+// Liberty file test: one-to-one mapping with mismatched bit widths
+// Should generate warning but still create timing arcs between bits with same index
+module one2one_test1 (
+  input wire [31:0] a,
+  output wire [19:0] y
+);
+
+  or_32_to_20 partial_wide_or_cell (
+    .A(a),
+    .B(32'b0),
+    .Y(y)
+  );
+
+endmodule

test/one2one_test2.v

@@ -0,0 +1,14 @@
+// Liberty file test: one-to-one mapping with mismatched bit widths
+// Should generate warning but still create timing arcs between bits with same index
+module one2one_test2 (
+  input wire [19:0] a,
+  output wire [31:0] y
+);
+
+  or_20_to_32 partial_wide_or_cell (
+    .A(a),
+    .B(20'b0),
+    .Y(y)
+  );
+
+endmodule

test/regression_vars.tcl

@@ -124,6 +124,7 @@ record_example_tests {
 record_sta_tests {
   prima3
   verilog_attribute
+  one2one
 }
 
 define_test_group fast [group_tests all]