Follow testing guidelines and specify unateness

test/get_filter.tcl

@@ -1,3 +1,5 @@
+# Test get_* -filter
+
 # Read in design and libraries
 read_liberty asap7_small.lib.gz
 read_verilog reg1_asap7.v

test/liberty_arcs_one2one.ok

@@ -1,60 +0,0 @@
-Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes.
-Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes.
-TEST 1:
-report_edges -from partial_wide_inv_cell/A[0]
-A[0] -> Y[0] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -from partial_wide_inv_cell/A[1]
-A[1] -> Y[1] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -from partial_wide_inv_cell/A[2]
-A[2] -> Y[2] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -from partial_wide_inv_cell/A[3]
-A[3] -> Y[3] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -from partial_wide_inv_cell/A[4]
-report_edges -from partial_wide_inv_cell/A[5]
-report_edges -from partial_wide_inv_cell/A[6]
-report_edges -from partial_wide_inv_cell/A[7]
-TEST 2:
-report_edges -to partial_wide_inv_cell/Y[0]
-A[0] -> Y[0] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -to partial_wide_inv_cell/Y[1]
-A[1] -> Y[1] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -to partial_wide_inv_cell/Y[2]
-A[2] -> Y[2] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -to partial_wide_inv_cell/Y[3]
-A[3] -> Y[3] combinational
-  v -> v 1.00:1.00
-  ^ -> v 1.00:1.00
-  ^ -> ^ 1.00:1.00
-  v -> ^ 1.00:1.00
-report_edges -to partial_wide_inv_cell/Y[4]
-report_edges -to partial_wide_inv_cell/Y[5]
-report_edges -to partial_wide_inv_cell/Y[6]
-report_edges -to partial_wide_inv_cell/Y[7]

test/liberty_arcs_one2one.tcl

@@ -1,23 +0,0 @@
-read_liberty liberty_arcs_one2one.lib
-
-puts "TEST 1:"
-read_verilog liberty_arcs_one2one_1.v
-link_design liberty_arcs_one2one_1
-create_clock -name clk -period 0
-set_input_delay -clock clk 0 [all_inputs]
-set_output_delay -clock clk 0 [all_outputs]
-for {set i 0} {$i < 8} {incr i} {
-    puts "report_edges -from partial_wide_inv_cell/A[$i]"
-    report_edges -from partial_wide_inv_cell/A[$i]
-}
-
-puts "TEST 2:"
-read_verilog liberty_arcs_one2one_2.v
-link_design liberty_arcs_one2one_2
-create_clock -name clk -period 0
-set_input_delay -clock clk 0 [all_inputs]
-set_output_delay -clock clk 0 [all_outputs]
-for {set i 0} {$i < 8} {incr i} {
-    puts "report_edges -to partial_wide_inv_cell/Y[$i]"
-    report_edges -to partial_wide_inv_cell/Y[$i]
-}

test/liberty_arcs_one2one_1.lib

@@ -1,4 +1,4 @@
-library (one_to_one_mismatched_width) {
+library (liberty_arcs_one2one_1) {
   delay_model : "table_lookup";
   simulation : false;
   capacitive_load_unit (1,pF);
@@ -47,34 +47,7 @@ library (one_to_one_mismatched_width) {
       direction : "output";
       timing () {
         related_pin : "A";
-        cell_rise (scalar) {
+	timing_sense : "negative_unate";
-          values ("1");
-        }
-        cell_fall (scalar) {
-          values ("1");
-        }
-        rise_transition (scalar) {
-          values ("1");
-        }
-        fall_transition (scalar) {
-          values ("1");
-        }
-      }
-    }
-  }
-
-  cell (inv_4_to_8) {
-    bus (A) {
-      capacitance : 1;
-      bus_type : "bus4";
-      direction : "input";
-    }
-    bus (Y) {
-      function : "!A";
-      bus_type : "bus8";
-      direction : "output";
-      timing () {
-        related_pin : "A";
         cell_rise (scalar) {
           values ("1");
         }

test/liberty_arcs_one2one_1.ok

@@ -0,0 +1,21 @@
+Warning: liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
+report_edges -from partial_wide_inv_cell/A[0]
+A[0] -> Y[0] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[1]
+A[1] -> Y[1] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[2]
+A[2] -> Y[2] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[3]
+A[3] -> Y[3] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -from partial_wide_inv_cell/A[4]
+report_edges -from partial_wide_inv_cell/A[5]
+report_edges -from partial_wide_inv_cell/A[6]
+report_edges -from partial_wide_inv_cell/A[7]

test/liberty_arcs_one2one_1.tcl

@@ -0,0 +1,11 @@
+# Test one-to-one functionality with mismatched widths where A width (8) is larger than Y width (4)
+read_liberty liberty_arcs_one2one_1.lib
+read_verilog liberty_arcs_one2one_1.v
+link_design liberty_arcs_one2one_1
+create_clock -name clk -period 0
+set_input_delay -clock clk 0 [all_inputs]
+set_output_delay -clock clk 0 [all_outputs]
+for {set i 0} {$i < 8} {incr i} {
+    puts "report_edges -from partial_wide_inv_cell/A[$i]"
+    report_edges -from partial_wide_inv_cell/A[$i]
+}

test/liberty_arcs_one2one_2.lib

@@ -0,0 +1,66 @@
+library (liberty_arcs_one2one_2) {
+  delay_model : "table_lookup";
+  simulation : false;
+  capacitive_load_unit (1,pF);
+  leakage_power_unit : "1pW";
+  current_unit : "1A";
+  pulling_resistance_unit : "1kohm";
+  time_unit : "1ns";
+  voltage_unit : "1v";
+  library_features : "report_delay_calculation";
+  input_threshold_pct_rise : 50;
+  input_threshold_pct_fall : 50;
+  output_threshold_pct_rise : 50;
+  output_threshold_pct_fall : 50;
+  slew_lower_threshold_pct_rise : 30;
+  slew_lower_threshold_pct_fall : 30;
+  slew_upper_threshold_pct_rise : 70;
+  slew_upper_threshold_pct_fall : 70;
+  slew_derate_from_library : 1.0;
+  nom_process : 1.0;
+  nom_temperature : 85.0;
+  nom_voltage : 0.75;
+  type (bus8) {
+    base_type : "array";
+    data_type : "bit";
+    bit_width : 8;
+    bit_from : 7;
+    bit_to : 0;
+  }
+  type (bus4) {
+    base_type : "array";
+    data_type : "bit";
+    bit_width : 4;
+    bit_from : 3;
+    bit_to : 0;
+  }
+
+  cell (inv_4_to_8) {
+    bus (A) {
+      capacitance : 1;
+      bus_type : "bus4";
+      direction : "input";
+    }
+    bus (Y) {
+      function : "!A";
+      bus_type : "bus8";
+      direction : "output";
+      timing () {
+        related_pin : "A";
+	timing_sense : "negative_unate";
+        cell_rise (scalar) {
+          values ("1");
+        }
+        cell_fall (scalar) {
+          values ("1");
+        }
+        rise_transition (scalar) {
+          values ("1");
+        }
+        fall_transition (scalar) {
+          values ("1");
+        }
+      }
+    }
+  }
+}

test/liberty_arcs_one2one_2.ok

@@ -0,0 +1,21 @@
+Warning: liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.
+report_edges -to partial_wide_inv_cell/Y[0]
+A[0] -> Y[0] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[1]
+A[1] -> Y[1] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[2]
+A[2] -> Y[2] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[3]
+A[3] -> Y[3] combinational
+  ^ -> v 1.00:1.00
+  v -> ^ 1.00:1.00
+report_edges -to partial_wide_inv_cell/Y[4]
+report_edges -to partial_wide_inv_cell/Y[5]
+report_edges -to partial_wide_inv_cell/Y[6]
+report_edges -to partial_wide_inv_cell/Y[7]

test/liberty_arcs_one2one_2.tcl

@@ -0,0 +1,11 @@
+# Test one-to-one functionality with mismatched widths where Y width (8) is larger than A width (4)
+read_liberty liberty_arcs_one2one_2.lib
+read_verilog liberty_arcs_one2one_2.v
+link_design liberty_arcs_one2one_2
+create_clock -name clk -period 0
+set_input_delay -clock clk 0 [all_inputs]
+set_output_delay -clock clk 0 [all_outputs]
+for {set i 0} {$i < 8} {incr i} {
+    puts "report_edges -to partial_wide_inv_cell/Y[$i]"
+    report_edges -to partial_wide_inv_cell/Y[$i]
+}

test/regression_vars.tcl

@@ -124,7 +124,8 @@ record_example_tests {
 record_sta_tests {
   prima3
   verilog_attribute
-  liberty_arcs_one2one
+  liberty_arcs_one2one_1
+  liberty_arcs_one2one_2
   get_filter
 }
 

test/verilog_attribute.tcl

@@ -1,3 +1,4 @@
+# Tests whether Verilog attributes can be parsed and retrieved correctly
 read_liberty ../examples/sky130hd_tt.lib
 read_verilog verilog_attribute.v
 link_design counter