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write_timing_model seg fault 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2023-10-09 19:28:18 -07:00
parent 3a892bf894
commit 4da3eb9099
1 changed files with 2 additions and 2 deletions
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4
search/MakeTimingModel.cc
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@ -515,14 +515,14 @@ MakeTimingModel::findClkInsertionDelays()
{
Instance *top_inst = network_->topInstance();
Cell *top_cell = network_->cell(top_inst);
CellPortIterator *port_iter = network_->portIterator(top_cell);
CellPortIterator *port_iter = network_->portBitIterator(top_cell);
while (port_iter->hasNext()) {
Port *port = port_iter->next();
if (network_->direction(port)->isInput()) {
const char *port_name = network_->name(port);
LibertyPort *lib_port = cell_->findLibertyPort(port_name);
Pin *pin = network_->findPin(top_inst, port);
if (sdc_->isClock(pin)) {
if (pin && sdc_->isClock(pin)) {
lib_port->setIsClock(true);
ClockSet *clks = sdc_->findClocks(pin);
size_t clk_count = clks->size();