Merge branch 'master' into feature-20260405-init-tcl
This commit is contained in:
Matt Liberty
GitHub
commit
46622306ba
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@ -30,3 +30,7 @@ doc/messages.txt
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# clangd turds
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.cache/
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# test artifacts
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*/test/*.log
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Testing/
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@ -1467,15 +1467,14 @@ TEST_F(ArcDcalcResultTest, CopyResult) {
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EXPECT_FLOAT_EQ(delayAsFloat(copy.loadSlew(1)), 6e-12f);
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}
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// Test ArcDcalcArg assignment
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TEST_F(ArcDcalcArgTest, Assignment) {
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// Test ArcDcalcArg copy construction with alternate values
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TEST_F(ArcDcalcArgTest, CopyConstructionAltValues) {
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ArcDcalcArg arg;
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arg.setLoadCap(3.5e-12f);
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arg.setInputDelay(1.5e-9f);
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arg.setInSlew(200e-12f);
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ArcDcalcArg other;
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other = arg;
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ArcDcalcArg other(arg);
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EXPECT_FLOAT_EQ(other.loadCap(), 3.5e-12f);
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EXPECT_FLOAT_EQ(other.inputDelay(), 1.5e-9f);
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EXPECT_FLOAT_EQ(other.inSlewFlt(), 200e-12f);
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@ -2829,14 +2828,13 @@ TEST_F(ArcDcalcArgTest, InputDelayConstructorZero) {
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EXPECT_FLOAT_EQ(arg.inputDelay(), 0.0f);
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}
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TEST_F(ArcDcalcArgTest, CopyAssignment) {
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TEST_F(ArcDcalcArgTest, CopyConstructionAltValues2) {
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ArcDcalcArg arg;
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arg.setLoadCap(3.0e-12f);
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arg.setInputDelay(2.0e-9f);
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arg.setInSlew(75e-12f);
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ArcDcalcArg copy;
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copy = arg;
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ArcDcalcArg copy(arg);
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EXPECT_FLOAT_EQ(copy.loadCap(), 3.0e-12f);
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EXPECT_FLOAT_EQ(copy.inputDelay(), 2.0e-9f);
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EXPECT_FLOAT_EQ(copy.inSlewFlt(), 75e-12f);
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@ -16,8 +16,8 @@ elif [[ "$OSTYPE" == "darwin"* ]]; then
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numThreads=$(sysctl -n hw.ncpu)
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else
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cat << EOF
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WARNING: Unsupported OSTYPE: cannot determine number of host CPUs"
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Defaulting to 2 threads. Use -threads=N to use N threads"
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WARNING: Unsupported OSTYPE: cannot determine number of host CPUs
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Defaulting to 2 threads. Use -threads=N to use N threads
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EOF
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numThreads=2
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fi
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@ -5,7 +5,6 @@ sta_module_tests("graph"
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delay_corners
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delete_modify
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incremental
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make_verify
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modify
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operations
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timing_edges
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@ -68,7 +68,6 @@ No paths found.
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No paths found.
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No paths found.
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--- Test 3: report with fields ---
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Warning 168: graph_bidirect.tcl line 1, unknown field nets.
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Startpoint: d1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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@ -80,12 +79,16 @@ Fanout Cap Slew Delay Time Description
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 0.88 0.10 0.00 0.00 v d1 (in)
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d1 (net)
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0.10 0.00 0.00 v buf1/A (BUF_X1)
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2 1.67 0.01 0.06 0.06 v buf1/Z (BUF_X1)
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n1 (net)
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0.01 0.00 0.06 v or1/A1 (OR2_X1)
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2 1.96 0.01 0.05 0.10 v or1/ZN (OR2_X1)
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n6 (net)
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0.01 0.00 0.10 v and2/A2 (AND2_X1)
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1 1.06 0.01 0.03 0.13 v and2/ZN (AND2_X1)
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n9 (net)
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0.01 0.00 0.13 v reg2/D (DFF_X1)
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0.13 data arrival time
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@ -41,7 +41,7 @@ report_checks -from [get_ports d3] -to [get_ports q4]
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# Test 3: Fields that exercise graph delay/slew queries
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#---------------------------------------------------------------
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puts "--- Test 3: report with fields ---"
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report_checks -fields {slew cap input_pins nets fanout}
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report_checks -fields {slew cap input_pins net fanout}
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report_checks -format full_clock
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@ -58,7 +58,6 @@ Path Type: min
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1.03 slack (MET)
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Warning 168: graph_delete_modify.tcl line 1, unknown field nets.
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Startpoint: d2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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@ -70,12 +69,16 @@ Fanout Cap Slew Delay Time Description
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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1 0.88 0.10 0.00 1.00 v d2 (in)
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d2 (net)
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0.10 0.00 1.00 v buf2/A (BUF_X1)
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2 1.69 0.01 0.06 1.06 v buf2/Z (BUF_X1)
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n2 (net)
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0.01 0.00 1.06 v or1/A1 (OR2_X1)
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2 2.56 0.01 0.05 1.11 v or1/ZN (OR2_X1)
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n6 (net)
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0.01 0.00 1.11 v nand1/A2 (NAND2_X1)
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1 1.14 0.01 0.02 1.12 ^ nand1/ZN (NAND2_X1)
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n7 (net)
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0.01 0.00 1.12 ^ reg2/D (DFF_X1)
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1.12 data arrival time
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@ -26,7 +26,7 @@ report_checks
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report_checks -path_delay min
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report_checks -fields {slew cap input_pins nets fanout}
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report_checks -fields {slew cap input_pins net fanout}
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#---------------------------------------------------------------
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# Test 2: Add multiple instances and nets, then delete
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@ -1 +0,0 @@
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No paths found.
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@ -1,10 +0,0 @@
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# Read liberty and design, make graph, verify
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog graph_test1.v
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link_design graph_test1
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# Creating the timing graph implicitly tests graph construction
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create_clock -name clk -period 10 [get_ports clk]
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# report_checks exercises the graph
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report_checks -from [get_ports d] -to [get_ports q]
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@ -2551,7 +2551,6 @@ A2 -> ZN combinational
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^ -> ^ 0.02:0.02:0.09:0.09
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v -> v 0.02:0.02:0.16:0.16
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--- fields per corner ---
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Warning 168: graph_modify.tcl line 1, unknown field nets.
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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@ -2564,14 +2563,19 @@ Fanout Cap Slew Delay Time Description
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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1 0.91 0.10 0.00 1.00 v d1 (in)
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d1 (net)
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0.10 0.00 1.00 v buf1/A (BUF_X1)
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2 2.36 0.01 0.04 1.04 v buf1/Z (BUF_X1)
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n1 (net)
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0.01 0.00 1.04 v and1/A1 (AND2_X1)
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1 1.60 0.00 0.02 1.06 v and1/ZN (AND2_X1)
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n5 (net)
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0.00 0.00 1.06 v nand1/A1 (NAND2_X1)
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3 6.91 0.01 0.01 1.07 ^ nand1/ZN (NAND2_X1)
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n7 (net)
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0.01 0.00 1.07 ^ buf4/A (BUF_X4)
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1 0.00 0.00 0.01 1.09 ^ buf4/Z (BUF_X4)
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q3 (net)
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0.00 0.00 1.09 ^ q3 (out)
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1.09 data arrival time
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@ -2599,6 +2603,7 @@ Fanout Cap Slew Delay Time Description
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0.00 10.00 clock network delay (ideal)
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0.00 0.00 10.00 ^ reg1/CK (DFF_X1)
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1 1.16 0.00 0.05 10.05 ^ reg1/Q (DFF_X1)
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n11 (net)
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0.00 0.00 10.05 ^ reg3/D (DFF_X1)
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10.05 data arrival time
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@ -2615,7 +2620,6 @@ Fanout Cap Slew Delay Time Description
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4.93 slack (MET)
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Warning 168: graph_modify.tcl line 1, unknown field nets.
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
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@ -2628,14 +2632,19 @@ Fanout Cap Slew Delay Time Description
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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1 0.84 0.10 0.00 1.00 v d1 (in)
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d1 (net)
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0.10 0.00 1.00 v buf1/A (BUF_X1)
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2 2.20 0.02 0.14 1.14 v buf1/Z (BUF_X1)
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n1 (net)
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0.02 0.00 1.14 v and1/A1 (AND2_X1)
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1 1.45 0.02 0.09 1.23 v and1/ZN (AND2_X1)
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n5 (net)
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0.02 0.00 1.23 v nand1/A1 (NAND2_X1)
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3 6.52 0.07 0.09 1.32 ^ nand1/ZN (NAND2_X1)
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n7 (net)
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0.07 0.00 1.32 ^ buf4/A (BUF_X4)
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1 0.00 0.01 0.07 1.38 ^ buf4/Z (BUF_X4)
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q3 (net)
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0.01 0.00 1.38 ^ q3 (out)
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1.38 data arrival time
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@ -2663,6 +2672,7 @@ Fanout Cap Slew Delay Time Description
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0.00 10.00 clock network delay (ideal)
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0.00 0.00 10.00 ^ reg1/CK (DFF_X1)
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1 1.03 0.02 0.23 10.23 v reg1/Q (DFF_X1)
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n11 (net)
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0.02 0.00 10.23 v reg3/D (DFF_X1)
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10.23 data arrival time
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@ -228,9 +228,9 @@ report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
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# report_checks with fields per corner
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#---------------------------------------------------------------
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puts "--- fields per corner ---"
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report_checks -corner fast -fields {slew cap input_pins nets fanout}
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report_checks -corner fast -fields {slew cap input_pins net fanout}
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report_checks -corner slow -fields {slew cap input_pins nets fanout}
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report_checks -corner slow -fields {slew cap input_pins net fanout}
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report_checks -corner fast -format full_clock
|
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|
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@ -1784,7 +1784,6 @@ Path Type: max
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--- report_checks options ---
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Warning 168: graph_operations.tcl line 1, unknown field nets.
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Startpoint: d1 (input port clocked by clk1)
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Endpoint: q3 (output port clocked by clk1)
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Path Group: clk1
|
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|
|
@ -1796,14 +1795,19 @@ Fanout Cap Slew Delay Time Description
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
|
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1 0.88 0.10 0.00 1.00 v d1 (in)
|
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d1 (net)
|
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0.10 0.00 1.00 v buf1/A (BUF_X1)
|
||||
2 2.29 0.01 0.06 1.06 v buf1/Z (BUF_X1)
|
||||
n1 (net)
|
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0.01 0.00 1.06 v and1/A1 (AND2_X1)
|
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1 1.53 0.01 0.03 1.09 v and1/ZN (AND2_X1)
|
||||
n5 (net)
|
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0.01 0.00 1.09 v nand1/A1 (NAND2_X1)
|
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3 6.80 0.02 0.03 1.11 ^ nand1/ZN (NAND2_X1)
|
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n7 (net)
|
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0.02 0.00 1.11 ^ buf4/A (BUF_X4)
|
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1 0.00 0.00 0.02 1.13 ^ buf4/Z (BUF_X4)
|
||||
q3 (net)
|
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0.00 0.00 1.13 ^ q3 (out)
|
||||
1.13 data arrival time
|
||||
|
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|
|
@ -1830,6 +1834,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 0.00 10.00 ^ reg1/CK (DFF_X1)
|
||||
1 1.06 0.01 0.08 10.08 v reg1/Q (DFF_X1)
|
||||
n11 (net)
|
||||
0.01 0.00 10.08 v reg3/D (DFF_X1)
|
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10.08 data arrival time
|
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|
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|
|
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|
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@ -241,7 +241,7 @@ report_check_types -max_delay -min_delay -verbose
|
|||
# report_checks with various options
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks options ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
|
|
|
|||
|
|
@ -86,7 +86,9 @@ parseBusName(std::string_view name,
|
|||
if (brkt_index != std::string_view::npos) {
|
||||
char brkt_left_ch = brkts_left[brkt_index];
|
||||
size_t left = name.rfind(brkt_left_ch);
|
||||
if (left != std::string_view::npos) {
|
||||
if (left != std::string_view::npos
|
||||
&& left + 1 < len
|
||||
&& isdigit(name[left + 1])) {
|
||||
is_bus = true;
|
||||
bus_name.append(name.data(), left);
|
||||
// Simple bus subscript.
|
||||
|
|
@ -140,19 +142,21 @@ parseBusName(std::string_view name,
|
|||
if (brkt_index != std::string_view::npos) {
|
||||
char brkt_left_ch = brkts_left[brkt_index];
|
||||
size_t left = name.rfind(brkt_left_ch);
|
||||
if (left != std::string_view::npos) {
|
||||
if (left != std::string_view::npos
|
||||
&& left + 1 < len
|
||||
&& (isdigit(name[left + 1]) || name[left + 1] == '*')) {
|
||||
is_bus = true;
|
||||
bus_name.append(name.data(), left);
|
||||
// Check for bus range.
|
||||
size_t range = name.find(':', left);
|
||||
if (range != std::string_view::npos) {
|
||||
is_range = true;
|
||||
from = std::stoi(std::string(name.substr(left + 1)));
|
||||
to = std::stoi(std::string(name.substr(range + 1)));
|
||||
}
|
||||
if (name[left + 1] == '*')
|
||||
subscript_wild = true;
|
||||
else {
|
||||
if (left + 1 < len && name[left + 1] == '*')
|
||||
subscript_wild = true;
|
||||
// Check for bus range.
|
||||
size_t range = name.find(':', left);
|
||||
if (range != std::string_view::npos) {
|
||||
is_range = true;
|
||||
from = std::stoi(std::string(name.substr(left + 1)));
|
||||
to = std::stoi(std::string(name.substr(range + 1)));
|
||||
}
|
||||
else
|
||||
from = to = std::stoi(std::string(name.substr(left + 1)));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -210,7 +210,6 @@ Path Type: max
|
|||
|
||||
No paths found.
|
||||
No paths found.
|
||||
Warning 168: network_advanced.tcl line 1, unknown field nets.
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -222,10 +221,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.00 0.00 0.00 v in1 (in)
|
||||
in1 (net)
|
||||
0.00 0.00 0.00 v buf1/A (BUF_X1)
|
||||
1 0.87 0.00 0.02 0.02 v buf1/Z (BUF_X1)
|
||||
n1 (net)
|
||||
0.00 0.00 0.02 v and1/A1 (AND2_X1)
|
||||
1 1.06 0.01 0.02 0.05 v and1/ZN (AND2_X1)
|
||||
n2 (net)
|
||||
0.01 0.00 0.05 v reg1/D (DFF_X1)
|
||||
0.05 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -204,5 +204,5 @@ report_checks -from [get_ports in1] -to [get_ports out1]
|
|||
report_checks -from [get_ports in2] -to [get_ports out1]
|
||||
|
||||
# Report with various field combinations
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
report_checks -format full_clock_expanded
|
||||
|
|
|
|||
|
|
@ -239,7 +239,6 @@ Path Type: min
|
|||
|
||||
|
||||
No paths found.
|
||||
Warning 168: network_bus_parse.tcl line 1, unknown field nets.
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -251,14 +250,19 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.00 0.00 0.00 v data_a[6] (in)
|
||||
data_a[6] (net)
|
||||
0.00 0.00 0.00 v buf_a6/A (BUF_X1)
|
||||
1 0.87 0.00 0.02 0.02 v buf_a6/Z (BUF_X1)
|
||||
stage1[6] (net)
|
||||
0.00 0.00 0.02 v and6/A1 (AND2_X1)
|
||||
3 2.85 0.01 0.03 0.05 v and6/ZN (AND2_X1)
|
||||
stage2[6] (net)
|
||||
0.01 0.00 0.05 v or_carry/A2 (OR2_X1)
|
||||
1 0.88 0.01 0.05 0.10 v or_carry/ZN (OR2_X1)
|
||||
internal_carry (net)
|
||||
0.01 0.00 0.10 v buf_carry/A (BUF_X1)
|
||||
1 0.00 0.00 0.02 0.12 v buf_carry/Z (BUF_X1)
|
||||
carry (net)
|
||||
0.00 0.00 0.12 v carry (out)
|
||||
0.12 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -173,4 +173,4 @@ puts "--- timing analysis ---"
|
|||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -from [get_ports {data_a[0]}] -to [get_ports {result[0]}]
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
|
|
|||
|
|
@ -361,7 +361,6 @@ Path Type: max
|
|||
9.92 slack (MET)
|
||||
|
||||
|
||||
Warning 168: network_escaped_names.tcl line 1, unknown field nets.
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -373,10 +372,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v in1 (in)
|
||||
in1 (net)
|
||||
0.10 0.00 0.00 v buf1/A (BUF_X1)
|
||||
1 0.87 0.01 0.06 0.06 v buf1/Z (BUF_X1)
|
||||
n1 (net)
|
||||
0.01 0.00 0.06 v and1/A1 (AND2_X1)
|
||||
1 1.06 0.01 0.03 0.08 v and1/ZN (AND2_X1)
|
||||
n2 (net)
|
||||
0.01 0.00 0.08 v reg1/D (DFF_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -225,7 +225,7 @@ report_checks -rise_to [get_ports out1]
|
|||
report_checks -fall_to [get_ports out1]
|
||||
|
||||
# Various report formats
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
report_checks -format full_clock
|
||||
report_checks -format full_clock_expanded
|
||||
report_checks -digits 6
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -359,7 +359,6 @@ Path Type: max
|
|||
9.89 slack (MET)
|
||||
|
||||
|
||||
Warning 168: network_hierarchy.tcl line 1, unknown field nets.
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -371,18 +370,25 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v in1 (in)
|
||||
in1 (net)
|
||||
0.10 0.00 0.00 v buf_in/A (BUF_X1)
|
||||
1 0.87 0.01 0.06 0.06 v buf_in/Z (BUF_X1)
|
||||
w1 (net)
|
||||
0.01 0.00 0.06 v sub1/and_gate/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
|
||||
sub1/n1 (net)
|
||||
0.01 0.00 0.08 v sub1/buf_gate/A (BUF_X1)
|
||||
1 0.87 0.00 0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
|
||||
w2 (net)
|
||||
0.00 0.00 0.11 v sub2/and_gate/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
|
||||
sub2/n1 (net)
|
||||
0.01 0.00 0.13 v sub2/buf_gate/A (BUF_X1)
|
||||
2 2.42 0.01 0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
|
||||
w3 (net)
|
||||
0.01 0.00 0.16 v inv1/A (INV_X1)
|
||||
1 1.14 0.01 0.01 0.17 ^ inv1/ZN (INV_X1)
|
||||
w4 (net)
|
||||
0.01 0.00 0.17 ^ reg1/D (DFF_X1)
|
||||
0.17 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -213,7 +213,7 @@ report_checks -from [get_ports in2] -to [get_ports out1]
|
|||
|
||||
report_checks -from [get_ports in3] -to [get_ports out2]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
|
|
|
|||
|
|
@ -193,7 +193,6 @@ Path Type: max
|
|||
9.80 slack (MET)
|
||||
|
||||
|
||||
Warning 168: network_leaf_iter.tcl line 1, unknown field nets.
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -205,18 +204,25 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v in1 (in)
|
||||
in1 (net)
|
||||
0.10 0.00 0.00 v buf_in/A (BUF_X1)
|
||||
1 0.87 0.01 0.06 0.06 v buf_in/Z (BUF_X1)
|
||||
w1 (net)
|
||||
0.01 0.00 0.06 v sub1/and_gate/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
|
||||
sub1/n1 (net)
|
||||
0.01 0.00 0.08 v sub1/buf_gate/A (BUF_X1)
|
||||
1 0.87 0.00 0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
|
||||
w2 (net)
|
||||
0.00 0.00 0.11 v sub2/and_gate/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
|
||||
sub2/n1 (net)
|
||||
0.01 0.00 0.13 v sub2/buf_gate/A (BUF_X1)
|
||||
2 2.42 0.01 0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
|
||||
w3 (net)
|
||||
0.01 0.00 0.16 v inv1/A (INV_X1)
|
||||
1 1.14 0.01 0.01 0.17 ^ inv1/ZN (INV_X1)
|
||||
w4 (net)
|
||||
0.01 0.00 0.17 ^ reg1/D (DFF_X1)
|
||||
0.17 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -214,7 +214,7 @@ report_checks -path_delay min
|
|||
report_checks -path_delay max
|
||||
|
||||
# Detailed reports with various fields
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
report_checks -format full_clock
|
||||
report_checks -format full_clock_expanded
|
||||
|
||||
|
|
|
|||
|
|
@ -242,7 +242,6 @@ Path Type: min
|
|||
-5.33 slack (VIOLATED)
|
||||
|
||||
|
||||
Warning 168: network_properties.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -254,10 +253,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 0.58 6.09 45.31 45.31 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
6.09 0.00 45.31 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 0.57 5.15 11.76 57.08 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
5.15 0.00 57.08 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 0.62 6.96 14.88 71.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
6.96 0.00 71.95 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
71.95 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -190,4 +190,4 @@ puts "all_registers -output_pins: [llength $reg_output]"
|
|||
puts "--- timing analysis ---"
|
||||
report_checks
|
||||
report_checks -path_delay min
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
|
|
|||
|
|
@ -216,7 +216,6 @@ Path Type: max
|
|||
6.82 slack (MET)
|
||||
|
||||
|
||||
Warning 168: network_sdc_pattern_deep.tcl line 1, unknown field nets.
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: out2 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -228,18 +227,25 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
1 0.88 0.10 0.00 1.00 v in1 (in)
|
||||
in1 (net)
|
||||
0.10 0.00 1.00 v buf_in/A (BUF_X1)
|
||||
1 0.87 0.01 0.06 1.06 v buf_in/Z (BUF_X1)
|
||||
w1 (net)
|
||||
0.01 0.00 1.06 v sub1/and_gate/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.03 1.08 v sub1/and_gate/ZN (AND2_X1)
|
||||
sub1/n1 (net)
|
||||
0.01 0.00 1.08 v sub1/buf_gate/A (BUF_X1)
|
||||
1 0.87 0.00 0.02 1.11 v sub1/buf_gate/Z (BUF_X1)
|
||||
w2 (net)
|
||||
0.00 0.00 1.11 v sub2/and_gate/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.02 1.13 v sub2/and_gate/ZN (AND2_X1)
|
||||
sub2/n1 (net)
|
||||
0.01 0.00 1.13 v sub2/buf_gate/A (BUF_X1)
|
||||
2 2.42 0.01 0.03 1.16 v sub2/buf_gate/Z (BUF_X1)
|
||||
w3 (net)
|
||||
0.01 0.00 1.16 v buf_out2/A (BUF_X1)
|
||||
1 0.00 0.00 0.02 1.18 v buf_out2/Z (BUF_X1)
|
||||
out2 (net)
|
||||
0.00 0.00 1.18 v out2 (out)
|
||||
1.18 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ report_checks -to [get_ports out1]
|
|||
report_checks -to [get_ports out2]
|
||||
|
||||
# Fields
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
|
|
|
|||
|
|
@ -448,7 +448,6 @@ Path Type: max
|
|||
9.88 slack (MET)
|
||||
|
||||
|
||||
Warning 168: network_sdc_query.tcl line 1, unknown field nets.
|
||||
Startpoint: data_a[6] (input port clocked by clk)
|
||||
Endpoint: carry (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -460,14 +459,19 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v data_a[6] (in)
|
||||
data_a[6] (net)
|
||||
0.10 0.00 0.00 v buf_a6/A (BUF_X1)
|
||||
1 0.87 0.01 0.06 0.06 v buf_a6/Z (BUF_X1)
|
||||
stage1[6] (net)
|
||||
0.01 0.00 0.06 v and6/A1 (AND2_X1)
|
||||
3 2.85 0.01 0.03 0.09 v and6/ZN (AND2_X1)
|
||||
stage2[6] (net)
|
||||
0.01 0.00 0.09 v or_carry/A2 (OR2_X1)
|
||||
1 0.88 0.01 0.05 0.13 v or_carry/ZN (OR2_X1)
|
||||
internal_carry (net)
|
||||
0.01 0.00 0.13 v buf_carry/A (BUF_X1)
|
||||
1 0.00 0.00 0.02 0.16 v buf_carry/Z (BUF_X1)
|
||||
carry (net)
|
||||
0.00 0.00 0.16 v carry (out)
|
||||
0.16 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -279,7 +279,7 @@ report_checks -from [get_ports {data_a[7]}] -to [get_ports carry]
|
|||
|
||||
report_checks -from [get_ports {data_b[6]}] -to [get_ports overflow]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -endpoint_count 5
|
||||
|
||||
|
|
|
|||
|
|
@ -68,7 +68,6 @@ buf1 pins: 2
|
|||
and1 pins: 3
|
||||
reg1 pins: 6
|
||||
--- timing report sorting ---
|
||||
Warning 168: network_sorting.tcl line 1, unknown field nets.
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -80,10 +79,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 10.00 0.00 0.00 v in1 (in)
|
||||
in1 (net)
|
||||
10.00 0.00 0.00 v buf1/A (BUF_X1)
|
||||
1 0.87 0.32 2.03 2.03 v buf1/Z (BUF_X1)
|
||||
n1 (net)
|
||||
0.32 0.00 2.03 v and1/A1 (AND2_X1)
|
||||
1 1.06 0.30 0.10 2.13 v and1/ZN (AND2_X1)
|
||||
n2 (net)
|
||||
0.30 0.00 2.13 v reg1/D (DFF_X1)
|
||||
2.13 data arrival time
|
||||
|
||||
|
|
@ -100,7 +102,6 @@ Fanout Cap Slew Delay Time Description
|
|||
7.74 slack (MET)
|
||||
|
||||
|
||||
Warning 168: network_sorting.tcl line 1, unknown field nets.
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -112,10 +113,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
1 0.97 10.00 0.00 0.00 ^ in1 (in)
|
||||
in1 (net)
|
||||
10.00 0.00 0.00 ^ buf1/A (BUF_X1)
|
||||
1 0.92 0.31 -0.18 -0.18 ^ buf1/Z (BUF_X1)
|
||||
n1 (net)
|
||||
0.31 0.00 -0.18 ^ and1/A1 (AND2_X1)
|
||||
1 1.14 0.02 0.06 -0.12 ^ and1/ZN (AND2_X1)
|
||||
n2 (net)
|
||||
0.02 0.00 -0.12 ^ reg1/D (DFF_X1)
|
||||
-0.12 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -86,8 +86,8 @@ puts "reg1 pins: [llength $reg_pins]"
|
|||
# sorting in report paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- timing report sorting ---"
|
||||
report_checks -path_delay max -fields {slew cap input_pins nets fanout}
|
||||
report_checks -path_delay min -fields {slew cap input_pins nets fanout}
|
||||
report_checks -path_delay max -fields {slew cap input_pins net fanout}
|
||||
report_checks -path_delay min -fields {slew cap input_pins net fanout}
|
||||
report_checks -sort_by_slack
|
||||
report_checks -group_path_count 5
|
||||
|
||||
|
|
|
|||
|
|
@ -94,7 +94,6 @@ Path Type: min
|
|||
|
||||
No paths found.
|
||||
No paths found.
|
||||
Warning 168: parasitics_annotation_query.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -106,10 +105,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 0.58 6.10 48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
6.10 0.00 48.40 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 0.57 5.15 11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
5.15 0.00 60.17 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 0.62 6.96 14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
6.96 0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
|
|
@ -217,7 +219,6 @@ elmore u1/Y->u2/A after SPEF: 0.0
|
|||
elmore r1/Q->u1/A after SPEF: 0.0
|
||||
elmore r3/Q->out after SPEF: 1.6213998893510606e-11
|
||||
--- Test 8: detailed reports ---
|
||||
Warning 168: parasitics_annotation_query.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -229,10 +230,13 @@ Fanout Cap Slew Delay Time Description
|
|||
12.11 12.11 clock network delay (propagated)
|
||||
48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -123,7 +123,7 @@ report_checks -from [get_ports in1] -to [get_ports out]
|
|||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Report parasitic annotation
|
||||
|
|
@ -206,7 +206,7 @@ puts "elmore r3/Q->out after SPEF: $elm_r3_spef"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 8: detailed reports ---"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
|
|
|
|||
|
|
@ -152,7 +152,6 @@ Path Type: max
|
|||
|
||||
No paths found.
|
||||
No paths found.
|
||||
Warning 168: parasitics_coupling.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -164,10 +163,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 0.58 6.10 48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
6.10 0.00 48.40 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 0.57 5.15 11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
5.15 0.00 60.17 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 0.62 6.96 14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
6.96 0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ report_checks -from [get_ports in1] -to [get_ports out]
|
|||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report parasitic annotation
|
||||
|
|
|
|||
|
|
@ -72,7 +72,6 @@ Path Type: min
|
|||
-13.41 slack (VIOLATED)
|
||||
|
||||
|
||||
Warning 168: parasitics_coupling_reduce.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -84,10 +83,13 @@ Fanout Cap Slew Delay Time Description
|
|||
11.30 11.30 clock network delay (propagated)
|
||||
45.81 0.00 11.30 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 13.58 23.96 64.33 75.63 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
37.80 9.52 85.14 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 13.07 43.97 33.69 118.83 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
57.40 12.42 131.25 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 13.12 52.35 44.67 175.92 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
64.37 12.82 188.74 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
188.74 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ report_checks
|
|||
|
||||
report_checks -path_delay min
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: DMP calculators with coupling caps
|
||||
|
|
|
|||
|
|
@ -138,7 +138,6 @@ Path Type: max
|
|||
419.17 slack (MET)
|
||||
|
||||
|
||||
Warning 168: parasitics_estimate_wirerc.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -150,10 +149,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 0.58 6.10 48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
6.10 0.00 48.40 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 0.57 5.15 11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
5.15 0.00 60.17 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 0.62 6.96 14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
6.96 0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ report_checks -path_delay min
|
|||
|
||||
report_checks -path_delay max
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Try different delay calculators with these parasitics
|
||||
|
|
|
|||
|
|
@ -179,7 +179,6 @@ Path Type: max
|
|||
0.06 slack (MET)
|
||||
|
||||
|
||||
Warning 168: parasitics_gcd_spef.tcl line 1, unknown field nets.
|
||||
Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: _418_ (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -191,34 +190,49 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
|
||||
3 0.01 0.04 0.32 0.32 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
|
||||
dpath.a_lt_b$in1[0] (net)
|
||||
0.04 0.00 0.32 v _214_/B_N (sky130_fd_sc_hd__nor2b_4)
|
||||
2 0.01 0.04 0.12 0.45 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
|
||||
_052_ (net)
|
||||
0.04 0.00 0.45 v _215_/C (sky130_fd_sc_hd__maj3_2)
|
||||
2 0.01 0.07 0.32 0.77 v _215_/X (sky130_fd_sc_hd__maj3_2)
|
||||
_053_ (net)
|
||||
0.07 0.00 0.77 v _216_/C (sky130_fd_sc_hd__maj3_2)
|
||||
2 0.01 0.06 0.32 1.10 v _216_/X (sky130_fd_sc_hd__maj3_2)
|
||||
_054_ (net)
|
||||
0.06 0.00 1.10 v _217_/C (sky130_fd_sc_hd__maj3_2)
|
||||
2 0.02 0.09 0.36 1.46 v _217_/X (sky130_fd_sc_hd__maj3_2)
|
||||
_055_ (net)
|
||||
0.09 0.00 1.46 v _218_/C (sky130_fd_sc_hd__maj3_2)
|
||||
2 0.02 0.10 0.38 1.83 v _218_/X (sky130_fd_sc_hd__maj3_2)
|
||||
_056_ (net)
|
||||
0.10 0.00 1.84 v _219_/C (sky130_fd_sc_hd__maj3_2)
|
||||
3 0.03 0.12 0.39 2.23 v _219_/X (sky130_fd_sc_hd__maj3_2)
|
||||
_057_ (net)
|
||||
0.12 0.00 2.23 v _222_/A2 (sky130_fd_sc_hd__o211ai_4)
|
||||
3 0.02 0.23 0.25 2.48 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
|
||||
_060_ (net)
|
||||
0.23 0.00 2.48 ^ _225_/A3 (sky130_fd_sc_hd__a311oi_4)
|
||||
4 0.02 0.14 0.16 2.63 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
|
||||
_063_ (net)
|
||||
0.14 0.00 2.64 v _228_/A3 (sky130_fd_sc_hd__o311ai_4)
|
||||
3 0.02 0.33 0.34 2.97 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
|
||||
_066_ (net)
|
||||
0.33 0.00 2.97 ^ _231_/A3 (sky130_fd_sc_hd__a311oi_4)
|
||||
2 0.02 0.14 0.17 3.14 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
|
||||
_069_ (net)
|
||||
0.14 0.00 3.15 v _292_/A3 (sky130_fd_sc_hd__o311a_2)
|
||||
3 0.02 0.10 0.43 3.58 v _292_/X (sky130_fd_sc_hd__o311a_2)
|
||||
_110_ (net)
|
||||
0.10 0.00 3.58 v _295_/A3 (sky130_fd_sc_hd__o31ai_4)
|
||||
11 0.08 0.88 0.72 4.30 ^ _295_/Y (sky130_fd_sc_hd__o31ai_4)
|
||||
_113_ (net)
|
||||
0.88 0.00 4.30 ^ split1/A (sky130_fd_sc_hd__buf_4)
|
||||
10 0.07 0.20 0.36 4.66 ^ split1/X (sky130_fd_sc_hd__buf_4)
|
||||
net1 (net)
|
||||
0.20 0.00 4.66 ^ _316_/A2 (sky130_fd_sc_hd__a221oi_1)
|
||||
1 0.00 0.13 0.11 4.78 v _316_/Y (sky130_fd_sc_hd__a221oi_1)
|
||||
_007_ (net)
|
||||
0.13 0.00 4.78 v _418_/D (sky130_fd_sc_hd__dfxtp_1)
|
||||
4.78 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ report_checks -path_delay min
|
|||
|
||||
report_checks -path_delay max
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
|
|
|
|||
|
|
@ -67,7 +67,6 @@ Path Type: min
|
|||
|
||||
No paths found.
|
||||
No paths found.
|
||||
Warning 168: parasitics_pi_pole_residue.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -79,10 +78,13 @@ Fanout Cap Slew Delay Time Description
|
|||
12.11 12.11 clock network delay (propagated)
|
||||
48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
22.89 17.61 93.23 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 13.97 46.91 30.36 123.59 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
46.91 17.58 141.17 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 14.02 56.09 42.76 183.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
56.09 17.72 201.65 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.65 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ report_checks -from [get_ports in1] -to [get_ports out]
|
|||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Delay calc reports with two-pole model
|
||||
|
|
|
|||
|
|
@ -125,7 +125,6 @@ Path Type: min
|
|||
|
||||
No paths found.
|
||||
No paths found.
|
||||
Warning 168: parasitics_reduce_dcalc.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -137,10 +136,13 @@ Fanout Cap Slew Delay Time Description
|
|||
12.11 12.11 clock network delay (propagated)
|
||||
48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ report_checks -from [get_ports in1] -to [get_ports out]
|
|||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
# Detailed dcalc
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
|
||||
|
|
|
|||
|
|
@ -359,7 +359,6 @@ Path Type: max
|
|||
301.74 slack (MET)
|
||||
|
||||
|
||||
Warning 168: parasitics_spef_namemap.tcl line 1, unknown field nets.
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -371,10 +370,13 @@ Fanout Cap Slew Delay Time Description
|
|||
12.11 12.11 clock network delay (propagated)
|
||||
48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
1 13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
r2q (net)
|
||||
50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
1 13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
u1z (net)
|
||||
66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
1 14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
u2z (net)
|
||||
73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ report_checks -path_delay min
|
|||
|
||||
report_checks -path_delay max
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
|
||||
|
|
|
|||
|
|
@ -1094,88 +1094,5 @@ Path Type: max
|
|||
7.89 slack (MET)
|
||||
|
||||
|
||||
--- remove_constraints ---
|
||||
remove_constraints: skipped (API removed)
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: out1 (output port clocked by clk1)
|
||||
Path Group: grp1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk1 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg2/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg2/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk1 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Endpoint: out2 (output port clocked by clk2)
|
||||
Path Group: grp3
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg3/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg3/Q (DFF_X1)
|
||||
0.00 0.08 ^ out2 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
20.00 20.00 clock clk2 (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
-3.00 17.00 output external delay
|
||||
17.00 data required time
|
||||
---------------------------------------------------------
|
||||
17.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
16.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in3 (input port clocked by clk2)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk2 (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
2.00 2.00 v input external delay
|
||||
0.00 2.00 v in3 (in)
|
||||
0.05 2.05 v or1/ZN (OR2_X1)
|
||||
0.03 2.07 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 2.07 ^ reg2/D (DFF_X1)
|
||||
2.07 data arrival time
|
||||
|
||||
10.00 10.00 clock clk1 (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-2.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.89 slack (MET)
|
||||
|
||||
|
||||
--- write_sdc with exceptions ---
|
||||
--- write_sdc compatible with exceptions ---
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
# Targets: ExceptionPath.cc exception merging, priority, matches,
|
||||
# overrides, through-pin matching, ExceptionThru matching,
|
||||
# Sdc.cc addException, findException, isPathGroupName,
|
||||
# pathGroupNames, removeConstraints, constraintsChanged,
|
||||
# pathGroupNames,
|
||||
# makeExceptionFrom/Thru/To, checkExceptionFromPins,
|
||||
# checkExceptionToPins, deleteExceptionFrom/Thru/To,
|
||||
# WriteSdc.cc writeExceptions (various exception types)
|
||||
|
|
@ -115,28 +115,6 @@ puts "--- exception override: false path then max_delay ---"
|
|||
set_max_delay -from [get_ports in3] -to [get_ports out2] 5.0
|
||||
report_checks
|
||||
|
||||
# remove_constraints (remove all SDC constraints)
|
||||
puts "--- remove_constraints ---"
|
||||
# TODO: sta::remove_constraints removed from Sta API
|
||||
# sta::remove_constraints
|
||||
# report_checks
|
||||
puts "remove_constraints: skipped (API removed)"
|
||||
|
||||
# Re-add constraints for write_sdc
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in2]
|
||||
set_input_delay -clock clk2 2.0 [get_ports in3]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
set_output_delay -clock clk2 3.0 [get_ports out2]
|
||||
|
||||
set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
|
||||
set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
|
||||
set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
|
||||
group_path -name grp1 -from [get_clocks clk1]
|
||||
report_checks
|
||||
|
||||
# Write SDC with all exception types
|
||||
puts "--- write_sdc with exceptions ---"
|
||||
set sdc1 [make_result_file sdc_exception_merge1.sdc]
|
||||
|
|
|
|||
|
|
@ -29,5 +29,4 @@ filter_insts ref_name =~ BUF*: 1
|
|||
filter_pins direction == input: 1
|
||||
filter_nets full_name =~ n*: 7
|
||||
No differences found.
|
||||
remove_constraints: skipped (API removed)
|
||||
No differences found.
|
||||
|
|
|
|||
|
|
@ -4,8 +4,7 @@
|
|||
# Sdc.cc: allInputs, allOutputs, isConstrained (pin, instance, net),
|
||||
# findClocksMatching, sortedClocks, findClock,
|
||||
# isClockSrc, isClock, isIdealClock,
|
||||
# clkThruTristateEnabled, setClkThruTristateEnabled,
|
||||
# removeConstraints
|
||||
# clkThruTristateEnabled, setClkThruTristateEnabled
|
||||
# Sdc.i: all_inputs_cmd, all_outputs_cmd, filter_ports, filter_insts,
|
||||
# filter_pins, filter_clocks, filter_lib_cells, filter_lib_pins,
|
||||
# filter_liberty_libraries, filter_nets, filter_timing_arcs,
|
||||
|
|
@ -13,7 +12,7 @@
|
|||
# net_is_constrained, is_clock_src, is_clock, is_ideal_clock,
|
||||
# clk_thru_tristate_enabled, set_clk_thru_tristate_enabled,
|
||||
# find_clocks_matching, default_arrival_clock,
|
||||
# pin_case_logic_value, pin_logic_value, remove_constraints
|
||||
# pin_case_logic_value, pin_logic_value
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -179,22 +178,6 @@ diff_files sdc_filter_query1.sdcok $sdc1
|
|||
unset_case_analysis [get_ports in1]
|
||||
unset_case_analysis [get_ports in2]
|
||||
|
||||
############################################################
|
||||
# remove_constraints
|
||||
############################################################
|
||||
# TODO: sta::remove_constraints removed from Sta API
|
||||
# sta::remove_constraints
|
||||
# report_checks
|
||||
puts "remove_constraints: skipped (API removed)"
|
||||
|
||||
############################################################
|
||||
# Re-apply constraints for final write
|
||||
############################################################
|
||||
create_clock -name clk1 -period 10 [get_ports clk1]
|
||||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [get_ports in1]
|
||||
set_output_delay -clock clk1 3.0 [get_ports out1]
|
||||
|
||||
set sdc2 [make_result_file sdc_filter_query2.sdc]
|
||||
write_sdc -no_timestamp $sdc2
|
||||
diff_files sdc_filter_query2.sdcok $sdc2
|
||||
|
|
|
|||
|
|
@ -289,7 +289,6 @@ Unannotated Arcs
|
|||
width reg2/CK -> reg2/CK
|
||||
--- Test 5: write SDF ---
|
||||
--- Test 6: detailed reports ---
|
||||
Warning 168: sdf_cond_pathpulse.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -301,14 +300,19 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v d1 (in)
|
||||
d1 (net)
|
||||
0.10 0.00 0.00 v buf1/A (BUF_X1)
|
||||
1 0.87 0.01 0.14 0.14 v buf1/Z (BUF_X1)
|
||||
n1 (net)
|
||||
0.01 0.03 0.17 v and1/A1 (AND2_X1)
|
||||
1 0.90 0.01 0.13 0.30 v and1/ZN (AND2_X1)
|
||||
n3 (net)
|
||||
0.01 0.03 0.33 v or1/A2 (OR2_X1)
|
||||
2 2.59 0.01 0.10 0.43 v or1/ZN (OR2_X1)
|
||||
n4 (net)
|
||||
0.01 0.03 0.46 v nand1/A1 (NAND2_X1)
|
||||
1 1.14 0.02 0.10 0.56 ^ nand1/ZN (NAND2_X1)
|
||||
n5 (net)
|
||||
0.02 0.02 0.58 ^ reg2/D (DFF_X1)
|
||||
0.58 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -119,7 +119,7 @@ write_sdf -divider . $sdf_out4
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 6: detailed reports ---"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -digits 6
|
||||
|
||||
|
|
|
|||
|
|
@ -320,7 +320,6 @@ cell hold arcs 3 3 0
|
|||
----------------------------------------------------------------
|
||||
6 6 0
|
||||
--- Test 7: detailed reports ---
|
||||
Warning 168: sdf_device_cond.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -332,14 +331,19 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
1 0.97 0.10 0.00 0.00 ^ d1 (in)
|
||||
d1 (net)
|
||||
0.10 0.00 0.00 ^ buf1/A (BUF_X1)
|
||||
2 2.62 0.01 0.15 0.15 ^ buf1/Z (BUF_X1)
|
||||
n1 (net)
|
||||
0.01 0.03 0.18 ^ inv1/A (INV_X1)
|
||||
1 0.79 0.00 0.09 0.27 v inv1/ZN (INV_X1)
|
||||
n3 (net)
|
||||
0.00 0.02 0.29 v or1/A1 (OR2_X1)
|
||||
2 2.59 0.01 0.03 0.32 v or1/ZN (OR2_X1)
|
||||
n5 (net)
|
||||
0.01 0.03 0.35 v nand1/A1 (NAND2_X1)
|
||||
1 1.14 0.02 0.10 0.45 ^ nand1/ZN (NAND2_X1)
|
||||
n6 (net)
|
||||
0.02 0.02 0.47 ^ reg2/D (DFF_X1)
|
||||
0.47 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -121,7 +121,7 @@ report_annotated_check -setup -hold
|
|||
# Test 7: Detailed path reports
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: detailed reports ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
report_checks -format full_clock
|
||||
|
||||
|
|
|
|||
|
|
@ -2125,14 +2125,6 @@ TEST_F(StaDesignTest, EndpointPins) {
|
|||
EXPECT_GT(eps.size(), 0u);
|
||||
}
|
||||
|
||||
// --- Sta: startpointPins ---
|
||||
|
||||
TEST_F(StaDesignTest, StartpointPins) {
|
||||
// startpointPins() is declared in Sta.hh but not defined - skip
|
||||
// PinSet sps = sta_->startpointPins();
|
||||
// EXPECT_GT(sps.size(), 0u);
|
||||
}
|
||||
|
||||
// --- Search: arrivalsValid ---
|
||||
|
||||
TEST_F(StaDesignTest, SearchArrivalsValidDesign) {
|
||||
|
|
|
|||
|
|
@ -404,10 +404,6 @@ TEST_F(StaDesignTest, StaPins) {
|
|||
EXPECT_NE(pins, nullptr);
|
||||
}
|
||||
|
||||
TEST_F(StaDesignTest, StaStartpointPins) {
|
||||
// startpointPins() is declared in Sta.hh but not defined - skip
|
||||
}
|
||||
|
||||
TEST_F(StaDesignTest, StaEndpointPins) {
|
||||
PinSet endpoints = sta_->endpointPins();
|
||||
EXPECT_GE(endpoints.size(), 1u);
|
||||
|
|
|
|||
|
|
@ -748,12 +748,6 @@ TEST_F(StaInitTest, SetArcDelayCalc) {
|
|||
ASSERT_NO_THROW(sta_->setArcDelayCalc("lumped_cap"));
|
||||
}
|
||||
|
||||
// Parasitic analysis pts
|
||||
TEST_F(StaInitTest, SetParasiticAnalysisPts) {
|
||||
// setParasiticAnalysisPts removed from API
|
||||
// setParasiticAnalysisPts removed from API
|
||||
}
|
||||
|
||||
// RemoveClockGroupsNull removed — nullptr now throws std::logic_error
|
||||
|
||||
// FindReportPathField
|
||||
|
|
@ -1892,12 +1886,6 @@ TEST_F(StaInitTest, CornersBeginEnd) {
|
|||
EXPECT_EQ(static_cast<size_t>(count), corners.size());
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, CornersOperatingConditionsChanged) {
|
||||
// operatingConditionsChanged removed from SceneSeq
|
||||
// No crash
|
||||
|
||||
}
|
||||
|
||||
// Levelize.cc uncovered functions
|
||||
TEST_F(StaInitTest, LevelizeNotLevelized) {
|
||||
Levelize *levelize = sta_->levelize();
|
||||
|
|
@ -2119,13 +2107,6 @@ TEST_F(StaInitTest, ClkSkewPaths) {
|
|||
EXPECT_EQ(skew.tgtPath(), nullptr);
|
||||
}
|
||||
|
||||
// ClkSkews class
|
||||
TEST_F(StaInitTest, ClkSkewsExists) {
|
||||
// ClkSkews is a component of Sta
|
||||
// Access through sta_ members
|
||||
|
||||
}
|
||||
|
||||
// CheckMaxSkews
|
||||
TEST_F(StaInitTest, CheckMaxSkewsExists) {
|
||||
// maxSkewSlack/maxSkewViolations removed from Sta API
|
||||
|
|
@ -2282,13 +2263,6 @@ TEST_F(StaInitTest, ReportPathFormatValues) {
|
|||
static_cast<int>(ReportPathFormat::slack_only));
|
||||
}
|
||||
|
||||
// Variables - additional variables
|
||||
TEST_F(StaInitTest, VariablesSearchPreamble) {
|
||||
// Search preamble requires network but we can test it won't crash
|
||||
// when there's no linked design
|
||||
|
||||
}
|
||||
|
||||
// Sta::clear on empty
|
||||
TEST_F(StaInitTest, StaClearEmpty) {
|
||||
sta_->clear();
|
||||
|
|
@ -2300,12 +2274,6 @@ TEST_F(StaInitTest, StaClearEmpty) {
|
|||
// (skipping because requires linked design)
|
||||
|
||||
// Additional Sta functions that exercise uncovered code paths
|
||||
TEST_F(StaInitTest, StaSearchPreambleNoDesign) {
|
||||
// searchPreamble requires ensureLinked which needs a network
|
||||
// We can verify the pre-conditions
|
||||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaTagCount) {
|
||||
TagIndex count = sta_->tagCount();
|
||||
EXPECT_GE(count, 0u);
|
||||
|
|
@ -2336,11 +2304,6 @@ TEST_F(StaInitTest, StaMaxPathCountVertex) {
|
|||
}
|
||||
|
||||
// More Sta.cc function coverage
|
||||
TEST_F(StaInitTest, StaSetSlewLimitClock) {
|
||||
// Without a clock this is a no-op - just exercise code path
|
||||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaOperatingConditions) {
|
||||
const OperatingConditions *op = sta_->operatingConditions(MinMax::min(), sta_->cmdSdc());
|
||||
(void)op;
|
||||
|
|
@ -2354,11 +2317,6 @@ TEST_F(StaInitTest, StaDelaysInvalidEmpty) {
|
|||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaFindRequiredsEmpty) {
|
||||
// Without timing, this should be a no-op
|
||||
// findRequireds removed from public Sta API
|
||||
}
|
||||
|
||||
// Additional Property types coverage
|
||||
TEST_F(StaInitTest, PropertyValuePwrActivity) {
|
||||
PwrActivity activity;
|
||||
|
|
@ -2454,18 +2412,6 @@ TEST_F(StaInitTest, StaClearLogicConstants) {
|
|||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaSetParasiticAnalysisPtsNotPerCorner) {
|
||||
// setParasiticAnalysisPts removed from API
|
||||
// No crash
|
||||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaSetParasiticAnalysisPtsPerCorner) {
|
||||
// setParasiticAnalysisPts removed from API
|
||||
// No crash
|
||||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaDeleteParasitics) {
|
||||
sta_->deleteParasitics();
|
||||
// No crash on empty
|
||||
|
|
@ -2493,14 +2439,6 @@ TEST_F(StaInitTest, WnsSlackLessConstructor) {
|
|||
|
||||
}
|
||||
|
||||
// Additional Sta.cc report functions
|
||||
TEST_F(StaInitTest, StaReportPathEndHeaderFooter) {
|
||||
// reportPathEndHeader removed from API
|
||||
// reportPathEndFooter removed from API
|
||||
// Just exercise without crash
|
||||
|
||||
}
|
||||
|
||||
// Sta.cc - make functions already called by makeComponents,
|
||||
// but exercising the public API on the Sta
|
||||
|
||||
|
|
@ -2621,24 +2559,6 @@ TEST_F(StaInitTest, StaMakeExceptionTo) {
|
|||
EXPECT_EQ(to, nullptr);
|
||||
}
|
||||
|
||||
// Sta.cc - checkTiming
|
||||
TEST_F(StaInitTest, StaCheckTimingNoDesign) {
|
||||
// checkTiming requires a linked network - just verify the method exists
|
||||
|
||||
}
|
||||
|
||||
// Exercise Sta.cc setPvt without instance
|
||||
TEST_F(StaInitTest, StaSetPvtMinMax) {
|
||||
// Can't call without instance/design, but verify the API exists
|
||||
// setPvt removed from public Sta API
|
||||
}
|
||||
|
||||
// Sta.cc - endpoint-related functions
|
||||
TEST_F(StaInitTest, StaEndpointViolationCountNoDesign) {
|
||||
// Requires graph, skip
|
||||
// endpointViolationCount removed from public Sta API
|
||||
}
|
||||
|
||||
// Additional coverage for SceneSeq iteration
|
||||
TEST_F(StaInitTest, CornersRangeForIteration) {
|
||||
const SceneSeq &corners = sta_->scenes();
|
||||
|
|
@ -3039,11 +2959,6 @@ TEST_F(StaInitTest, StaEnsureClkArrivals) {
|
|||
EXPECT_THROW(sta_->ensureClkArrivals(), std::exception);
|
||||
}
|
||||
|
||||
// startpointPins() is declared in Sta.hh but not defined - skip
|
||||
TEST_F(StaInitTest, StaStartpointPins) {
|
||||
// startpointPins not implemented
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaEndpoints2) {
|
||||
EXPECT_THROW(sta_->endpoints(), std::exception);
|
||||
}
|
||||
|
|
@ -3091,18 +3006,6 @@ TEST_F(StaInitTest, StaSetReportPathFormat2) {
|
|||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaReportPathEndHeader) {
|
||||
// reportPathEndHeader removed from API
|
||||
// No crash
|
||||
|
||||
}
|
||||
|
||||
TEST_F(StaInitTest, StaReportPathEndFooter) {
|
||||
// reportPathEndFooter removed from API
|
||||
// No crash
|
||||
|
||||
}
|
||||
|
||||
// --- Sta.cc: operating conditions ---
|
||||
TEST_F(StaInitTest, StaSetOperatingConditions) {
|
||||
sta_->setOperatingConditions(nullptr, MinMaxAll::all(), sta_->cmdSdc());
|
||||
|
|
@ -3284,11 +3187,6 @@ TEST_F(StaInitTest, StaRemoveDelaySlewAnnotations) {
|
|||
|
||||
}
|
||||
|
||||
// --- Sta.cc: minPeriodViolations and maxSkewViolations (throw) ---
|
||||
TEST_F(StaInitTest, StaMinPeriodViolationsThrows) {
|
||||
// minPeriodViolations removed from API;
|
||||
}
|
||||
|
||||
// minPeriodSlack removed from API
|
||||
TEST_F(StaInitTest, StaMinPeriodReportThrows) {
|
||||
EXPECT_THROW(sta_->reportMinPeriodChecks(nullptr, 10, false, false, sta_->scenes()), std::exception);
|
||||
|
|
|
|||
|
|
@ -52,7 +52,6 @@ Sorted correctly: 0
|
|||
Warning 502: search_path_enum_deep.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
grouped epc 5: 14
|
||||
--- report_checks epc 3 -fields ---
|
||||
Warning 168: search_path_enum_deep.tcl line 1, unknown field nets.
|
||||
Warning 502: search_path_enum_deep.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -65,10 +64,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
1 0.89 0.00 0.00 1.00 v in2 (in)
|
||||
in2 (net)
|
||||
0.00 0.00 1.00 v and1/A2 (AND2_X1)
|
||||
1 0.88 0.01 0.02 1.02 v and1/ZN (AND2_X1)
|
||||
n1 (net)
|
||||
0.01 0.00 1.02 v buf1/A (BUF_X1)
|
||||
1 1.05 0.01 0.02 1.05 v buf1/Z (BUF_X1)
|
||||
n2 (net)
|
||||
0.01 0.00 1.05 v reg1/D (DFFR_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
|
|
@ -96,10 +98,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
1 0.87 0.00 0.00 1.00 v in1 (in)
|
||||
in1 (net)
|
||||
0.00 0.00 1.00 v and1/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.02 1.02 v and1/ZN (AND2_X1)
|
||||
n1 (net)
|
||||
0.01 0.00 1.02 v buf1/A (BUF_X1)
|
||||
1 1.05 0.01 0.02 1.05 v buf1/Z (BUF_X1)
|
||||
n2 (net)
|
||||
0.01 0.00 1.05 v reg1/D (DFFR_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
|
|
@ -127,10 +132,13 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 ^ input external delay
|
||||
1 0.97 0.00 0.00 1.00 ^ in2 (in)
|
||||
in2 (net)
|
||||
0.00 0.00 1.00 ^ and1/A2 (AND2_X1)
|
||||
1 0.97 0.01 0.03 1.03 ^ and1/ZN (AND2_X1)
|
||||
n1 (net)
|
||||
0.01 0.00 1.03 ^ buf1/A (BUF_X1)
|
||||
1 1.13 0.01 0.02 1.05 ^ buf1/Z (BUF_X1)
|
||||
n2 (net)
|
||||
0.01 0.00 1.05 ^ reg1/D (DFFR_X1)
|
||||
1.05 data arrival time
|
||||
|
||||
|
|
@ -158,8 +166,10 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFFR_X1)
|
||||
2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1)
|
||||
n3 (net)
|
||||
0.01 0.00 0.10 ^ buf2/A (BUF_X1)
|
||||
1 0.00 0.00 0.02 0.12 ^ buf2/Z (BUF_X1)
|
||||
out1 (net)
|
||||
0.00 0.00 0.12 ^ out1 (out)
|
||||
0.12 data arrival time
|
||||
|
||||
|
|
@ -186,8 +196,10 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg2/CK (DFFR_X1)
|
||||
1 0.97 0.01 0.10 0.10 ^ reg2/Q (DFFR_X1)
|
||||
n5 (net)
|
||||
0.01 0.00 0.10 ^ buf3/A (BUF_X1)
|
||||
1 0.00 0.00 0.02 0.11 ^ buf3/Z (BUF_X1)
|
||||
out2 (net)
|
||||
0.00 0.00 0.11 ^ out2 (out)
|
||||
0.11 data arrival time
|
||||
|
||||
|
|
@ -214,8 +226,10 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFFR_X1)
|
||||
2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1)
|
||||
n3 (net)
|
||||
0.01 0.00 0.08 v buf2/A (BUF_X1)
|
||||
1 0.00 0.00 0.02 0.11 v buf2/Z (BUF_X1)
|
||||
out1 (net)
|
||||
0.00 0.00 0.11 v out1 (out)
|
||||
0.11 data arrival time
|
||||
|
||||
|
|
@ -242,6 +256,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.50 0.50 ^ input external delay
|
||||
2 3.56 0.00 0.00 0.50 ^ rst (in)
|
||||
rst (net)
|
||||
0.00 0.00 0.50 ^ reg1/RN (DFFR_X1)
|
||||
0.50 data arrival time
|
||||
|
||||
|
|
@ -269,6 +284,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.50 0.50 ^ input external delay
|
||||
2 3.56 0.00 0.00 0.50 ^ rst (in)
|
||||
rst (net)
|
||||
0.00 0.00 0.50 ^ reg2/RN (DFFR_X1)
|
||||
0.50 data arrival time
|
||||
|
||||
|
|
@ -296,6 +312,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFFR_X1)
|
||||
2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1)
|
||||
n3 (net)
|
||||
0.01 0.00 0.10 ^ reg2/D (DFFR_X1)
|
||||
0.10 data arrival time
|
||||
|
||||
|
|
@ -323,6 +340,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFFR_X1)
|
||||
2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1)
|
||||
n3 (net)
|
||||
0.01 0.00 0.08 v reg2/D (DFFR_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ puts "grouped epc 5: [llength $paths_g]"
|
|||
# report_checks with endpoint_count (text output)
|
||||
############################################################
|
||||
puts "--- report_checks epc 3 -fields ---"
|
||||
report_checks -path_delay max -endpoint_count 3 -fields {slew cap input_pins nets fanout}
|
||||
report_checks -path_delay max -endpoint_count 3 -fields {slew cap input_pins net fanout}
|
||||
|
||||
puts "--- report_checks epc 3 -format end ---"
|
||||
report_checks -path_delay max -endpoint_count 3 -format end
|
||||
|
|
|
|||
|
|
@ -536,8 +536,7 @@ Path Type: max
|
|||
7.88 slack (MET)
|
||||
|
||||
|
||||
--- report_checks -fields nets ---
|
||||
Warning 168: search_report_path_types.tcl line 1, unknown field nets.
|
||||
--- report_checks -fields net ---
|
||||
Startpoint: rst (input port clocked by clk)
|
||||
Endpoint: reg1 (recovery check against rising-edge clock clk)
|
||||
Path Group: asynchronous
|
||||
|
|
@ -549,6 +548,7 @@ Path Type: max
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.50 0.50 ^ input external delay
|
||||
0.00 0.50 ^ rst (in)
|
||||
rst (net)
|
||||
0.00 0.50 ^ reg1/RN (DFFR_X1)
|
||||
0.50 data arrival time
|
||||
|
||||
|
|
@ -576,7 +576,9 @@ Path Type: max
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFFR_X1)
|
||||
0.10 0.10 ^ reg1/Q (DFFR_X1)
|
||||
n3 (net)
|
||||
0.02 0.12 ^ buf2/Z (BUF_X1)
|
||||
out1 (net)
|
||||
0.00 0.12 ^ out1 (out)
|
||||
0.12 data arrival time
|
||||
|
||||
|
|
@ -648,7 +650,6 @@ Fanout Delay Time Description
|
|||
|
||||
|
||||
--- report_checks -fields all ---
|
||||
Warning 168: search_report_path_types.tcl line 1, unknown field nets.
|
||||
Startpoint: rst (input port clocked by clk)
|
||||
Endpoint: reg1 (recovery check against rising-edge clock clk)
|
||||
Path Group: asynchronous
|
||||
|
|
@ -660,6 +661,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.50 0.50 ^ input external delay
|
||||
2 3.56 0.10 0.00 0.50 ^ rst (in)
|
||||
rst (net)
|
||||
0.10 0.00 0.50 ^ reg1/RN (DFFR_X1)
|
||||
0.50 data arrival time
|
||||
|
||||
|
|
@ -687,8 +689,10 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFFR_X1)
|
||||
2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1)
|
||||
n3 (net)
|
||||
0.01 0.00 0.10 ^ buf2/A (BUF_X1)
|
||||
1 0.00 0.00 0.02 0.12 ^ buf2/Z (BUF_X1)
|
||||
out1 (net)
|
||||
0.00 0.00 0.12 ^ out1 (out)
|
||||
0.12 data arrival time
|
||||
|
||||
|
|
@ -705,7 +709,6 @@ Fanout Cap Slew Delay Time Description
|
|||
|
||||
|
||||
--- report_checks min -fields all ---
|
||||
Warning 168: search_report_path_types.tcl line 1, unknown field nets.
|
||||
Startpoint: rst (input port clocked by clk)
|
||||
Endpoint: reg1 (removal check against rising-edge clock clk)
|
||||
Path Group: asynchronous
|
||||
|
|
@ -717,6 +720,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.50 0.50 ^ input external delay
|
||||
2 3.56 0.10 0.00 0.50 ^ rst (in)
|
||||
rst (net)
|
||||
0.10 0.00 0.50 ^ reg1/RN (DFFR_X1)
|
||||
0.50 data arrival time
|
||||
|
||||
|
|
@ -744,6 +748,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFFR_X1)
|
||||
2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1)
|
||||
n3 (net)
|
||||
0.01 0.00 0.08 v reg2/D (DFFR_X1)
|
||||
0.08 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -69,17 +69,17 @@ report_checks -path_delay max -fields {cap}
|
|||
puts "--- report_checks -fields input_pins ---"
|
||||
report_checks -path_delay max -fields {input_pins}
|
||||
|
||||
puts "--- report_checks -fields nets ---"
|
||||
report_checks -path_delay max -fields {nets}
|
||||
puts "--- report_checks -fields net ---"
|
||||
report_checks -path_delay max -fields {net}
|
||||
|
||||
puts "--- report_checks -fields fanout ---"
|
||||
report_checks -path_delay max -fields {fanout}
|
||||
|
||||
puts "--- report_checks -fields all ---"
|
||||
report_checks -path_delay max -fields {slew cap input_pins nets fanout}
|
||||
report_checks -path_delay max -fields {slew cap input_pins net fanout}
|
||||
|
||||
puts "--- report_checks min -fields all ---"
|
||||
report_checks -path_delay min -fields {slew cap input_pins nets fanout}
|
||||
report_checks -path_delay min -fields {slew cap input_pins net fanout}
|
||||
|
||||
############################################################
|
||||
# report_checks with -digits
|
||||
|
|
|
|||
|
|
@ -67,6 +67,21 @@ proc diff_files_sorted { file1 file2 } {
|
|||
}
|
||||
}
|
||||
|
||||
proc assert_file_nonempty { path } {
|
||||
if { ![file exists $path] || [file size $path] <= 0 } {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains { path token } {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if { [string first $token $text] < 0 } {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc diff_files { file1 file2 { ignore "" } } {
|
||||
set stream1 [open $file1 r]
|
||||
set stream2 [open $file2 r]
|
||||
|
|
|
|||
|
|
@ -13,12 +13,12 @@ DIFF_FILE="${RESULT_DIR}/${TEST_NAME}.diff"
|
|||
mkdir -p "${RESULT_DIR}"
|
||||
|
||||
# Run test, merge stderr into stdout, capture to log.
|
||||
${STA_EXE} -no_init -no_splash -exit ${TEST_NAME}.tcl > ${LOG_FILE} 2>&1
|
||||
"${STA_EXE}" -no_init -no_splash -exit "${TEST_NAME}.tcl" > "${LOG_FILE}" 2>&1
|
||||
sta_exit=$?
|
||||
|
||||
if [ $sta_exit -ne 0 ]; then
|
||||
echo "Error: sta exited with code ${sta_exit}"
|
||||
cat ${LOG_FILE}
|
||||
cat "${LOG_FILE}"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
|
|
@ -28,10 +28,10 @@ if [ ! -f "${TEST_NAME}.ok" ]; then
|
|||
exit 1
|
||||
fi
|
||||
|
||||
if diff ${TEST_NAME}.ok ${LOG_FILE} > ${DIFF_FILE} 2>&1; then
|
||||
if diff "${TEST_NAME}.ok" "${LOG_FILE}" > "${DIFF_FILE}" 2>&1; then
|
||||
exit 0
|
||||
else
|
||||
echo "FAIL: output differs from ${TEST_NAME}.ok"
|
||||
cat ${DIFF_FILE}
|
||||
cat "${DIFF_FILE}"
|
||||
exit 1
|
||||
fi
|
||||
|
|
|
|||
|
|
@ -1,2 +0,0 @@
|
|||
--- processor_count ---
|
||||
Error: util_report_redirect.tcl, 11 invalid command name "processor_count"
|
||||
|
|
@ -69,7 +69,6 @@ Path Type: min
|
|||
|
||||
No paths found.
|
||||
No paths found.
|
||||
Warning 168: verilog_const_concat.tcl line 1, unknown field nets.
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -81,8 +80,10 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
2 2.34 10.00 0.00 0.00 v in2 (in)
|
||||
in2 (net)
|
||||
10.00 0.00 0.00 v or_const/A1 (OR2_X1)
|
||||
1 1.06 0.33 2.85 2.85 v or_const/ZN (OR2_X1)
|
||||
n2 (net)
|
||||
0.33 0.00 2.85 v reg2/D (DFF_X1)
|
||||
2.85 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ report_checks -from [get_ports in1] -to [get_ports out1]
|
|||
|
||||
report_checks -from [get_ports in2] -to [get_ports out2]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Write verilog
|
||||
|
|
|
|||
|
|
@ -106,7 +106,6 @@ No paths found.
|
|||
din[2]->dout[2]: done
|
||||
No paths found.
|
||||
din[3]->dout[3]: done
|
||||
Warning 168: verilog_error_paths.tcl line 1, unknown field nets.
|
||||
Startpoint: din[1] (input port clocked by clk)
|
||||
Endpoint: reg_b0 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -118,14 +117,19 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.88 0.10 0.00 0.00 v din[1] (in)
|
||||
din[1] (net)
|
||||
0.10 0.00 0.00 v buf1/A (BUF_X1)
|
||||
4 4.36 0.01 0.06 0.06 v buf1/Z (BUF_X1)
|
||||
stage2[1] (net)
|
||||
0.01 0.00 0.06 v sub1/and_inner/A1 (AND2_X1)
|
||||
1 0.88 0.01 0.03 0.09 v sub1/and_inner/ZN (AND2_X1)
|
||||
sub1/n1 (net)
|
||||
0.01 0.00 0.09 v sub1/buf_inner/A (BUF_X1)
|
||||
1 0.89 0.00 0.02 0.12 v sub1/buf_inner/Z (BUF_X1)
|
||||
wide1[0] (net)
|
||||
0.00 0.00 0.12 v and_b0/A2 (AND2_X1)
|
||||
1 1.06 0.01 0.03 0.14 v and_b0/ZN (AND2_X1)
|
||||
wide2[0] (net)
|
||||
0.01 0.00 0.14 v reg_b0/D (DFF_X1)
|
||||
0.14 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ foreach from_idx {0 1 2 3} {
|
|||
puts "din\[$from_idx\]->dout\[$from_idx\]: done"
|
||||
}
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Fanin/fanout through hierarchy and assigns
|
||||
|
|
|
|||
|
|
@ -3,21 +3,6 @@
|
|||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path] || [file size $path] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Write constant/concat design
|
||||
# Exercises: writeChildren with constant pin connections
|
||||
|
|
|
|||
|
|
@ -2,21 +2,6 @@
|
|||
# Exercises: verilogPortDir for tristate/supply, writePortDcls
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path] || [file size $path] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Write supply/tristate design (special port directions)
|
||||
# Exercises: verilogPortDir for tristate/supply, writePortDcls
|
||||
|
|
|
|||
|
|
@ -65,7 +65,6 @@ Path Type: min
|
|||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
Warning 168: verilog_preproc_param.tcl line 1, unknown field nets.
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -77,12 +76,16 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
1 0.89 0.10 0.00 0.00 v d2 (in)
|
||||
d2 (net)
|
||||
0.10 0.00 0.00 v ps1/g1/A2 (AND2_X1)
|
||||
2 1.94 0.01 0.07 0.07 v ps1/g1/ZN (AND2_X1)
|
||||
n1 (net)
|
||||
0.01 0.00 0.07 v buf1/A (BUF_X1)
|
||||
2 1.96 0.01 0.03 0.09 v buf1/Z (BUF_X1)
|
||||
n4 (net)
|
||||
0.01 0.00 0.09 v or1/A2 (OR2_X1)
|
||||
1 1.06 0.01 0.05 0.14 v or1/ZN (OR2_X1)
|
||||
n6 (net)
|
||||
0.01 0.00 0.14 v reg3/D (DFF_X1)
|
||||
0.14 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -53,7 +53,7 @@ report_checks -from [get_ports d3] -to [get_ports q2]
|
|||
|
||||
report_checks -from [get_ports d1] -to [get_ports q3]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Write verilog and verify
|
||||
|
|
|
|||
|
|
@ -2,27 +2,6 @@
|
|||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_not_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
|
|
|
|||
|
|
@ -3,27 +3,6 @@
|
|||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_not_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
|
|
|
|||
|
|
@ -2,27 +2,6 @@
|
|||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_not_has_cell {path cell_name} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
|
|
|
|||
|
|
@ -2,27 +2,6 @@
|
|||
source ../../test/helpers.tcl
|
||||
suppress_msg 1140
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_not_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
|
|
|
|||
|
|
@ -5,21 +5,6 @@
|
|||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path] || [file size $path] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test: Read verilog with specify blocks and parameters
|
||||
#---------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -101,7 +101,6 @@ Path Type: max
|
|||
|
||||
|
||||
No paths found.
|
||||
Warning 168: verilog_supply_tristate.tcl line 1, unknown field nets.
|
||||
Startpoint: in3 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -113,6 +112,7 @@ Fanout Cap Slew Delay Time Description
|
|||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
2 2.61 10.00 0.00 0.00 v in3 (in)
|
||||
in3 (net)
|
||||
10.00 0.00 0.00 v reg3/D (DFF_X1)
|
||||
0.00 data arrival time
|
||||
|
||||
|
|
|
|||
|
|
@ -71,7 +71,7 @@ report_checks -from [get_ports in3] -to [get_ports out3]
|
|||
|
||||
report_checks -from [get_ports in3] -to [get_ports {outbus[0]}]
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
report_checks -fields {slew cap input_pins net fanout}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: report_net for assign-related nets
|
||||
|
|
|
|||
|
|
@ -2,27 +2,6 @@
|
|||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
|
|
|
|||
|
|
@ -2,21 +2,6 @@
|
|||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path] || [file size $path] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog verilog_assign_test.v
|
||||
link_design verilog_assign_test
|
||||
|
|
|
|||
|
|
@ -2,21 +2,6 @@
|
|||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path] || [file size $path] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_files_equal {path_a path_b} {
|
||||
set in_a [open $path_a r]
|
||||
set text_a [read $in_a]
|
||||
|
|
|
|||
|
|
@ -2,21 +2,6 @@
|
|||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path] || [file size $path] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_files_equal {path_a path_b} {
|
||||
set in_a [open $path_a r]
|
||||
set text_a [read $in_a]
|
||||
|
|
|
|||
|
|
@ -1,27 +1,6 @@
|
|||
# Test verilog writer options
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
read_verilog verilog_test1.v
|
||||
link_design verilog_test1
|
||||
|
|
|
|||
|
|
@ -2,21 +2,6 @@
|
|||
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path] || [file size $path] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
|
||||
read_verilog ../../test/verilog_attribute.v
|
||||
link_design counter
|
||||
|
|
|
|||
|
|
@ -1,27 +1,6 @@
|
|||
# Test advanced verilog writer options - ASAP7 design
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 1: Write verilog from ASAP7 design (has more complexity)
|
||||
#---------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -1,27 +1,6 @@
|
|||
# Test advanced verilog writer options - Write after modification
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Write after network modification
|
||||
#---------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -1,27 +1,6 @@
|
|||
# Test advanced verilog writer options - Nangate45 write
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Write verilog for Nangate45 design
|
||||
#---------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -1,27 +1,6 @@
|
|||
# Test advanced verilog writer options - Sky130 with attributes
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
proc assert_file_nonempty {path} {
|
||||
if {![file exists $path]} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string length $text] <= 0} {
|
||||
error "expected non-empty file: $path"
|
||||
}
|
||||
}
|
||||
|
||||
proc assert_file_contains {path token} {
|
||||
set in [open $path r]
|
||||
set text [read $in]
|
||||
close $in
|
||||
if {[string first $token $text] < 0} {
|
||||
error "expected '$token' in $path"
|
||||
}
|
||||
}
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Write verilog for sky130 design with attributes
|
||||
#---------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Reference in New Issue