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write_verilog bus ports missing bits

This commit is contained in:
James Cherry 2019-12-09 16:57:18 -07:00
parent a52877451d
commit 435bc2ba98
1 changed files with 16 additions and 12 deletions
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28
network/ConcreteLibrary.cc
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@ -318,6 +318,7 @@ public:
~BusPort(); ~BusPort();
const char *name() const { return name_; } const char *name() const { return name_; }
void pushMember(ConcretePort *port); void pushMember(ConcretePort *port);
void setFrom(int from);
void setTo(int to); void setTo(int to);
int from() const { return from_; } int from() const { return from_; }
int to() const { return to_; } int to() const { return to_; }
@ -357,6 +358,12 @@ BusPort::pushMember(ConcretePort *port)
members_->push_back(port); members_->push_back(port);
} }
void
BusPort::setFrom(int from)
{
from_ = from;
}
void void
BusPort::setTo(int to) BusPort::setTo(int to)
{ {
@ -376,10 +383,9 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
// Remove bus bit ports from the ports_ vector during the scan by // Remove bus bit ports from the ports_ vector during the scan by
// keeping an index to the next insertion index and skipping over // keeping an index to the next insertion index and skipping over
// the ones we want to remove. // the ones we want to remove.
int port_index = 0; ConcretePortSeq ports = ports_;
ConcretePortSeq::Iterator port_iter(ports_); ports_.clear();
while (port_iter.hasNext()) { for (ConcretePort *port : ports) {
ConcretePort *port = port_iter.next();
const char *port_name = port->name(); const char *port_name = port->name();
char *bus_name; char *bus_name;
int index; int index;
@ -389,7 +395,9 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
if (!port->isBusBit()) { if (!port->isBusBit()) {
BusPort *bus_port = port_map.findKey(bus_name); BusPort *bus_port = port_map.findKey(bus_name);
if (bus_port) { if (bus_port) {
bus_port->setTo(index); // Treat it as [max:min]/[from:to], ie downto.
bus_port->setFrom(std::max(index, bus_port->from()));
bus_port->setTo(std::min(index, bus_port->to()));
stringDelete(bus_name); stringDelete(bus_name);
} }
else { else {
@ -399,13 +407,11 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
bus_port->pushMember(port); bus_port->pushMember(port);
} }
else else
ports_[port_index++] = port; ports_.push_back(port);
} }
else else
ports_[port_index++] = port; ports_.push_back(port);
} }
// Resize to forget the ports that didn't make the cut.
ports_.resize(port_index);
// Make the bus ports. // Make the bus ports.
BusPortMap::Iterator bus_iter(port_map); BusPortMap::Iterator bus_iter(port_map);
@ -418,9 +424,7 @@ ConcreteCell::groupBusPorts(const char bus_brkt_left,
port->setDirection(bus_port->direction()); port->setDirection(bus_port->direction());
delete bus_port; delete bus_port;
ConcretePortSeq::Iterator member_iter(members); for (ConcretePort *port : *members) {
while (member_iter.hasNext()) {
ConcretePort *port = member_iter.next();
char *bus_name; char *bus_name;
int index; int index;
parseBusName(port->name(), bus_brkts_left, bus_brkts_right, escape_, parseBusName(port->name(), bus_brkts_left, bus_brkts_right, escape_,